CN114461010A

CN114461010A - Circuit for simultaneously accessing FPGA GTY bank to 4-path clock and implementation method

Info

Publication number: CN114461010A
Application number: CN202111578409.8A
Authority: CN
Inventors: 孙静; 宋猛; 武岩
Original assignee: Tianjin Optical Electrical Communication Technology Co Ltd
Current assignee: Tianjin Optical Electrical Communication Technology Co Ltd
Priority date: 2021-12-22
Filing date: 2021-12-22
Publication date: 2022-05-10
Anticipated expiration: 2041-12-22
Also published as: CN114461010B

Abstract

The invention relates to a circuit for enabling FPGAGTYbank to access 4 clocks simultaneously and an implementation method thereof, wherein the circuit comprises a local crystal oscillator G1, an FPGA chip U1 and a clock chip U2, the clock chip U2 is provided with 4 DPLLs, the FPGAGTYbank supports two-way clock input, and the clock at the clock input end of the adjacent GTYbank can be used as the input clock thereof based on the clock borrowing characteristic of the GTYbank, so that the GTY bank of the FPGA chip U1 has 4 clock inputs, and can process 4 high-speed signals matched with the clock frequency. The circuit is simple, and 4 paths of clocks can be provided simultaneously; the problem of simultaneous processing of various signals is solved, and the requirements of high-speed signals on synchronous and asynchronous clocks can be met simultaneously.

Description

Circuit for simultaneously accessing FPGA GTY bank to 4-path clock and implementation method

Technical Field

The invention relates to a clock circuit, in particular to a circuit for simultaneously accessing FPGAGTYbank to 4 paths of clocks and an implementation method.

Technical Field

With the continuous forward development of optical communication technology, the transmission signal rate is upgraded from the original 2.5Gbps and 10Gbps to 40Gbps and 100Gbps, and the corresponding interface specification and processing protocol are continuously perfected and used. The signal format gradually transits from the conventional SDH signal to the ethernet signal and the OTN signal. Also, with the advancement of ethernet technology, ethernet signals are increasingly being used more widely. However, under the background of continuous development of emerging technologies such as big data and cloud computing, OTN signals with high speed and large bandwidth increasingly become an indispensable signal format in a communication link.

The existing communication link has original SDH signal, ethernet signal, and emerging OTN signal, and a situation of coexistence of multiple rate signals occurs. Each signal has a different signal rate, a different protocol, and a different clock frequency necessary to process data. Usually, different interface boards are used to distinguish different signal rates to complete the input and output of signals. Due to different processed signal rates and different clocks, the hardware circuits of each interface board are inconsistent and cannot be used universally. Therefore, the processing complexity is increased, the equipment cost is wasted, and huge workload is brought to line scheduling and data analysis in the communication machine room.

Disclosure of Invention

In view of the problems in the prior art, the invention provides a circuit and an implementation method for enabling FPGAGTYbank to simultaneously access 4 clocks, under the condition of not changing any hardware circuit, 3 continuous gtybaks with an FPGA can simultaneously access 4 clocks, and the specific technical scheme is that the circuit for enabling FPGAGTYbank to simultaneously access 4 clocks comprises a local crystal oscillator G1, an FPGA chip U1 and a clock chip U2, and is characterized in that: the clock chip U2 is a programmable low-jitter clock chip with 4 DPLLs and supporting 4 input ends and 4 output ends, the local crystal oscillator G1 outputs an asynchronous clock and is connected with the 1 input end of the clock chip U2,

3 interfaces of the FPGA chip U1 output synchronous clocks which are connected to the other 3 input ends of the clock chip U2, 4 output ends of the clock chip U2 output 4 clocks, and 3 continuous GTYbank clock input interfaces of the FPGA chip U1 are connected.

The method for implementing the FPGAGTYbank circuit simultaneously accessing to the 4-way clock as claimed in claim 1, wherein: the GTY bank < n > of the FPGA chip U1 only has 2 clock input pins MGTREFCLK, two different clocks are input, 2 high-speed data signals corresponding to the two clock frequencies are processed according to the two clock frequencies, and based on the GTYbank clock borrowing characteristic of the FPGA chip U1, the GTY bank < n > of the FPGA chip U1 uses the clocks on the GTY bank < n-1>, GTY bank < n-2>, GTY bank < n +1> and GTY bank < n +2> clock input pins MGTREFCLK as input clocks, so that the GTY bank < n > of the FPGA chip U1 can process a plurality of high-speed data signals matched with the clock frequencies if the clocks have multi-path clock input, the clock chip U2 is a programmable low-jitter clock chip which is provided with 4 DPLLs and supports 4-path input and 4-path output, the local crystal oscillator G1 is used as the clock chip U2 to provide one path of input clocks, and mainly provide stable local clock sources for the clock chip U2, the clock chip U2 respectively outputs from 4 output ports and is respectively connected to GTY bank < n > of the FPGA chip U1, so that the GTY bank < n > of the FPGA chip U1 has 4 clock inputs and can process 4 high-speed data signals matched with the clock frequency, and similarly, the GTY bank < n-1> and GTY bank < n +1> of the FPGA chip U1 also have 4 clock inputs and can process 4 high-speed data signals matched with the clock frequency.

The invention has the technical effects that the clock circuit is simple, and 4 clocks with different frequencies can be provided at the same time; under the condition of not changing any hardware circuit, 3 continuous GTYbanks of the FPGA can be simultaneously accessed with 4 clocks, the problem of simultaneous processing of multiple signal rates is solved, and the requirements of high-speed data signals on synchronous clocks and asynchronous clocks can be simultaneously met.

Drawings

FIG. 1 is a block diagram of the circuit connections of the present invention;

fig. 2 is a schematic circuit diagram according to a first embodiment of the present invention.

Detailed Description

The invention is further illustrated by the following figures and examples.

Example one

As shown in fig. 1 and fig. 2, the circuit for enabling FPGAGTYbank to access to 4 clocks at the same time includes a local crystal G1, an FPGA chip U1, and a clock chip U2, where the model of the local crystal G1 is SIT9121AI-2D133e19.44t, the model of the FPGA chip U1 is XCVU9P-2FLGB104I, the model of the clock chip U2 is SI5347C _ D _ GM, and has 4 DPLLs, supporting a programmable low-jitter clock chip with 4 inputs and 4 outputs,

the 3 GTY banks of the FPGA respectively select bank125, bank126 and bank127, so that 3 continuous FPGAGTYbanks can be adaptively accessed to circuits with 4 clock frequencies, and the circuit connection relationship is as follows:

the 4 pins and the 5 pins of the local crystal oscillator G1 are connected with one ends of capacitors C2 and C3, the other ends of the capacitors C2 and C3 are connected with the 63 pins and the 64 pins of a clock chip U2, a resistor R3 is connected between the 63 pins and the 64 pins of the clock chip U2, the 6 pin of the local crystal oscillator G1 is connected with a power supply VCC _3V3, a capacitor C1 is connected between the power supply VCC _3V3 and GND in a bridging manner, the 1 pin and the 2 pin of the local crystal oscillator G1 are respectively connected with one ends of resistors R1 and R2, the other ends of the resistors R1 and R2 are connected with the power supply VCC _3V3, and the 3 pin of the local crystal oscillator G1 is connected with GND;

AY18 and BA18 pins of an FPGA chip U1 are connected with one ends of capacitors C4 and C5, the other ends of the capacitors C4 and C5 are connected with 1 pin and 2 pins of a clock chip U2, a bridge resistor R4 is connected between the 1 pin and the 2 pin of the clock chip U2, AW20 and AY20 pins of the FPGA chip U1 are connected with one ends of capacitors C6 and C7, the other ends of the capacitors C6 and C7 are connected with 14 pins and 15 pins of the clock chip U2, a bridge resistor R5 is connected between the 14 pin and the 15 pin of the clock chip U2, AV21 and AW21 pins of the FPGA chip U1 are connected with one ends of capacitors C8 and C9, the other ends of the capacitors C8 and C9 are connected with 61 pins and 62 pins of the clock chip U2, and a bridge resistor R6 is connected between the 61 pin and the 62 pin of the clock chip U2;

pins 24 and 23 of a clock chip U2 are connected with one ends of capacitors C10 and C11, the other ends of capacitors C10 and C10 are connected with pin AC 10 and pin AC 10 of FPGA chip U10, pins 38 and 37 of the clock chip U10 are connected with one ends of capacitors C10 and C10, the other ends of capacitors C10 and C10 are connected with pin W10 and pin W10 of FPGA chip U10, pins 45 and 44 of the clock chip U10 are connected with one ends of capacitors C10 and C10, the other ends of capacitors C10 and C10 are connected with pin U10 and pin U10 of FPGA chip U10, pins 51 and pin 50 of the clock chip U10 are connected with one ends of capacitors C10 and C10, and the other ends of C10 are connected with pin R10 and pin R10 of FPGA chip U10.

Principle of

The GTY bank < n > of the FPGA chip U1 only has 2 clock input pins MGTREFCLK, two different clocks can be input, 2 corresponding high-speed data signals can be processed according to the two clock frequencies, and based on the GTYbank clock borrowing characteristic of the FPGA chip U1, the GTY bank < n > of the FPGA chip U1 can use the clocks on the GTY bank < n-1>, GTY bank < n-2>, GTY bank < n +1>, GTY bank < n +2> clock input pins MGTREFCLK as input clocks, so that the GTY bank < n > of the FPGA chip U1 can process a plurality of high-speed data signals matched with the clock frequencies if a plurality of clock inputs exist, the clock chip U2 is a programmable low-jitter clock chip with 4 DPLLs and supporting 4 input and 4 output, and the local crystal oscillator U1 serves as the clock chip U2 to provide one input clock, the clock chip U2 mainly provides a stable local clock source for the clock chip U2 and can be used for generating an asynchronous system clock without special requirements, the FPGA chip U1 outputs 3 paths of clocks, the clocks are connected to the rest 3 paths of input pins of the clock chip U2, a recovery clock is mainly provided for the clock chip U2 and is used for generating clock signals according to synchronous requirements, the clock chip U2 respectively outputs from 4 output ports and is respectively connected to the GTY bank < n > of the FPGA chip U1, therefore, the GTY bank < n > of the FPGA chip U1 has 4 paths of clock input, 4 high-speed data signals matched with clock frequency can be processed, and similarly, the GTY bank < n-1> and the GTY bank < n +1> of the FPGA chip U1 also have 4 paths of clock input, and all 4 high-speed data signals matched with clock frequency can be processed.

Claims

1. A circuit for enabling FPGAGTYbank to access 4 paths of clocks simultaneously comprises a local crystal oscillator G1, an FPGA chip U1 and a clock chip U2, and is characterized in that: the clock chip U2 is a programmable low-jitter clock chip with 4 DPLLs and supports 4 input ends and 4 output ends, the local crystal oscillator G1 outputs an asynchronous clock and is connected to 1 input end of the clock chip U2, 3 interfaces of the FPGA chip U1 output a synchronous clock and are connected to the rest 3 input ends of the clock chip U2, 4 output ends of the clock chip U2 output 4 clocks and are connected to 3 continuous GTYbank clock input interfaces of the FPGA chip U1.

2. The method for implementing the FPGAGTYbank circuit simultaneously accessing to the 4-way clock as claimed in claim 1, wherein: the GTY bank < n > of the FPGA chip U1 only has 2 clock input pins MGTREFCLK, two different clocks are input, 2 high-speed data signals corresponding to the two clock frequencies are processed according to the two clock frequencies, and based on the GTYbank clock borrowing characteristic of the FPGA chip U1, the GTY bank < n > of the FPGA chip U1 uses the clocks on the GTY bank < n-1>, GTY bank < n-2>, GTY bank < n +1> and GTY bank < n +2> clock input pins MGTREFCLK as input clocks, so that the GTY bank < n > of the FPGA chip U1 processes various high-speed data signals matched with the clock frequencies if multiple clock inputs exist, the clock chip U2 is a programmable low-jitter clock chip with 4 DPLLs and supporting 4 inputs and 4 outputs, the local crystal oscillator G1 serves as the clock chip U2 to provide one input clock and stable local clock sources for the U2, the clock chip U2 respectively outputs from 4 output ports and is respectively connected to GTY bank < n > of the FPGA chip U1, so that the GTY bank < n > of the FPGA chip U1 has 4 clock inputs for processing 4 high-speed data signals matched with the clock frequency, and similarly, the GTY bank < n-1> and the GTY bank < n +1> of the FPGA chip U1 also have 4 clock inputs for processing 4 high-speed data signals matched with the clock frequency.