CN114460882A - Incremental encoder pulse detection circuit based on programmable logic array - Google Patents
Incremental encoder pulse detection circuit based on programmable logic array Download PDFInfo
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- CN114460882A CN114460882A CN202210128118.7A CN202210128118A CN114460882A CN 114460882 A CN114460882 A CN 114460882A CN 202210128118 A CN202210128118 A CN 202210128118A CN 114460882 A CN114460882 A CN 114460882A
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- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
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Abstract
A pulse detection circuit based on a programmable logic array incremental encoder belongs to the technical field of encoder detection and comprises an optocoupler receiving circuit, a programmable logic array, a microprocessor and an LCD display system. According to the invention, because the pulse counting of the A, B pulse signal and the zero position signal Z latching and zero clearing function circuit are all completed by the programmable logic array hardware circuit, the detection of high-speed pulse counting is really realized by replacing an MCU program low-speed detection algorithm by a high-speed hardware circuit, and the method can be widely applied to the field of pulse detection of an incremental encoder with high pulse, high precision and high rotating speed, and provides standard measurement and verification for developing the incremental encoder with higher subdivision rate.
Description
Technical Field
The invention belongs to the technical field of encoder detection, and particularly relates to a pulse detection circuit based on a programmable logic array incremental encoder.
Background
The incremental encoder converts displacement into a periodic analog electrical signal, and then converts the analog electrical signal into an incremental A, B, Z pulse signal for feeding back relative angle information or speed information. Wherein A is a pulse signal generated by clockwise rotation of the incremental encoder, B is a pulse signal generated by counterclockwise rotation of the incremental encoder, and Z is a zero pulse signal.
The existing incremental detection device usually uses an internal counter of a microprocessor or an external interrupt to determine the number of pulses of one cycle of an encoder. Due to the limitation of corresponding time of external interruption of the microprocessor, when the number of incremental pulses reaches over one hundred thousand levels, the jump edge change of the zero pulse Z or A, B pulse signal cannot be captured, so that the counting detection cannot be carried out.
Therefore, there is a need in the art for a new solution to solve this problem.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the pulse detection circuit based on the programmable logic array incremental encoder is used for solving the technical problem that the existing incremental detection device cannot capture the jump edge change of a zero pulse Z or A, B pulse signal, so that the counting detection cannot be carried out.
A pulse detection circuit based on a programmable logic array incremental encoder comprises an optical coupler receiving circuit, a programmable logic array, a microprocessor and an LCD display system, wherein the optical coupler receiving circuit correspondingly converts a received pulse signal A generated by clockwise rotation of a measured incremental encoder, a received pulse signal B generated by counterclockwise rotation of the measured incremental encoder and a received zero pulse signal Z into 3.3V TTL level signals A0, B0 and Z0 and inputs the signals into the programmable logic array;
the programmable logic array comprises two 32-bit pulse capture counters, a 32-bit adder, four 8-bit latches and a logic output circuit, and is used for increasing and decreasing the count of pulse signals which rotate clockwise or anticlockwise of the incremental encoder to be tested and clearing the received zero pulse signals Z; the two 32-bit pulse capture counters receive output signals A0, B0 and Z0 of the optical coupling receiving circuit, and the two 32-bit pulse capture counters are used for up-down counting of pulse signals which rotate clockwise or anticlockwise of the incremental encoder to be measured respectively; the input end of the 32-bit adder is respectively connected with the output ends of the two 32-bit pulse capture counters, the 32-bit adder is used for merging the data of the two 32-bit pulse capture counters, and the output end of the 32-bit adder is respectively connected with the input ends of the four 8-bit latches; the four 8-bit latches are also connected with a zero clearing output end of a zero pulse signal Z of the programmable logic array, and the four 8-bit latches are used for synchronously latching the current counting data of the 32-bit adder under the condition of acquiring the zero pulse signal Z input; the input end of the logic output circuit is respectively connected with the output ends of the four 8-bit latches and output signals A0, B0 and Z0 of the optocoupler receiving circuit, and the logic output circuit splits the 32-bit output signals of the four 8-bit latches into 4 8-bit time-sharing reading output interface circuits; the microprocessor is electrically connected with the output end of the logic output circuit and the LCD display system respectively.
The 8-bit latch adopts 74373 tri-state buffer output 8-bit latch.
A decoder 74138 is also employed in the logic output circuit.
Through the design scheme, the invention can bring the following beneficial effects:
according to the invention, because the pulse counting of the A, B pulse signal and the zero pulse signal Z latching and zero clearing function circuit are all completed by the programmable logic array hardware circuit, the detection of high-speed pulse counting is really realized by replacing an MCU program low-speed detection algorithm by a high-speed hardware circuit, the method can be widely applied to the field of pulse detection of an incremental encoder with high pulse, high precision and high rotating speed, and provides standard measurement and verification for developing an incremental encoder with higher subdivision rate.
Drawings
The invention is further described with reference to the following figures and detailed description:
fig. 1 is a block diagram of an incremental detection apparatus in the prior art.
FIG. 2 is a block diagram of a pulse detection circuit of an incremental encoder based on a programmable logic array according to the present invention.
FIG. 3 is a circuit diagram of an optical transceiver circuit in a pulse detection circuit of an incremental encoder based on a programmable logic array according to the present invention.
FIG. 4 is a schematic diagram of the circuit connection between two 32-bit pulse capture counters and a 32-bit adder in a pulse detection circuit based on an incremental encoder of a programmable logic array according to the present invention.
FIG. 5 is a schematic diagram of the circuit connection of four 8-bit latches in the pulse detection circuit of the incremental encoder based on the programmable logic array according to the present invention.
FIG. 6 is a schematic diagram of the connection of the logic output circuit in the pulse detection circuit based on the incremental encoder of the programmable logic array according to the present invention.
FIG. 7 is a schematic diagram of the circuit connection of a microprocessor in the pulse detection circuit based on the incremental encoder of the programmable logic array according to the present invention.
FIG. 8 is a schematic diagram of the circuit connections of an LCD display system in the pulse detection circuit based on the incremental encoder of the programmable logic array according to the present invention.
In the figure, a 1-optical coupling receiving circuit, a 2-programmable logic array, a 3-microprocessor, a 4-LCD display system, a circuit with 5-four 8-bit latches and a 6-logic output circuit are adopted.
Detailed Description
As shown in the figure, the pulse detection circuit based on the incremental encoder of the programmable logic array comprises an optical coupler receiving circuit 1, a programmable logic array 2, a microprocessor 3 and an LCD display system 4, wherein the optical coupler receiving circuit 1 adopts two TLP2168 photoelectric couplers to correspondingly convert a pulse signal a generated by clockwise rotation, a pulse signal B generated by counterclockwise rotation and a zero pulse signal Z of the received incremental encoder to 3.3VTTL level signals a0, B0 and Z0 and inputs the signals to the programmable logic array 2;
the programmable logic array 2 comprises two 32-bit pulse capture counters, a 32-bit adder, four 8-bit latches and a logic output circuit 6, and the programmable logic array 2 is used for increasing and decreasing the count of pulse signals which rotate clockwise or anticlockwise of the incremental encoder to be tested and clearing the received zero-bit pulse signals Z; the two 32-bit pulse capture counters receive output signals A0, B0 and Z0 of the optical coupling receiving circuit 1, and the two 32-bit pulse capture counters are respectively used for performing corresponding count increasing or count decreasing on pulse signals when the detected incremental encoder rotates clockwise or anticlockwise; the input ends of the 32-bit adders are respectively connected with the output ends q [31..0] of the two 32-bit pulse capture counters in a one-to-one correspondence mode, the 32-bit adders are used for merging data of the two 32-bit pulse capture counters, and the output ends result [31..0] of the 32-bit adders split every 8 data into one group and are sequentially connected with the input ends of the four 8-bit latches in a corresponding mode; the four 8-bit latches are also connected with a zero clearing output end Z/, of a zero pulse signal Z of the programmable logic array 2, the four 8-bit latches are used for synchronously latching the current counting data of the 32-bit adder under the condition that the zero pulse signal Z is acquired as input, and circuits 5 of the four 8-bit latches are shown in FIG. 5; the input end of the logic output circuit 6 is respectively connected with the output ends of the four 8-bit latches and the output signals A0, B0 and Z0 of the optocoupler receiving circuit 1, and the logic output circuit 6 splits the 32-bit output signals of the four 8-bit latches into 4 time-sharing reading output interface circuits with 8 bits; the microprocessor 3 is electrically connected to the output terminals D0-D7 of the logic output circuit 6 and the LCD display system 4, respectively.
The 8-bit latch adopts 74373 tri-state buffer output 8-bit latch.
A decoder 74138 is also employed in the logic output circuit 6.
The microprocessor 3 adopts a C8051F120 singlechip.
According to the circuit structure implementation shown in fig. 3, a pulse signal a generated by clockwise rotation of the incremental encoder to be tested, a pulse signal B generated by counterclockwise rotation of the incremental encoder to be tested, and a zero pulse signal Z are correspondingly received and converted by an optical coupler into 3.3V TTL level signals a0, B0, and Z0, and are input into the EPM570T100C5 programmable logic array 2.
The B0 signal is counted as in the circuit shown in fig. 4 using two 32-bit pulse capture counters as a 32-bit rising edge capture up counter array and a down counter array. Adding a counter array: when A0 is inverted to high, B0 is in a rising edge state, and the counter is increased by 1; decrementing the counter array: when the A0 is inverted to be high level, the B0 is in an inverted rising edge state, the counter is decremented by 1, and the function of positive and negative rotation, addition and subtraction and counting of the incremental encoder to be detected is realized. When Z0 is active high, the counter clears the current count value to 0 and counts again. The counting results of the two counters are synchronously input into a 32-bit adder to be combined with data, and are output into four 8-bit latch circuits together with a zero inverted signal.
As shown in fig. 5, when Z0 is active, the 4 8-bit latches latch the current count data synchronously to obtain the total number of pulses between two zero-bit pulse signals Z, i.e. the total number of pulses for one rotation of the incremental encoder.
As shown in fig. 6, the data logic output circuit 6 splits 32-bit data into 4 output interface circuits capable of being read in time and 8-bit data, so that the number of peripheral data connection interfaces is reduced, the connection with MCU chips such as a single chip microcomputer is facilitated, and resources are saved.
As shown in fig. 7 and 8, the display circuit is formed by the single chip microcomputer and the LCD12864, and the pulse count data of the programmable logic array is read, driven and displayed on the LCD12864 liquid crystal display, so that intuitive pulse detection data is obtained.
In the overall circuit, the connection nodes labeled the same in fig. 3 to 8 are electrically connected together.
Claims (4)
1. An incremental encoder pulse detection circuit based on a programmable logic array (2), which is characterized in that: the optical coupler receiving circuit (1) correspondingly converts a received pulse signal A generated by clockwise rotation of the incremental encoder to be detected, a received pulse signal B generated by counterclockwise rotation of the incremental encoder to be detected and a received zero pulse signal Z into 3.3V TTL level signals A0, B0 and Z0 and inputs the signals into the programmable logic array (2);
the programmable logic array (2) comprises two 32-bit pulse capture counters, a 32-bit adder, four 8-bit latches and a logic output circuit, and the programmable logic array (2) is used for increasing and decreasing the count of pulse signals which rotate clockwise or anticlockwise of the incremental encoder to be tested and clearing the received zero-bit pulse signals Z; the two 32-bit pulse capture counters receive output signals A0, B0 and Z0 of the optical coupling receiving circuit (1), and the two 32-bit pulse capture counters are used for up-down counting of pulse signals which rotate clockwise or anticlockwise of the incremental encoder to be measured respectively; the input end of the 32-bit adder is respectively connected with the output ends of the two 32-bit pulse capture counters, the 32-bit adder is used for merging the data of the two 32-bit pulse capture counters, and the output end of the 32-bit adder is respectively connected with the input ends of the four 8-bit latches; the four 8-bit latches are also connected with a zero clearing output end of a zero pulse signal Z of the programmable logic array (2), and the four 8-bit latches are used for synchronously latching the current counting data of the 32-bit adder under the condition of acquiring the zero pulse signal Z input; the input end of the logic output circuit is respectively connected with the output ends of the four 8-bit latches and output signals A0, B0 and Z0 of the optocoupler receiving circuit (1), and the logic output circuit splits the 32-bit output signals of the four 8-bit latches into 4 time-sharing reading output interface circuits with 8 bits; the microprocessor (3) is respectively electrically connected with the output end of the logic output circuit and the LCD display system (4).
2. A programmable logic array (2) based incremental encoder pulse detection circuit as claimed in claim 1, wherein: the 8-bit latch adopts 74373 tri-state buffer output 8-bit latch.
3. A programmable logic array (2) based incremental encoder pulse detection circuit as claimed in claim 1, wherein: a decoder 74138 is also employed in the logic output circuit.
4. A programmable logic array (2) based incremental encoder pulse detection circuit as claimed in claim 1, wherein: the microprocessor (3) adopts a C8051F120 singlechip.
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| CN202210128118.7A CN114460882A (en) | 2022-02-11 | 2022-02-11 | Incremental encoder pulse detection circuit based on programmable logic array |
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| CN202210128118.7A CN114460882A (en) | 2022-02-11 | 2022-02-11 | Incremental encoder pulse detection circuit based on programmable logic array |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005022126A1 (en) * | 2003-09-02 | 2005-03-10 | Chempaq A/S | A pulse height analyser |
| CN200959128Y (en) * | 2006-08-17 | 2007-10-10 | 贾良红 | Universal counter of incremental encoder |
| CN102200541A (en) * | 2010-03-24 | 2011-09-28 | 中国科学院自动化研究所 | Method and device for measuring rotating speed of motor |
| CN103616839A (en) * | 2013-12-13 | 2014-03-05 | 广西大学 | Field programmable gate array (FPGA)-based adaptive speed detection device |
| CN113443489A (en) * | 2020-03-27 | 2021-09-28 | 住友重机械工业株式会社 | Conveying system and input circuit |
-
2022
- 2022-02-11 CN CN202210128118.7A patent/CN114460882A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005022126A1 (en) * | 2003-09-02 | 2005-03-10 | Chempaq A/S | A pulse height analyser |
| CN200959128Y (en) * | 2006-08-17 | 2007-10-10 | 贾良红 | Universal counter of incremental encoder |
| CN102200541A (en) * | 2010-03-24 | 2011-09-28 | 中国科学院自动化研究所 | Method and device for measuring rotating speed of motor |
| CN103616839A (en) * | 2013-12-13 | 2014-03-05 | 广西大学 | Field programmable gate array (FPGA)-based adaptive speed detection device |
| CN113443489A (en) * | 2020-03-27 | 2021-09-28 | 住友重机械工业株式会社 | Conveying system and input circuit |
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