CN114448431A - 集成电感电容振荡器及其方法 - Google Patents
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- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1206—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification
- H03B5/1212—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
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- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
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- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1296—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the feedback circuit comprising a transformer
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- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
Abstract
一集成振荡器包含:一第一电感布局成一第一回路以及一第二电感布局成一第二回路;一第一电容布局于该第一回路的两端之间;一第二电容布局于该第二回路的两端之间;一第三电感、一第四电感、一第三电容以及一第四电容,皆布局于该第一回路内;以及一交错耦合晶体管对,用来在电性上耦接该第一回路的两端,并耦接该第二回路的两端。对一对称平面而言,该集成振荡器的整体结构是实质对称的。
Description
技术领域
本公开大体上涉及一电感电容(LC)振荡器,尤其涉及一LC振荡器具有降低的相位噪声。
背景技术
如图1所示,一电感电容(LC)振荡器100包含一第一LC腔110、一交错耦合对120与一第二LC腔130。该第一LC腔110包含电感111与电容112,用来于一共振频率下共振。该交错耦合对120包含两个NMOS(N通道金属氧化物半导体)晶体管121与122,并以一交错耦合形态被配置。该第二LC腔130包含电感131与电容132,用来于该第一LC腔100的共振频率的二倍下共振。该第一电感111的一中央抽头连接一电源供应节点“VDD”。该第一LC腔110决定一振荡频率,其大约等于该共振频率。该交错耦合对120提供一再生功能(regenerationfunction),以补偿该第一LC腔110的一欧姆损失(Ohmic loss),并维持该振荡。该第二LC腔130是用来提供该交错耦合对120的一源极衰退(source degeneration),以抑制该LC振荡器100的一相位噪声,其肇因于该交错耦合对120的闪烁噪声的升频(an up-conversion ofa flicker noise)。LC振荡器100为本领域所熟知,故在此不予赘述。
一种受关注的方案,是该LC振荡器100是通过一互补式金属氧化物半导体(CMOS)工艺集成于一硅基板上。这需要该LC振荡器100在布局上是紧凑(compact)的,且具有一低相位噪声;这也需要该LC振荡器100与其它电路之间的磁性耦合(magnetic coupling)能够被减轻,所述其它电路是共存于该硅基板上的电路。
本技术领域需要的是一集成LC振荡器,其在布局上是紧凑的,且具有一低相位噪声,同时减轻与其它电路的磁性耦合,所述其它电路是共存于同一硅基板上的电路。
发明内容
于本公开的一实施例中,一种集成振荡器包含:一第一电感,其布局成从一第一端至一第二端的一第一回路,对一对称平面而言,该第一回路是实质对称的;一第二电感,其布局成从一第三端至一第四端的一第二回路,该第三端连结该第一端,该第四端连结该第二端,对该对称平面而言,该第二回路是实质对称的;一第三电感,其布局成一逆时针螺旋状,该逆时针螺旋状的该第三电感位于该第一回路内,且处于该对称平面的一侧;一第四电感,其布局成一顺时针螺旋状,该顺时针螺旋状的该第四电感位于该第一回路内,对该对称平面而言,该第四电感为该第三电感的一镜像;一接地条,其沿着该对称平面被布局,以提供该第三电感与该第四电感的一共同终止处;一第一电容,其布局于该第一端与该第二端之间;一第二电容,其布局于该第三端与该第四端之间;一第三电容,其布局于该第三电感与该接地条之间;一第四电容,其布局于该第四电感与该接地条之间,对该对称平面而言,该第四电容为该第三电容的一镜像;以及一交错耦合晶体管对,用来在电性上交错耦接该第一端与该第二端。
于本公开的一实施例中,一种集成一振荡器的方法包含:对一对称平面而言,以一实质对称方式布局一第一电感成为从一第一端至一第二端的一第一回路;对该对称平面而言,以一实质对称方式布局一第二电感成为从一第三端至一第四端的一第二回路,该第三端连结该第一端,该第四端连结该第二端;布局一第三电感成为一逆时针螺旋状,该逆时针螺旋状的该第三电感位于该第一回路内,且处于该对称平面的一侧;布局一第四电感成为一顺时针螺旋状,该顺时针螺旋状的该第四电感位于该第一回路内,对该对称平面而言,该第四电感为该第三电感的一镜像;沿着该对称平面布局一接地条,以提供该第三电感与该第四电感的一共同终止处;布局一第一电容于该第一端与该第二端之间;布局一第二电容于该第三端与该第四端之间;布局一第三电容于该第三电感与该接地条之间;布局一第四电容于该第四电感与该接地条之间;以及布局一交错耦合晶体管对,以在电性上交错耦接该第一端与该第二端。
有关本发明的特征、实作与技术效果,兹配合附图作优选实施例详细说明如下。
附图说明
图1显示一LC振荡器的示意图;
图2A依据本公开的一实施例显示一集成LC振荡器的示意图;
图2B显示图2A的集成LC振荡器的布局的顶视图;以及
图3依据本公开显示一方法的流程图。
符号说明
100:LC振荡器
110:第一LC腔
120:交错耦合对
130:第二LC腔
111:电感
112:电容
121:NMOS晶体管
122:NMOS晶体管
131:电感
132:电容
VDD:电源供应节点
200:LC振荡器
201:第一节点
202:第二节点
203:第三节点
220:交错耦合对
L1:第一电感
L2:第二电感
L3:第三电感
L4:第四电感
C1:第一电容
C2:第二电容
C3:第三电容
C4:第四电容
M1:第一NMOS晶体管
M2:第二NMOS晶体管
VDD:电源供应节点
k13:第一互耦
k14:第二互耦
B200:说明方块
UTM:超厚金属
RDL:重布层
F1~F8:手指
S1:第一条带
v1_1、v1_2、v1_3、v1_4:第一组通孔
S2:第二条带
v2_1、v2_2、v2_3、v2_4:第二组通孔
L3_1:第一绕线圈
L3_2:第二绕线圈
L3_V:通孔
L4_1:第三绕线圈
L4_2:第四绕线圈
L4_V:通孔
M1n2:区域
C1_1、C1_2、C1_3、C1_4、C1_5、C1_6:第一电容C1的电容
C2_1、C2_2、C2_3、C2_4、C2_5、C2_6:第二电容C2的电容
GND:接地条
P200:对称平面
CT1:第一中央抽头位置
CT2:第二中央抽头位置
300:流程图
310~390:步骤
具体实施方式
本公开涉及电感电容(LC)振荡器。尽管本说明书公开了本公开的多个实施例可视为实施本发明的优选范例,但本发明可通过多种方式被实施,不限于后述的特定范例,也不限于用来实现该些特定范例的技术特征的特定方式。在其它情况下,已知的细节未被显示或说明,以避免妨碍呈现本公开的观点。
本技术领域技术人员可了解本公开所使用的与微电子相关的用语及基本概念,像是“电压”、“电流”、“振荡器”、“频率”、“共振(resonance)”、“电源供应”、“CMOS(互补式金属氧化物半导体)”、“NMOS(N通道金属氧化物半导体)”、“电感”、“电容”、“通孔(via)”、“交错耦合(cross couple)”、以及“绕线圈(coil)”。诸如此类的用语是用于微电子的文章中,且与其相关的概念对本领域技术人员而言是显而易知的,故它们的细节于此不再赘述。
本技术领域技术人员可识别出一电容符号、一电感符号、一互感耦合(mutualinductive coupling)符号,并能识别出一NMOS晶体管符号,且能识别其“源极”、“栅极”与“漏极”端。本技术领域技术人员可读懂一电路的图示包含元件像是电容、电感、NMOS晶体管等等,且不需要冗余的说明指出该图示中某个元件是如何连接到另一个元件。
本公开是用工程观念的字眼来表达。举例来说,关于两个变数X与Y,当提到“X等于Y”时,这表示“X大约等于Y”,亦即“X与Y之间的差异小于一特定的工程误差”;当提到“X为零”时,这表示“X大约为零”,亦即“X小于一特定的工程误差”;当提到“X甚小于Y(X issubstantially smaller than Y)”时,这表示“X对于Y而言是可忽略的”,亦即“X与Y之间的比值小于一工程误差,从而X相较于Y是可忽略的”。
一电源供应节点为一电压的一电路节点,该电压大约等于一电源供应电压,其高于零,但可能具有一微小的高频变化(small high-frequency fluctuation)。一接地节点为一电压的一电路节点,该电压大约为零,但可能具有一微小的高频变化。
本公开的全文里,“VDD”表示一电源供应节点。本公开中,根据那些对本技术领域技术人员而言是显而易见的文意,有时VDD是指该电源供应节点VDD的电压准位。举例而言,显而易见的是当我们说“VDD”为0.7V时,我们是在表达该电源供应节点VDD的电压准位为0.7V。
一电路是一晶体管、一电阻、一电感、一电容、及/或其它电子装置以一特定方式互连的集合体,用来实现一特定功能。
一电感包含一导电路径,通常是由一金属线(或走线(trace))来实现,该金属线(或走线)允许一电流流过,并引起一磁场。一电感通常是由一金属线(或走线)来实现,该金属线(或走线)是以具有两个开口端(open ends)的回路形态(loop topology)来配置,该两个开口端包含一第一端与一第二端,其中一电流能够从该第一端流到该第二端。一绕线圈是一电感包含一金属线(或走线),该金属线(或走线)以一多匝螺旋形态(multi-turnspiral topology)来配置。
一CMOS工艺技术允许集成多个晶体管、电容、电感,该些元件被布局于一多层结构中,并使用金属走线与金属层间通孔(inter-metal-layer vias)来互连。本公开的目的的一为使用一CMOS工艺技术来集成一LC振荡器具有一紧凑的布局面积,同时达到一低噪声的技术效果。一CMOS技术的多层结构包含一多晶硅层与多个金属层,该多个金属层包含一超厚金属(ultra-thick metal;UTM)层、一重布层(re-distribution layer;RDL)、以及多个下方金属层(lower metal layers)。举例而言,一28纳米1P7M(于一多层结构中有一多晶硅层、一UTM层、六个下方金属层、与一RDL)的CMOS技术被采用,然此并非本发明的实施限制。
依据本发明的一实施例,图2A示出一LC振荡器200的示意图。LC振荡器200是通过一28纳米(28nm)1P7M的CMOS技术以集成并制作于一硅基板上,上述做法如前所述仅是范例,非本发明的实施限制。LC振荡器200包含:一第一电感L1、一第二电感L2、一第三电感L3、一第四电感L4、一第一电容C1、一第二电容C2、一第三电容C3、一第四电容C4、以及一交错耦合对220包含一第一NMOS晶体管M1与一第二NMOS晶体管M2。该第一电感L1的一中央抽头(center tap)连接该电源供应节点“VDD”,举一非限制性的例子而言,VDD为0.7V。在该第一电感L1与该第三电感L3之间有一第一互耦(mutual coupling),以k13来标示;在该第一电感L1与该第四电感L4之间有一第二互耦,以k14来标示。就功能而言,LC振荡器200相似于图1的LC振荡器100。该第一电感L1与该第二电感L2都是置于一第一节点201与一第二节点202之间,因此它们是以并联方式连接,并共同地实现一单一电感如同图1的电感111。该第一电容C1与该第二电容C2都是置于该第一节点201与该第二节点202之间,因此它们是以并联方式连接,并共同地实现一单一电容的功能如同图1的电容112。该第三电感L3与该第四电感L4都是置于一第三节点203与一接地节点之间,因此它们是以并联方式连接,并共同地实现一单一电感的功能如同图1的电感131。该第三电容C3与该第二电容C4都是置于该第三节点203与该接地节点,并共同地实现一单一电容的功能如同图1的电容132。该交错耦合对220实现图1的交错耦合对120的功能。
简言之,电感111被分成两个平行电感L1与L2,而电感131被分成两个平行电感L3与L4。上述做法的优点说明于后。此外,LC振荡器200与图1的LC振荡器100之间的一主要差异为该第一互耦k13(该第一电感L1与该第三电感L3之间)以及该第二互耦k14(该第一电感L1与该第四电感L4之间)。于一实施例中,该第一电感L1与该第二电感L2是相同的,该第一电容C1与该第二电容C2是相同的,该第三电容C3与该第四电容C4是相同的,以及该第三电感L3与该第四电感L4是相同的。该第一互耦k13与该第二互耦k14在大小上是相同的,但在正负号(sign)上是相反的。
基于紧凑布局的目的,该第一电感L1、该第三电感L3与该第四电感L4被设置得相当靠近(in closed proximity),因此该第一互耦k13与该第二互耦k14相当强。然而,基于该第一互耦k13与该第二互耦k14在大小上是相等的但在正负号上是相反的,该第一互耦的效应k13抵消了该第二互耦k14的效应。借此方式,紧凑布局所引起的强烈互耦的效应可被减轻。
图2B显示LC振荡器200的布局的顶视图。方块B200中显示图示说明。该第一电感L1是以一回路形态布局于该UTM层上,带有两个叉合的多指端(two interdigitated multi-finger ends),包含一第一多指端与一第二多指端,该第一多指端包含手指F1与F3,该第二多指端包含手指F2与F4。该第二电感L2是以一回路形态布局于该UTM层上,带有两个叉合的多指端,包含一第三多指端与一第四多指端,该第三多指端包含手指F5与F7,该第四多指端包含手指F6与F8。该第一多指端电性连接该第三多指端,并实际上作为(effectivelyembodying)该第一节点201。该第二多指端电性连接该第四多指端,并实际上作为该第二节点202。于另一实施例中,LC电感进一步包含:一第一条带(strip)S1布局于该RDL上,以及一第一组通孔包含v1_1、v1_2、v1_3与v1_4,该些通孔用来连接手指F1、F3、F5与F7,因此它们在电性上短路,并以一分散方式(distributed manner)共同地实现该第一节点201;一第二条带S2布局于该RDL上,以及一第二组通孔包含v2_1、v2_2、v2_3与v2_4,该些通孔用来连接手指F2、F4、F6与F8,因此它们在电性上短路,并以一分散方式共同地实现该第二节点202。该第三电感L3与该第四电感L4是布局于该第一电感L1的回路内。该第三电感L3包含一第一绕线圈L3_1布局于该UTM层上,并包含一第二绕线圈L3_2布局于该RDL上,其中该第一绕线圈L3_1与该第二绕线圈L3_2是以一螺旋形态被布局,并以一逆时针方向成螺旋形,且通过一通孔L3_V而连接起来。该第四电感L4包含一第三绕线圈L4_1布局于该UTM层上,并包含一第四绕线圈L4_2布局于该RDL上,其中该第三绕线圈L4_1与该第四绕线圈L4_2是以一螺旋形态被布局,并以一顺时针方向成螺旋形,且通过一通孔L4_V而连接起来。
该第一NMOS晶体管M1与该第二NMOS晶体管M2是布局于标示为M1n2的区域内。该第一电容C1是以一分散方式被实现,并包含电容C1_1、C1_2、C1_3、C1_4、C1_5与C1_6。该第二电容C2也是以一分散方式被实现,并包含电容C2_1、C2_2、C2_3、C2_4、C2_5与C2_6。电容C1_1与C1_2是置于手指F1与F2之间。电容C1_3与C1_4是置于手指F2与F3之间。电容C1_5与C1_6是置于手指F3与F4之间。电容C2_1与C2_2是置于手指F5与F6之间。电容C2_3与C2_4是置于手指F6与F7之间。电容C2_5与C2_6是置于手指F7与F8之间。标示为“GND”的一接地带(ground strip)是布局于该UTM层上,以提供一共同终止处(common termination)给该第三电感L3与该第四电感L4,并实现一接地节点。值得注意的是,该第三电感L3与该第四电感L4也连接该第三节点203,如图2A与图2B所示。
对一对称平面(plane of symmetry)P200而言,该第三电感L3与该第四电感L4互为镜像(mirror images)。值得注意的是,从该顶视图来看,该对称平面P200看起来为一条线。该接地带GND是沿着该对称平面P200而被布局。对该对称平面P200而言,该第一电感L1与该第二电感L2实质地对称。基于该对称性,从该第三节点203流向该第三电感L3的电流相同于从该第三节点203流向该第四电感L4的电流,但该二电流以相反方向盘旋:前者是以一逆时针方向,而后者是以一顺时针方向。因此,该第二电感L3与该第一电感L1之间的互耦(亦即:k13)以及该第四电感L4与该第一电感L1之间的互耦(亦即:k14)在大小上会是相同的,但在正负号上是相反的。通过上述方式,以一紧密相邻方式(close proximity)布局该第三电感L3与该第四电感L4于该第一电感L1内所引起的一强烈磁性耦合的净效应(neteffect of a strong magnetic coupling)为零。
于一实施例中,图2B的每个电容(亦即:C1_1、C1_2等等)为一金属-氧化物-金属(MOM)电容,其包含多个叉合的手指于下方金属层(lower metal layers)中,并伴随多个通孔。MOM电容为现有技术,故在此不予详述。
将电感111分成平行的电感L1与L2的一个优点是:以一顺时针方式从该第一多指端流向该第二多指端的L1的一第一电流,总是会伴随着以一逆时针方式从该第三多指端流向该第四多指端的L2的一第二电流,因此由该第一电流所激发的磁场以及由该第二电流所激发的磁场会形成一闭回路,从而一磁通量可被限制。LC振荡器200与其它共存于同一硅基板上的任何电路之间的不需要的磁性耦合(undesired magnetic coupling)可被有效地减轻。
将电感131分成平行的电感L3与L4的一个优点是:L3与L4可被设置于L1的回路内,这使得一紧凑布局成为可能,同时避免与L1形成不需要的净耦(undesired netcoupling),这多亏了在布局上的对称性,其使得L1与L3之间的磁性耦合能够抵消L1与L4之间的磁性耦合。
LC振荡器200能够具有一低相位噪声,这多亏了电感L3、L4与电容C3、C4一起提供的源极衰退(source degeneration),如同LC振荡器100中电感131与电容132所提供的源极衰退。
如图2B所示,一第一中央抽头位置CT1是标注于该对称平面P200上该第一电感L1的一中点,而一第二中央抽头位置CT2是标注于该对称平面P200上该第二电感L2的一中点。如图2A所示,该电源供应节点“VDD”连接该第一电感L1的该中央抽头(亦即:图2B中的CT1)。于一替代实施例中(未显示于图2A),该电源供应节点“VDD”连接该第二电感L2的该中央抽头(亦即:图2B中的CT2),而非连接该第一电感L1的该中央抽头。于另一替代实施例中,该电源供应节点“VDD”连接该第一电感L1的该中央抽头,也连接该第二电感L2的该中央抽头。
该第一电感L1具有两个多指端(亦即:该第一多指端与该第二多指端),其相互叉合(interdigitated);这使得该第一电容C1能够以一分散方式(distributed manner)布局于该两个多指端之间,形成一紧凑的布局面积,同时该第一电感的部分布局面积被重复使用于布局该第一电容。上述做法也适用于该第二电感L2与该第二电容C2。虽然多指形态是有帮助的,但并非实施本发明的必要条件。
如图3的流程图300所示,依据本公开的一实施例,集成一振荡器的方法包含:(步骤310)对一对称平面而言,以一实质对称方式布局一第一电感成为从一第一端至一第二端的一第一回路;(步骤320)对该对称平面而言,以一实质对称方式布局一第二电感成为从一第三端至一第四端的一第二回路,该第三端连结该第一端,该第四端连结该第二端;(步骤330)布局一第三电感成为一逆时针螺旋状,该逆时针螺旋状的该第三电感位于该第一回路内,且处于该对称平面的一侧;(步骤340)布局一第四电感成为一顺时针螺旋状,该顺时针螺旋状的该第四电感位于该第一回路内,对该对称平面而言,该第四电感为该第三电感的一镜像;(步骤350)沿着该对称平面布局一接地条,以提供该第三电感与该第四电感的一共同终止处;(步骤360)布局一第一电容于该第一端与该第二端之间;(步骤370)布局一第二电容于该第三端与该第四端之间;(步骤380)布局一第三电容于该第三电感与该接地条之间,以及布局一第四电容于该第四电感与该接地条之间,对该对称平面而言,该第四电容为该第三电容的一镜像;以及(步骤390)布局一交错耦合晶体管对,以在电性上交错耦接该第一端与该第二端。
虽然本发明的实施例如上所述,然而该些实施例并非用来限定本发明,本技术领域技术人员可依据本发明的明示或隐含的内容对本发明的技术特征施以变化,凡此种种变化均可能属于本发明所寻求的专利保护范围,换言之,本发明的专利保护范围须视本说明书的权利要求所界定者为准。
Claims (10)
1.一种集成振荡器,包含:
一第一电感,其布局成从一第一端至一第二端的一第一回路,对一对称平面而言,该第一回路是对称的;
一第二电感,其布局成从一第三端至一第四端的一第二回路,该第三端连结该第一端,该第四端连结该第二端,对该对称平面而言,该第二回路是对称的;
一第三电感,其布局成一逆时针螺旋状,该逆时针螺旋状的该第三电感位于该第一回路内,且处于该对称平面的一侧;
一第四电感,其布局成一顺时针螺旋状,该顺时针螺旋状的该第四电感位于该第一回路内,对该对称平面而言,该第四电感为该第三电感的一镜像;
一接地条,其沿着该对称平面被布局,以提供该第三电感与该第四电感的一共同终止处;
一第一电容,其布局于该第一端与该第二端之间;
一第二电容,其布局于该第三端与该第四端之间;
一第三电容,其布局于该第三电感与该接地条之间;
一第四电容,其布局于该第四电感与该接地条之间,对该对称平面而言,该第四电容为该第三电容的一镜像;以及
一交错耦合晶体管对,用来在电性上交错耦接该第一端与该第二端。
2.如权利要求1所述的集成振荡器,其中该第一端属于一多指形态,包含一第一组手指;该第二端属于一多指形态,包含一第二组手指,该第二组手指与该第一组手指叉合;该第三端属于一多指形态,包含一第三组手指;该第四端属于一多指形态,包含一第四组手指,该第四组手指与该第三组手指叉合;该第一组手指、该第二组手指、该第三组手指与该第四组手指均垂直于该对称平面。
3.如权利要求2所述的集成振荡器,其中该第一电容以一分散方式布局于该第一组手指与该第二组手指之间,而该第二电容以一分散方式布局于该第三组手指与该第四组手指之间。
4.如权利要求2所述的集成振荡器,进一步包含:一第一连接条与一第一组通孔,用来在电性上将该第一组手指与该第三组手指短路在一起;以及一第二连接条与一第二组通孔,用来在电性上将该第二组手指与该第四组手指短路在一起。
5.如权利要求1所述的集成振荡器,其通过一互补式金属氧化物半导体工艺集成于一硅基板上,并包含一多层平面结构,该多层平面结构包含一超厚金属层、一重布层、多个下方金属层以及多个通孔层,该多个通孔层用于提供金属层间电性连接。
6.如权利要求5所述的集成振荡器,其中该第一电感是布局于该超厚金属层上。
7.如权利要求5所述的集成振荡器,其中该第二电感是布局于该超厚金属层上。
8.如权利要求5所述的集成振荡器,其中该第三电感包含:一第一绕线圈布局于该超厚金属层上;一第二绕线圈布局于该重布层上;以及一通孔位于该超厚金属层与该重布层之间,用来在电性上连接该第一绕线圈与该第二绕线圈。
9.如权利要求1所述的集成振荡器,其中该第一电感的一中央抽头是位于该对称平面,并在电性上连接一电源供应节点。
10.如权利要求1所述的集成振荡器,其中该第二电感的一中央抽头是位于该对称平面,并在电性上连接一电源供应节点。
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US10804847B2 (en) * | 2019-02-12 | 2020-10-13 | Apple Inc. | Harmonic trap for voltage-controlled oscillator noise reduction |
CN110971191B (zh) * | 2019-11-28 | 2022-12-13 | 中国电子科技集团公司第十三研究所 | 推推介质振荡器 |
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2020
- 2020-11-04 US US17/088,646 patent/US11075603B1/en active Active
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2021
- 2021-03-03 TW TW110107546A patent/TWI779508B/zh active
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