CN114446338A

CN114446338A - Memory, memory system and pre-charging method

Info

Publication number: CN114446338A
Application number: CN202210119196.0A
Authority: CN
Inventors: 贾信磊; 贾建权; 靳磊
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-02-08
Filing date: 2022-02-08
Publication date: 2022-05-06

Abstract

The embodiment of the application discloses a memory, a memory system and a pre-charging method, and belongs to the technical field of storage. The pre-charging method comprises the following steps: applying a precharge voltage to the source line connection terminal; applying a voltage to the gate of each memory cell in the memory cell stack; the voltage applied to the gate of the programmed memory cell is greater than the threshold voltage of the programmed memory cell, and the voltage applied to the gate of the unprogrammed memory cell is greater than the threshold voltage of the unprogrammed memory cell. The method can ensure that electrons in the doped region and electrons in the channel of the memory cell coupled with the selected word line are attracted to the source line connecting end sufficiently under the condition that a programmed memory cell exists in the memory cell stack, thereby realizing sufficient pre-charging of unselected memory strings and reducing programming interference on the memory cell coupled with the selected word line in the memory cell stack.

Description

Memory, memory system and pre-charging method

Technical Field

The embodiment of the application relates to the technical field of storage, in particular to a memory, a storage system and a pre-charging method.

Background

The memory generally comprises a plurality of memory strings, and in some embodiments, each memory string comprises a selection tube stack and a memory cell stack between a bit line connection terminal and a source line connection terminal, and the selection tube stack and the memory cell stack are connected through a doped region.

The related art precharges unselected memory strings among the plurality of memory strings in the following manner: a precharge voltage is applied to the source line connection of the unselected memory strings and 0V is applied to the gates of each memory cell in the memory cell stack.

When the above-mentioned method is used for precharging, if a programmed memory cell exists in the memory cell stack, the precharging is insufficient, so that the memory cell coupled with the selected word line in the memory cell stack is subjected to stronger program interference.

Disclosure of Invention

The embodiment of the application provides a memory, a memory system and a pre-charging method, which can be used for fully pre-charging unselected memory strings. The technical scheme is as follows:

in one aspect, embodiments of the present application provide a memory, which includes a memory array and peripheral circuits communicatively connected to the memory array;

the memory array comprises unselected memory strings, a selection tube stack and a memory cell stack are arranged between a bit line connecting end and a source line connecting end of each unselected memory string, the selection tube stack is connected with the memory cell stack through a doped region, and the memory cell stack comprises programmed memory cells and unprogrammed memory cells;

the peripheral circuit is configured to apply a precharge voltage to the source line connection terminal; applying a voltage to the gate of each memory cell in the memory cell stack; wherein the voltage applied to the gate of the programmed memory cell is greater than the threshold voltage of the programmed memory cell, and the voltage applied to the gate of the unprogrammed memory cell is greater than the threshold voltage of the unprogrammed memory cell.

In one possible implementation, the peripheral circuitry is configured to apply a first voltage to both the gates of the programmed memory cells and the gates of the unprogrammed memory cells, the first voltage being greater than a threshold voltage of the programmed memory cells.

In one possible implementation, the peripheral circuit is configured to apply a first voltage to the gate of the programmed memory cell, the first voltage being greater than the threshold voltage of the programmed memory cell, and a second voltage to the gate of the unprogrammed memory cell, the second voltage being greater than the threshold voltage of the unprogrammed memory cell and less than the first voltage.

In one possible implementation, the off-time of applying the first voltage to the gate of the programmed memory cell is earlier than the off-time of applying the precharge voltage to the source line connection terminal.

In one possible implementation, the number of programmed memory cells is plural; the off time for applying the first voltage to the gates of programmed memory cells that are further from the source line connection is no later than the off time for applying the first voltage to the gates of programmed memory cells that are closer to the source line connection.

In another aspect, a storage system is provided, the storage system comprising a memory and a controller coupled to the memory, the controller configured to control the memory;

the memory comprises a storage array and peripheral circuits communicatively connected with the storage array;

In another aspect, a pre-charging method is provided, the pre-charging method is used for pre-charging unselected memory strings, a select transistor stack and a memory cell stack are included between a bit line connection terminal and a source line connection terminal of the unselected memory strings, the select transistor stack and the memory cell stack are connected through a doped region, and the memory cell stack includes programmed memory cells and unprogrammed memory cells; the method comprises the following steps:

applying a precharge voltage to the source line connection terminal;

applying a voltage to the gate of each memory cell in the memory cell stack;

wherein the voltage applied to the gate of the programmed memory cell is greater than the threshold voltage of the programmed memory cell, and the voltage applied to the gate of the unprogrammed memory cell is greater than the threshold voltage of the unprogrammed memory cell.

In one possible implementation, the applying a voltage to the gate of each memory cell in the memory cell stack includes:

applying a first voltage to both the gate of the programmed memory cell and the gate of the unprogrammed memory cell, the first voltage being greater than the threshold voltage of the programmed memory cell.

applying a first voltage to a gate of the programmed memory cell, the first voltage being greater than a threshold voltage of the programmed memory cell;

applying a second voltage to the gate of the unprogrammed memory cell, the second voltage being greater than the threshold voltage of the unprogrammed memory cell and less than the first voltage.

The technical scheme provided by the embodiment of the application at least has the following beneficial effects:

according to the technical scheme provided by the embodiment of the application, on the basis of applying the pre-charging voltage to the source line connecting end, the voltages larger than the threshold voltages of the gates of the programmed memory cells and the gates of the unprogrammed memory cells in the memory cell stack are applied. In this way, when programmed memory cells exist in the memory cell stack, the channels of the memory cells in the memory cell stack are all ensured to be conductive, so that electrons in the doped region and electrons in the channels of the memory cells coupled with the selected word line are all attracted to the source line connecting end sufficiently, thereby realizing sufficient pre-charging of unselected memory strings, and being beneficial to reducing programming interference on the memory cells coupled with the selected word line in the memory cell stack.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of a system provided in an embodiment of the present application;

FIG. 2 is a schematic structural diagram of a memory card according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a solid-state drive according to an embodiment of the present application;

FIG. 4 is a schematic structural diagram of a memory according to an embodiment of the present disclosure;

FIG. 5 is a schematic cross-sectional view of a memory string provided by an embodiment of the present application;

FIG. 6 is a flow chart of a pre-charging method provided by an embodiment of the present application;

FIG. 7 is a schematic diagram of a voltage application provided by an embodiment of the present application;

fig. 8 is a flowchart of a precharging method provided in an embodiment of the present application.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

It should be noted that the terms "first," "second," and the like in this application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

It should be readily understood that the meaning of "on …", "above …" and "above …" in this disclosure should be interpreted in the broadest manner such that "on …" means not only "directly on something", but also includes the meaning of "on something" with intervening features or layers therebetween, and "above …" or "above …" means not only the meaning of "above something" or "above something", but may also include the meaning of "above something" or "above something" with no intervening features or layers therebetween (i.e., directly on something).

Furthermore, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or feature's relationship to another element or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations in use or operation of the device in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Fig. 1 is a schematic structural diagram of a system provided in an embodiment of the present application, and the system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having a memory therein.

As shown in fig. 1, the system 100 includes a host 101 and a storage system 102, the storage system 102 including one or more memories 103 and a controller 104.

The host 101 may be a Processor (e.g., a Central Processing Unit (CPU)) or a System on Chip (SoC) (e.g., an Application Processor (AP)) of an electronic device. The host 101 may be configured to send data to the memory 103. Alternatively, the host 101 may be configured to receive data from the memory 103.

The memory 103 may be any memory referred to in the embodiments of the present application. Optionally, the memory 103 is a flash memory, such as a Three Dimensional NAND (3D NAND) flash memory.

In some embodiments, controller 104 is coupled to memory 103 and host 101 and is configured to control memory 103. The controller 104 may manage data stored in the memory 103 and communicate with the host 101.

In some embodiments, the controller 104 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) Flash drive, or other media for use in electronic devices such as personal computers, Digital cameras, mobile phones, and the like.

In some embodiments, the controller 104 is designed to operate in a high duty cycle environment, such as a Solid State Drive (SSD) or an Embedded multimedia Card (eMMC). SSD or eMMC is used as a data store and enterprise storage array for mobile devices such as smart phones, tablet computers, laptop computers, and the like.

The controller 104 may be configured to control operations of the memory 103, e.g., read, erase, program operations, and so on. The controller 104 may also be configured to manage various functions with respect to data stored or to be stored in the memory 103, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, and the like. In some embodiments, the controller 104 is also configured to process an Error Correction Code (ECC) with respect to data read from the memory 103 or data written to the memory 103. The controller 104 may also perform any other suitable function, such as formatting the memory 103.

The controller 104 may communicate with an external device (e.g., the host 101) according to a particular communication protocol. For example, the controller 104 may communicate with the external device via at least one of various Interface protocols, including but not limited to USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire (Firewire) protocol, and the like.

The controller 104 and the one or more memories 103 may be integrated into various types of Storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the storage system 102 may be implemented and packaged into different types of end electronic products.

As shown in fig. 2, the controller 104 and the single memory 103 may be integrated into a memory card 200. The Memory Card 200 may include a PC (Personal Computer Memory Card International Association, PCMCIA, abbreviated PC) Card, a CF Card, a Smart Media (SM) Card, a Memory stick, a multimedia Card (MMC, RS-MMC (Reduced-Size-MMC, small multimedia Card), MMCmicro (micro multimedia Card)), an SD Card (SD, miniSD (small Secure Digital Memory Card), microSD (micro Secure Digital Memory Card), SDHC (Secure Digital High Capacity Card)), a UFS, and the like. Memory card 200 may also include a memory card connector 201 that couples memory card 200 with a host (e.g., host 101 in FIG. 1).

As shown in fig. 3, the controller 104 and the plurality of memories 103 may be integrated into the solid state drive 300. Solid state drive 300 may also include solid state drive connector 301 that couples solid state drive 300 with a host (e.g., host 101 in fig. 1). In some embodiments, the storage capacity and/or operating speed of the solid state drive 300 is greater than the storage capacity and/or operating speed of the memory card 200.

Fig. 4 shows a schematic structural diagram of a memory provided in an embodiment of the present application. As shown in fig. 4, memory 103 includes a memory array 410 and peripheral circuitry 420 communicatively coupled to memory array 410.

The memory array 410 includes a plurality of memory strings 411, the plurality of memory strings 411 being arranged in an array, the plurality of memory strings 411 being located on a carrying side of a substrate (not shown) and extending in a direction perpendicular to the carrying side of the substrate. By way of example, the substrate carrying surface is the surface that the substrate has for carrying the memory array 410.

Each memory string 411 includes a plurality of memory cells 412, and the plurality of memory cells 412 in each memory string 411 are stacked in a direction perpendicular to the substrate carrying surface. Each memory cell 412 has the function of storing data, the stored data being determined by the number of electrons stored by the memory cell 412, the number of electrons stored by the memory cell 412 being capable of determining the magnitude of the threshold voltage of the memory cell 412, and thus the threshold voltage of the memory cell 412 being capable of indicating the data stored by the memory cell 412. Illustratively, the memory cell 412 is a floating gate field effect transistor or a Charge Trap (Charge Trap) type field effect transistor.

For example, the memory Cell 412 may be a Single Level Cell (SLC), a Multiple Level Cell (MLC), a Triple Level Cell (TLC), a Quad Level Cell (QLC), or the like. SLC, MLC, TLC and QLC are capable of storing 1, 2, 3 and 4 bit data, respectively.

Each memory string 411 further comprises an upper Select Gate (TSG) 413 and a lower Select Gate 414(Bottom Select Gate, BSG), the upper Select gates 413 at the same height or at a similar height from the substrate carrying surface in different memory strings 411 being coupled to the same Drain Select Line (DSL) 430. The lower Select tubes 414 of different strings 411 are coupled to the same Source Select Line (SSL) 440 at the same height or a similar height from the substrate carrying surface. Wherein the upper selection pipe 413 and the lower selection pipe 414 are used to activate a selected memory string at the time of an erase or program operation. In some embodiments, upper select tube 413 is also referred to as a top select gate or drain select tube and lower select tube 414 is also referred to as a bottom select gate or source select tube. In some embodiments, between upper select pipe 413 and memory Cell 412, and between lower select pipe 414 and memory Cell 412, there is also a Dummy Cell (DC).

One end of each memory string 411 is coupled to a Bit Line (BL) 450, and the other end of each memory string 411 is coupled to a Source Line (SL) 460. Illustratively, the end coupled to the bit line 450 is referred to as a bit line connection end, and the end coupled to the source line 460 is referred to as a source line connection end.

The memory cells 412 in different memory strings 411 are at the same level with the same height or similar heights from the substrate carrying surface, and a plurality of memory cells 412 at the same level form a memory cell row 41a, i.e., the memory array 410 includes a plurality of memory cell rows respectively coupled to a plurality of Word Lines (WL) 470. By applying a voltage (V) to the word line 470 coupled to a row of memory cells_WL) Control of the individual memory cells in the row of memory cells can be achieved.

All memory strings 411 of the memory array 410 sharing a Common set of word lines 470 form a memory Block (Block)41b, and the Source connections of the memory strings 411 in the same memory Block 41b are illustratively coupled to a same Source Line 460, which Source Line 460 is also referred to as a Common Source Line (CSL).

Peripheral circuitry 420 may be coupled to memory array 410 through drain select line 430, source select line 440, bit line 450, source line 460, and word line 470. Peripheral circuitry 420 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory array 410 by applying voltage and/or current signals to memory cells 412 via drain select line 430, source select line 440, bit line 450, source line 460, and word line 470, and sensing voltage and/or current signals from memory cells 412.

The peripheral circuit 420 may include various types of peripheral circuits formed using Metal-Oxide-Semiconductor (MOS) technology. Peripheral circuitry 420 is capable of performing erase, program, read, or verify operations on memory strings 411 in memory array 410. In some embodiments, memory array 410 includes unselected memory strings and peripheral circuitry 420 is capable of precharging unselected memory strings in memory array 410 in accordance with the precharge scheme provided by embodiments of the present application.

Fig. 5 is a schematic cross-sectional view illustrating a memory string provided in an embodiment of the present application. As shown in fig. 5, the memory string 411 is located on the carrier side of the substrate 510, and the memory string 411 includes a select transistor stack 530 and a memory cell stack 520 between the bit line connection terminal and the source line connection terminal, and the memory cell stack 520 and the select transistor stack 530 are connected by a doped region 540. The cell stack 520 and the select tube stack 530 are stacked in a direction perpendicular to the substrate bearing surface, and the select tube stack 530 is located on a side of the cell stack 520 away from the substrate bearing surface. Illustratively, memory cell stack 520 is comprised of memory cells of memory string 411 and the BSG, and select pipe stack 530 is comprised of the TSG of memory string 411.

The material of the substrate 510 may be silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

Memory cell stack 520 may include alternating conductive layers 521 and dielectric layers 522. The material of the conductive layer 521 is a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. The conductive layer 521 may extend laterally to form the SSL 440 or the wordline 470.

As shown in fig. 5, memory cell stack 520 includes a channel structure that extends vertically through conductive layer 521 and dielectric layer 522. The channel structure of memory cell stack 520 includes channel 523, tunneling layer 524, memory layer 525, and blocking layer 526. The tunneling layer 524, the storage layer 525, and the blocking layer 526 may be referred to as functional layers. In some embodiments, the material of the channel 523 may be silicon, e.g., polysilicon. The material of the tunneling layer 524 may be silicon oxide, silicon oxynitride, or any combination thereof. The material of the memory layer 525 may be silicon nitride, silicon oxynitride, or any combination thereof, and the memory layer 525 may be a floating gate or a charge trap layer, for example. The material of barrier layer 526 may be silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In some embodiments, the channel structure of the memory cell stack 520 may have a pillar shape (e.g., a cylinder, a prism, a truncated cone, etc.), with the channel 523, the tunneling layer 524, the memory layer 525, and the barrier layer 526 being radially arranged in this order from the center of the pillar toward the outer surface of the pillar.

The selection tube stack 530 may include alternating conductive layers 531 and dielectric layers 532. The material of conductive layer 531 is a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. Conductive layer 531 may extend laterally to form DSL 430.

As shown in fig. 5, the select tube stack 530 includes a channel structure that extends vertically through the conductive layer 531 and the dielectric layer 532. The channel structure of select tube stack 530 includes channel 533 and insulating layer 534. In some embodiments, the material of the channel 533 may be silicon, e.g., polysilicon. The material of the insulating layer 534 may be silicon oxide. In some embodiments, the channel structure of the select tube stack 530 may have a pillar shape (e.g., a cylinder, a prism, a truncated cone, etc.), with the channels 533 and insulating layers 534 arranged radially in this order from the center of the pillar toward the outer surface of the pillar.

As shown in fig. 5, the size of the channel structure of the select tube stack 530 is smaller than that of the memory cell stack 520, which can reduce the space occupied by the channel structure of the select tube stack 530, thereby providing a larger process window for forming the top select gate notch structure, and thus increasing the unit memory density of the memory.

The select tube stack 530 and the memory cell stack 520 are connected by a doped region 540, the doped region 540 being formed by doping a semiconductor material with impurities, the material of the doped region 540 being, illustratively, a heavily N-doped material to enhance the conductivity of the doped region 540. Heavily doped means that the concentration of the impurity doped in the semiconductor material is greater than a concentration threshold, which is set empirically, orFlexibly adjusted according to the application scenario, e.g. concentration threshold of 10 per cubic centimeter¹⁸And (4) atoms. The doped region 540 is used to ensure that a tight coupling relationship is formed between the select tube stack 530 and the memory cell stack 520.

It should be understood that although not shown in fig. 5, the memory string 411 may also include other additional components including, but not limited to, gate line slits, source contacts, local contacts, interconnect layers, and the like.

The precharge method provided by the embodiment of the application is used for precharging unselected memory strings before programming the selected memory cells. In programming a selected memory cell, a programming voltage needs to be applied to the selected word line to tunnel electrons in the channel of the selected memory cell to the floating gate or charge trapping layer. However, the programming voltage may cause electron tunneling in the memory cells coupled to the selected word line in the unselected memory strings, that is, the memory cells coupled to the selected word line in the unselected memory strings are subjected to program disturb when the selected memory cells are programmed.

To reduce program disturb, unselected memory strings are precharged prior to programming selected memory cells to reduce program disturb on memory cells in the unselected memory strings coupled to the selected word line. In an exemplary embodiment, for ease of operation, in addition to precharging non-selected memory strings, a selected memory string in which a selected memory cell is located is precharged.

The precharge method provided by the embodiment of the application is used for precharging the unselected memory strings with the structure shown in fig. 5. That is, the non-selected memory strings include a select transistor stack and a memory cell stack between a bit line connection terminal and a source line connection terminal, and the select transistor stack and the memory cell stack are connected by a doped region. The memory cells in the unselected memory strings are all in a stack of memory cells, that is, the memory cells in the unselected memory strings that are coupled to the selected word line refer to the memory cells in the stack of memory cells that are coupled to the selected word line.

The large number of electrons present in the doped region reduces the channel potential of the memory cells in the memory cell stack of the non-selected memory string during programming, thereby enhancing the program disturb experienced by the memory cells in the memory cell stack. Illustratively, the more electrons in the doped region have an adverse effect on memory cells in the memory cell stack that are closer to the doped region.

Therefore, in precharging unselected memory strings, it is desirable to reduce electrons in the doped region in addition to reducing electrons in the channel of the memory cell coupled to the selected word line in the memory cell stack. Wherein reducing electrons in the channel of the memory cell coupled to the selected word line increases the channel potential coupled out of the memory cell coupled to the selected word line during programming, and wherein reducing electrons in the doped region decreases the decrease in the channel potential of the memory cell coupled to the selected word line by electrons in the doped region. By reducing electrons in the channel of the memory cell coupled with the selected word line and reducing electrons in the doped region, the memory cell coupled with the selected word line can have higher channel potential during programming, so that the voltage difference between the gate and the channel of the memory cell coupled with the selected word line is smaller, and the program interference of the memory cell coupled with the selected word line is further reduced.

Some embodiments precharge the unselected memory strings having the structure shown in fig. 5 in a manner that: a precharge voltage is applied to source line connection terminals of unselected memory strings, and a 0V voltage is applied to the gates of all memory cells in the memory cell stack. The inventor has found that the voltage of 0V is not sufficient to turn on the channel of the programmed memory cell, and if there is a programmed memory cell in the memory cell stack, it cannot be guaranteed that electrons in the doped region and electrons in the channel of the memory cell coupled to the selected word line are sufficiently attracted to the source line connection terminal, which easily results in insufficient pre-charge, and thus the memory cell coupled to the selected word line is subjected to serious program disturb.

As can be seen from the above analysis, it is difficult to precharge unselected memory strings more sufficiently by using the precharge approach in some embodiments, and therefore it is important to provide an approach that can precharge unselected memory strings more sufficiently.

The embodiment of the present application provides a precharge method, which is performed by the peripheral circuit 420 in the memory 103. The precharge method is used to precharge the unselected memory strings before programming the selected memory cells. The non-selected memory string comprises a selection tube stack and a memory cell stack between a bit line connecting end and a source line connecting end, the selection tube stack and the memory cell stack are connected through a doped region, and the memory cell stack comprises a programmed memory cell and an unprogrammed memory cell.

For a memory block, the process of programming according to the programming direction includes a plurality of programming phases, different programming phases correspond to different selected word lines, one programming phase is used for programming selected memory cells corresponding to the one programming phase, and the selected memory cells are memory cells needing to be written with data in the memory cells coupled with the selected word lines. Before each programming phase, there is a pre-charging phase, and the pre-charging phase is used for pre-charging the non-selected memory strings corresponding to the programming phases, that is, the non-selected memory strings corresponding to each programming phase need to be pre-charged before the selected memory cells corresponding to each programming phase are programmed.

The principle of precharging the unselected memory strings corresponding to each programming phase is the same, and the embodiments of the present application take any programming phase as an example for description, that is, the selected word line and the unselected memory strings in the embodiments of the present application refer to the selected word line and the unselected memory strings corresponding to any programming phase. It should be noted that the selected word lines in different programming phases are different, and the unselected memory strings in different programming phases may be the same or different.

It should be noted that the number of the unselected memory strings may be one or more, and the principle of precharging each unselected memory string is the same, the embodiment of the present application takes the number of the unselected memory strings as one example, and if the number of the unselected memory strings is multiple, the precharge method provided in the embodiment of the present application may be referred to implement the precharge of each unselected memory string.

As shown in fig. 6, the precharge method provided in the embodiment of the present application includes step 601 and step 602.

In step 601, a precharge voltage is applied to the source line connection.

The precharge voltage is capable of applying an electric field force directed toward the source line connection to electrons in the doped region and to electrons in the channel of the memory cell coupled to the selected word line. The embodiment of the present application does not limit the magnitude of the precharge voltage, and the precharge voltage is, for example, a certain voltage of 0 to 10V, for example, 2V.

In an exemplary embodiment, the source line connection is coupled to the SL, and the precharge voltage is applied to the source line connection by: a precharge voltage is applied to the SL coupled to the source line connection.

For example, during the process of precharging the unselected memory strings, the bit line connection terminal may be grounded, that is, a voltage of 0V is applied to the bit line connection terminal, and a voltage greater than 0V but less than the precharge voltage may also be applied to the bit line connection terminal.

In an exemplary embodiment, in the process of precharging the unselected memory strings, in addition to applying the precharge voltage to the source line connection terminal, a turn-on voltage needs to be applied to the gate of the select transistor (i.e., the BSG) on the source line connection terminal side to turn on the channel of the BSG, so as to prevent the BSG from blocking the movement of electrons toward the source line connection terminal. In an exemplary embodiment, the process of applying the turn-on voltage to the gate of the BSG is achieved by applying the turn-on voltage to the BSG-coupled SSL. The turn-on voltage is greater than the threshold voltage of the BSG. For example, if the threshold voltage of the BSG ranges from 1V to 4V, the on-state voltage may range from 5V to 15V.

In step 602, applying a voltage to a gate of each memory cell in the memory cell stack; the voltage applied to the gate of the programmed memory cell is greater than the threshold voltage of the programmed memory cell, and the voltage applied to the gate of the unprogrammed memory cell is greater than the threshold voltage of the unprogrammed memory cell.

The gate of the programmed memory cell and the gate of the unprogrammed memory cell in the memory cell stack are applied with voltages larger than respective threshold voltages, so that the channel of each memory cell in the memory cell stack can be conducted, that is, under the condition that the programmed memory cell exists in the memory cell stack, electrons in the doped region and electrons in the channel of the memory cell coupled with the selected word line can be ensured to be attracted to the source line connecting end sufficiently, and therefore sufficient pre-charging of the unselected memory strings is achieved.

The programmed memory cells refer to memory cells to which data is written, and the unprogrammed memory cells refer to memory cells to which data is not written.

Since the memory cell coupled to the selected word line in the memory cell stack is not written with data, an unprogrammed memory cell must exist in the memory cell stack. The embodiment of the present application is not limited to the case where programmed memory cells exist in the memory cell stack.

For example, taking the erase mode corresponding to the memory block in which the unselected memory string is located as an example of total erase, the case that the programmed memory cell exists in the memory cell stack includes: the programming direction is the forward programming direction (i.e., the direction from the source line connection to the bit line connection) and there are programmed memory cells between the memory cells coupled to the selected word line and the source line connection; alternatively, the programming direction is the reverse programming direction (i.e., the direction from the bit line connection to the source line connection) and there are programmed memory cells between the memory cells coupled to the selected word line and the bit line connection.

In the case where the erase method corresponding to the memory block in which the unselected memory string is located is full erase, any one of the programmed memory cells is a memory cell to which data is rewritten after erase. In some embodiments, the erase mode corresponding to the memory block in which the unselected memory string is located may also be a partial erase, in which case, any one of the programmed memory cells may be an un-erased memory cell or a memory cell in which data is rewritten after erase.

In an exemplary embodiment, an implementation of applying a voltage to a gate of each memory cell in a memory cell stack includes: a first voltage is applied to both the gates of programmed memory cells and the gates of unprogrammed memory cells. Wherein the first voltage is greater than a threshold voltage of the programmed memory cell.

Since the threshold voltage of the unprogrammed memory cell is less than the threshold voltage of the programmed memory cell, the channels of the memory cells in the memory cell stack can be guaranteed to be conductive by applying a first voltage greater than the threshold voltage of the programmed memory cell to both the gate of the programmed memory cell and the gate of the unprogrammed memory cell. The operation convenience of the implementation mode is high.

For example, the number of programmed memory cells is plural, the threshold voltages of different programmed memory cells may be different, and the first voltage is a voltage greater than the threshold voltage of each programmed memory cell. Illustratively, the threshold voltage of the programmed memory cell ranges from 0V to 5V, and correspondingly, the first voltage ranges from 5V to 7V.

Illustratively, the process of applying the first voltage to both the gates of the programmed memory cells and the gates of the unprogrammed memory cells is performed by applying the first voltage to both the word lines to which the programmed memory cells are coupled and the word lines to which the unprogrammed memory cells are coupled.

The magnitude relationship between the precharge voltage and the first voltage is not limited in the embodiments of the present application. In an exemplary embodiment, the precharge voltage is greater than the first voltage. Of course, the precharge voltage may also be less than the first voltage.

In an exemplary embodiment, an implementation of applying a voltage to the gate of each memory cell in a stack of memory cells includes: a first voltage is applied to the gate of a programmed memory cell and a second voltage is applied to the gate of an unprogrammed memory cell. The first voltage is greater than the threshold voltage of the programmed memory cell, and the second voltage is greater than the threshold voltage of the unprogrammed memory cell and less than the first voltage.

The second voltage can enable the channel of the non-programmed memory cell to be conducted and is smaller than the first voltage, and the first voltage and the second voltage are respectively applied to the grid of the programmed memory cell and the grid of the non-programmed memory cell, so that power resources can be saved on the basis of ensuring that the channel of each memory cell in the memory cell stack is conducted.

Illustratively, the second voltage is a default voltage continuously applied to the gate of the memory cell, that is, the gate of the unprogrammed memory cell is continuously applied with the second voltage, and the default voltage is greater than the threshold voltage of the unprogrammed memory cell and less than the first voltage. For example, the threshold voltage of the unprogrammed memory cell is a negative value, and the default voltage may be 0V.

Illustratively, the process of applying a first voltage to the gate of a programmed memory cell is accomplished by applying the first voltage to a word line to which the programmed memory cell is coupled; the process of applying the second voltage to the gate of the unprogrammed memory cell is accomplished by applying the second voltage to the word line to which the unprogrammed memory cell is coupled.

In an exemplary embodiment, taking the example that the first voltage and the second voltage are respectively applied to the gate of the programmed memory cell and the gate of the unprogrammed memory cell, and the second voltage is a default voltage continuously applied to the gate of the memory cell, the sequence of the off-time of applying the first voltage and the pre-charge voltage is defined to further improve the pre-charge effect. In an exemplary embodiment, a turn-off time for applying the first voltage to the gate of the programmed memory cell is earlier than a turn-off time for applying the precharge voltage to the source line connection terminal. Illustratively, upon reaching the off-time of the applied voltage, the voltage drops to a default voltage, illustratively 0V.

When the first voltage is applied to the grid of the programmed memory cell, part of electrons are adsorbed around the programmed memory cell, the off time of applying the first voltage to the grid of the programmed memory cell is earlier than the off time of applying the pre-charging voltage to the source line connecting end, and after the voltage applied to the grid of the programmed memory cell is reduced to 0V, the electrons adsorbed around the programmed memory cell can continuously migrate and diffuse towards the direction of the source line connecting end under the action of the electric field force provided by the pre-charging voltage, so that the pre-charging effect on the unselected memory strings is further improved.

In an exemplary embodiment, in addition to applying the precharge voltage to the source line connection terminal and the first voltage to the gate of the programmed memory cell, the turn-on voltage is applied to the gate of the BSG, and in this case, the turn-off time of applying the first voltage to the gate of the programmed memory cell is earlier than the turn-off time of applying the turn-on voltage to the gate of the BSG and the turn-off time of applying the precharge voltage to the source line connection terminal, so as to ensure sufficient precharge. Illustratively, the off time for applying the turn-on voltage to the gate of the BSG is no later than the off time for applying the precharge voltage to the source line connection terminal.

In an exemplary embodiment, in the case where the number of programmed memory cells is plural, the off time of applying the first voltage to the gate of the programmed memory cell distant from the source line connection terminal is not later than the off time of applying the first voltage to the gate of the programmed memory cell close to the source line connection terminal to ensure the precharge is sufficient. That is, the off-time for applying the first voltage to the gates of the respective programmed memory cells is the same; alternatively, the gate of the programmed memory cell farther from the source line connection terminal is applied with the first voltage for an earlier off-time.

It should be noted that, the above description only describes the sequence of the off time of the applied voltage by taking as an example that the first voltage and the second voltage are respectively applied to the gate of the programmed memory cell and the gate of the unprogrammed memory cell, and the second voltage is a default voltage continuously applied to the gate of the memory cell, and the embodiment of the present application is not limited thereto.

In an exemplary embodiment, in the case where the first voltage is applied to both the gate of the programmed memory cell and the gate of the unprogrammed memory cell, the off-time of applying the first voltage to the gate of the programmed memory cell and the off-time of applying the first voltage to the gate of the unprogrammed memory cell are earlier than the off-time of applying the precharge voltage to the source line connection terminal to ensure that the precharge is sufficient. Illustratively, the off-time of applying the first voltage to the gate of the memory cell farther from the source line connection terminal among the respective memory cells is not later than the off-time of applying the first voltage to the gate of the memory cell closer to the source line connection terminal to ensure sufficient precharging.

In an exemplary embodiment, in a case where the first voltage and the second voltage are applied to the gate of the programmed memory cell and the gate of the unprogrammed memory cell, respectively, and the second voltage is not a default voltage that is continuously applied to the gate of the memory cell, an off-time of applying the first voltage to the gate of the programmed memory cell and an off-time of applying the second voltage to the gate of the unprogrammed memory cell are earlier than an off-time of applying the precharge voltage to the source line connection terminal to ensure that the precharge is sufficient. Illustratively, the off-time for applying the respective voltages to the gates of the memory cells that are farther from the source line connection is not later than the off-time for applying the respective voltages to the gates of the memory cells that are closer to the source line connection to ensure that the precharging is sufficient. If the memory cell is a programmed memory cell, the corresponding voltage is a first voltage; if the memory cell is an unprogrammed memory cell, the corresponding voltage is the second voltage.

The embodiment of the present application does not limit the relationship between the start times of the applied voltages. Illustratively, the start time of applying each voltage (e.g., the precharge voltage, the turn-on voltage, the first voltage, etc.) is the same except for the default voltage that is continuously applied.

Through the

steps

601 and 602, under the condition that the programmed memory cells exist in the memory cell stack, the unselected memory strings can be sufficiently precharged, so that the program interference on the memory cells coupled with the selected word line is reduced.

In an exemplary embodiment, in a precharge phase prior to the programming phase, in addition to precharging unselected memory strings, selected memory strings may be precharged for operation. The selected memory string is a memory string in which the selected memory cell is located. The implementation process of precharging the selected memory string is detailed in the implementation process of precharging the unselected memory strings, and is not described herein again. In an exemplary embodiment, the process of precharging the memory strings to be precharged may be performed together or in batches, which is not limited in the embodiment of the present application.

After the precharge of each memory string to be precharged is completed, the precharge phase preceding the program phase is completed. After the precharge phase before the programming phase is completed, the programming phase is entered to program the selected memory cell.

In an exemplary embodiment, the selected memory cells are programmed by: a program voltage is applied to the selected word line, a pass voltage is applied to the word lines other than the selected word line (i.e., non-selected word lines), and a turn-on voltage is applied to the TSG-coupled DSL of the selected memory string. Further, a voltage of 0V is applied to the BSG-coupled SSL, the bit line terminal-coupled BL, and the source line terminal-coupled SL of the selected memory string; the TSG coupled DSL, BSG coupled SSL, bit line terminal coupled BL and source line terminal coupled SL of the unselected memory strings are all applied with 0V.

The programming voltage is high, for example, 22V, so that a sufficiently high positive voltage difference exists between the gate and the channel of the selected memory cell, and electrons in the channel of the selected memory cell can enter the floating gate or the charge trapping layer of the selected memory cell through a tunneling effect, so as to write data. By adjusting the magnitude of the programming voltage, the number of electrons stored in the floating gate or charge trapping layer can be adjusted, which in turn can adjust the threshold voltage of the selected memory cell. Illustratively, the minimum voltage that causes electrons in the channel to tunnel to the floating gate or charge trapping layer of a selected memory cell is referred to as the tunneling voltage, and then the programming voltage is not less than the tunneling voltage. It is understood that the tunneling voltage is a voltage greater than the threshold voltage.

The channel of other memory cells except the selected memory cell in the selected memory string can be conducted by applying the passing voltage to the unselected word line, and the passing voltage is lower than the programming voltage, so that the voltage difference between the gate and the channel of other memory cells in the selected memory string is relatively small, thereby preventing electrons in the channel from tunneling to a floating gate or a charge trapping layer, and realizing the program inhibition of other memory cells in the selected memory string.

Applying a turn-on voltage to the TSG-coupled DSL of the selected memory string can turn on the channel of the TSG of the selected memory string. During programming of the selected memory cell, the channels of the BSG of the selected memory string and the channels of the TSG and the BSG of the unselected memory strings are all off.

In the precharge method provided by the embodiment of the application, on the basis of applying the precharge voltage to the source line connection terminal, voltages larger than respective threshold voltages are applied to the gates of the programmed memory cells and the gates of the unprogrammed memory cells in the memory cell stack. In this way, when programmed memory cells exist in the memory cell stack, the channels of the memory cells in the memory cell stack are all ensured to be conductive, so that electrons in the doped region and electrons in the channels of the memory cells coupled with the selected word line are all attracted to the source line connecting end sufficiently, thereby realizing sufficient pre-charging of unselected memory strings, and being beneficial to reducing programming interference on the memory cells coupled with the selected word line in the memory cell stack.

For example, in the case of applying the first voltage to both the gates of programmed memory cells and the gates of unprogrammed memory cells, the voltages applied to unselected memory strings during the precharge phase and the programming phase are as shown in FIG. 7.

In the precharge phase, a precharge voltage (V) is applied to the CSL coupled to the source line connection of the unselected memory strings_CC) Applying a turn-on voltage (V) to BSG coupled SSLs of unselected memory strings_BSG) Applying a first voltage (V) to both the selected word line (sel. WL) and the unselected word line (Unsel. WL)_PRE). Exemplarily, V_PREA voltage greater than 5V. 0V is applied to BL coupled to the bit line connection of the unselected memory string and to DSL coupled to TSG of the unselected memory string.

Voltage application during the precharge phase shown in FIG. 7In the case of addition, V is applied_CCStart time of (1), application of V_BSGStart time of and application of V_PREAre all t₀Applying V_PREHas a cut-off time of t₁Applying V_CCOff-time and application of V_BSGAll cutoff times are t₂. Wherein, t₀、t₁And t₂The sequence from morning to evening is: t is t₀、t₁、t₂。

The voltage of 0V is a default voltage to be continuously applied. When the off-time for applying a certain voltage greater than 0V is reached, the voltage greater than 0V drops to 0V.

In a programming phase, a programming voltage (V) is applied to a selected word line (sel_PGM) Applying a pass voltage (V) to the unselected word lines (Unsel. WL)_PASS) The source line terminal coupled CSL, BSG coupled SSL, TSG coupled DSL, and bit line terminal coupled BL of the unselected memory strings are all applied with 0V.

In the case of voltage application in the programming phase shown in FIG. 7, V is applied_PGMStart time and application of V_PASSAre all t₃Applying V_PGMOff-time and application of V_PASSAll cutoff times are t₆。V_PGMAt t₄The highest value is reached. V_PGMAnd V_PASSAre all at t₅It begins to fall. Wherein, t₃、t₄、t₅And t₆The sequence from morning to evening is: t is t₃、t₄、t₅、t₆。

The embodiment shown in fig. 6 described above describes an implementation of precharging unselected memory strings in the case where a precharge voltage is applied to the source line connection terminal. In an exemplary embodiment, precharging of unselected memory strings may also be accomplished by applying a precharge voltage to the bit line connections. In some embodiments, the process of precharging unselected memory strings is: applying a precharge voltage to the bit line connection terminal; a voltage of 0V is applied to the gates of all memory cells in the memory cell stack. The inventor found that the voltage of 0V is not enough to make the channel of the programmed memory cell conductive, and if the programmed memory cell exists between the bit line connection terminal and the target memory cell, although electrons in the doped region can be attracted to the bit line connection terminal more sufficiently, electrons in the channel of the target memory cell cannot be attracted to the bit line connection terminal more sufficiently, which easily results in insufficient precharging, and thus the target memory cell is subjected to serious program disturb. The target memory cell refers to a memory cell coupled to a selected word line in a memory cell stack.

As can be seen from the above analysis, it is difficult to fully precharge the unselected memory strings by the precharge method in some embodiments, and therefore it is important to provide a method capable of fully precharging the unselected memory strings.

In an exemplary embodiment, the unselected memory strings are precharged according to the precharge method shown in

steps

801 and 802 in fig. 8 to reduce program disturb to the target memory cell.

In step 801, a precharge voltage is applied to the bit line connection.

The precharge voltage is capable of applying an electric field force directed to the bit line connection for electrons in the doped region and for electrons in the channel of the target memory cell. The target memory cell refers to a memory cell coupled to a selected word line in a memory cell stack. The embodiment of the present application does not limit the magnitude of the precharge voltage, and the precharge voltage is, for example, a certain voltage of 0 to 10V, for example, 2V.

In an exemplary embodiment, the bit line connection is coupled to BL and the precharge voltage is applied to the bit line connection by: a precharge voltage is applied to the BL coupled to the bit line connection.

For example, in the case where the precharge voltage is applied to the bit line connection terminal, the source line connection terminal may be grounded, that is, a voltage of 0V may be applied to the source line connection terminal, and a voltage greater than 0V but less than the precharge voltage may also be applied to the source line connection terminal.

In an exemplary embodiment, in the process of precharging the unselected memory strings, in addition to applying the precharge voltage to the bit line connection terminal, an on-voltage needs to be applied to the gate of the select transistor (that is, each select transistor in the select transistor stack, which may also be referred to as TSG) on the bit line connection terminal side to turn on the channel of the TSG, so as to prevent the TSG from blocking the movement of electrons toward the bit line connection terminal. In an exemplary embodiment, the process of applying the turn-on voltage to the gate of the TSG is accomplished by applying the turn-on voltage to the TSG-coupled DSL. The turn-on voltage is greater than the threshold voltage of the TSG. For example, if the threshold voltage of the TSG ranges from 1V to 4V, the on-state voltage may range from 5V to 15V.

In step 802, a channel of a memory cell in the memory cell stack between the bit line connection and a target memory cell is turned on, the memory cell between the bit line connection and the target memory cell comprising a programmed memory cell; the target memory cell is a memory cell coupled to the selected word line in the memory cell stack.

The programmed memory cell refers to a memory cell in which data is written between the bit line connection terminal and the target memory cell, and the memory cell in which data is written may refer to a memory cell which is not erased or a memory cell in which data is rewritten after erasing. Under the condition that the memory cell between the bit line connecting terminal and the target memory cell comprises a programmed memory cell, the channel of the memory cell between the bit line connecting terminal and the target memory cell is conducted, the phenomenon that the non-conducting channel blocks electrons in the channel of the target memory cell to move to the bit line connecting terminal can be avoided, and the electrons in the channel of the target memory cell and the electrons in the doped region can be attracted to the bit line connecting terminal more fully.

The embodiments of the present application do not limit whether the memory cell located between the bit line connection terminal and the target memory cell includes an unprogrammed memory cell. An unprogrammed memory cell refers to a memory cell between the bit line connection and the target memory cell, to which data is not written. That is, the memory cells between the bit line connection and the target memory cell may be all programmed memory cells, or may include both programmed memory cells and unprogrammed memory cells.

Illustratively, since the doped region is located between the bit line connection terminal and the target memory cell, and the doped region and the bit line connection terminal are located between the select transistor stack, and no memory cell exists in the select transistor stack, the memory cell located between the bit line connection terminal and the target memory cell is identical to the memory cell located between the doped region and the target memory cell.

The embodiment of the present application does not limit the case where the memory cell located between the bit line connection terminal and the target memory cell includes a programmed memory cell. For example, taking the erasing manner corresponding to the memory block in which the unselected memory string is located as an example of the total erasing, the case where the memory cell located between the bit line connection terminal and the target memory cell includes a programmed memory cell includes: the programming direction is a reverse programming direction, and a memory cell for rewriting data after erasing exists between the doped region and the target memory cell.

For example, the erasing manner corresponding to the memory block in which the unselected memory string is located may be partial erasing, in which case, the case where the memory cell located between the bit line connection terminal and the target memory cell includes a programmed memory cell may also be other cases, for example, there is an un-erased memory cell between the bit line connection terminal and the target memory cell.

In one possible implementation, the conduction of the channel of the memory cell in the memory cell stack between the bit line connection and the target memory cell may be implemented by: a first voltage is applied to the gate of the memory cell between the bit line connection and the target memory cell, the first voltage being greater than the threshold voltage of the programmed memory cell.

Since the threshold voltage of the unprogrammed memory cell is less than that of the programmed memory cell, whether or not the memory cell between the bit line connection terminal and the target memory cell includes the unprogrammed memory cell, the channel conduction of the memory cell between the bit line connection terminal and the target memory cell can be ensured by applying the first voltage to the gate of the memory cell between the bit line connection terminal and the target memory cell. The operation convenience of the implementation mode is high.

For example, the number of programmed memory cells is plural, the threshold voltages of different programmed memory cells may be different, and the first voltage is a voltage greater than the threshold voltage of each programmed memory cell. For example, if the threshold voltage of the programmed memory cell has a value range of 0-5V, the first voltage may have a value range of 5-7V.

Illustratively, the applying of the first voltage to the gate of the memory cell located between the bit line connection and the target memory cell is performed by applying the first voltage to a word line coupled to the memory cell located between the bit line connection and the target memory cell.

In an exemplary embodiment, the memory cell between the bit line connection terminal and the target memory cell further includes an unprogrammed memory cell, and in this case, the channel conduction of the memory cell between the bit line connection terminal and the target memory cell in the memory cell stack may be realized by: applying a first voltage to a gate of a programmed memory cell; a second voltage is applied to the gate of the unprogrammed memory cell. The first voltage is greater than the threshold voltage of the programmed memory cell, and the second voltage is greater than the threshold voltage of the unprogrammed memory cell and less than the first voltage.

The second voltage can enable the channel of the non-programmed memory cell to be conducted and is smaller than the first voltage, and the first voltage and the second voltage are respectively applied to the grid of the programmed memory cell and the grid of the non-programmed memory cell, so that power resources can be saved on the basis of ensuring that the channels of the programmed memory cell and the non-programmed memory cell are both conducted.

Illustratively, the memory cell stack includes, in addition to the memory cell located between the bit line connection terminal and the target memory cell, a memory cell not located between the bit line connection terminal and the target memory cell. The memory cells not located between the bit line connection terminal and the target memory cell include the target memory cell and the memory cells located between the source line connection terminal and the target memory cell.

In an exemplary embodiment, in addition to turning on the channel of the memory cell located between the bit line connection terminal and the target memory cell, the channel of the memory cell not located between the bit line connection terminal and the target memory cell in the memory cell stack may be turned on, so that the channels of all the memory cells in the memory cell stack are turned on. The principle of implementing the channel conduction of the memory cell not located between the bit line connection terminal and the target memory cell is the same as the principle of implementing the channel conduction of the memory cell located between the bit line connection terminal and the target memory cell, and is not described herein again.

In an exemplary embodiment, since the memory cell not located between the bit line connection terminal and the target memory cell does not block the movement of electrons in the channel of the target memory cell toward the bit line connection terminal, only a default voltage (e.g., 0V) needs to be applied to the gate of the memory cell not located between the bit line connection terminal and the target memory cell, regardless of whether the channel of the memory cell not located between the bit line connection terminal and the target memory cell is turned on.

In an exemplary embodiment, taking the example that the first voltage and the second voltage are respectively applied to the gate of the programmed memory cell and the gate of the unprogrammed memory cell, and the second voltage is a default voltage continuously applied to the gate of the memory cell, the sequence of the off-time of applying the first voltage and the pre-charge voltage is defined to further improve the pre-charge effect. In an exemplary embodiment, a cutoff time for applying the first voltage to the gate of the programmed memory cell is earlier than a cutoff time for applying the precharge voltage to the bit line connection terminal. Illustratively, upon reaching the off-time of the applied voltage, the voltage drops to a default voltage, illustratively 0V.

When the first voltage is applied to the grid of the programmed memory cell, part of electrons are adsorbed around the programmed memory cell, the off time of applying the first voltage to the grid of the programmed memory cell is earlier than the off time of applying the pre-charging voltage to the bit line connecting terminal, and after the voltage applied to the grid of the programmed memory cell is reduced to 0V, the electrons adsorbed around the programmed memory cell can continuously migrate and diffuse towards the bit line connecting terminal under the action of the electric field force provided by the pre-charging voltage, so that the pre-charging effect on the unselected memory strings is further improved.

In an exemplary embodiment, in addition to applying the precharge voltage to the bit line connection terminal and the first voltage to the gate of the programmed memory cell, the turn-on voltage is applied to the gate of the TSG, and in this case, the turn-off time for applying the first voltage to the gate of the programmed memory cell is earlier than the turn-off time for applying the turn-on voltage to the gate of the TSG and the turn-off time for applying the precharge voltage to the bit line connection terminal, so as to ensure sufficient precharging. Illustratively, the off-time of applying the on-voltage to the gate of the TSG is not later than the off-time of applying the precharge voltage to the bit line connection terminal.

In an exemplary embodiment, in the case where the number of programmed memory cells is plural, the off time of applying the first voltage to the gate of the programmed memory cell far from the bit line connection terminal is not later than the off time of applying the first voltage to the gate of the programmed memory cell near to the bit line connection terminal to ensure the precharge is sufficient. That is, the off-time for applying the first voltage to the gates of the respective programmed memory cells is the same; alternatively, the gate of the programmed memory cell farther from the bit line connection terminal is applied with the first voltage for the earlier off-time.

In an exemplary embodiment, in the case where the first voltage is applied to the gate of the memory cell located between the bit line connection terminal and the target memory cell, the off-time of applying the first voltage to the gate of the memory cell located between the bit line connection terminal and the target memory cell is earlier than the off-time of applying the precharge voltage to the bit line connection terminal to ensure that the precharge is sufficient. Illustratively, in applying the first voltage to the gate of the memory cell located between the bit line connection terminal and the target memory cell, the off-time of applying the first voltage to the gate of the memory cell located farther from the bit line connection terminal is not later than the off-time of applying the first voltage to the gate of the memory cell located closer to the bit line connection terminal to ensure that the precharge is sufficient.

In an exemplary embodiment, in the case where the first voltage and the second voltage are applied to the gate of the programmed memory cell and the gate of the unprogrammed memory cell, respectively, and the second voltage is not a default voltage that is continuously applied to the gate of the memory cell, the off-time of applying the first voltage to the gate of the programmed memory cell and the off-time of applying the second voltage to the gate of the unprogrammed memory cell are both earlier than the off-time of applying the precharge voltage to the bit line connection terminal to ensure that the precharge is sufficient. For example, the off-time for applying the respective voltage to the gate of the memory cell located further from the bit line connection terminal is not later than the off-time for applying the respective voltage to the gate of the memory cell located closer to the bit line connection terminal, in order to ensure that the precharging is sufficient. If the memory cell is a programmed memory cell, the corresponding voltage is a first voltage; if the memory cell is an unprogrammed memory cell, the corresponding voltage is the second voltage.

Through the

steps

801 and 802, under the condition that a programmed memory cell exists between the bit line connection terminal and the target memory cell, the unselected memory strings can be sufficiently precharged, so that the program interference on the memory cell coupled with the selected word line is reduced.

According to the pre-charging method provided by the embodiment of the application, on the basis of applying the pre-charging voltage to the bit line connecting end, the channel of the storage unit between the bit line connecting end and the target storage unit is conducted, the phenomenon that electrons in the channel of the target storage unit are blocked by the non-conducted channel and move to the bit line connecting end can be avoided, so that the electrons in the doped region and the electrons in the channel of the target storage unit are attracted to the bit line connecting end sufficiently, the unselected storage strings are pre-charged sufficiently, and the programming interference on the target storage unit in the storage unit stack is reduced.

In an exemplary embodiment, there is also provided a memory including a memory array and peripheral circuitry communicatively coupled to the memory array;

the peripheral circuit is configured to apply a precharge voltage to the source line connection terminal; applying a voltage to the gate of each memory cell in the memory cell stack; the voltage applied to the gate of the programmed memory cell is greater than the threshold voltage of the programmed memory cell, and the voltage applied to the gate of the unprogrammed memory cell is greater than the threshold voltage of the unprogrammed memory cell.

In one possible implementation, the peripheral circuitry is configured to apply a first voltage to both the gates of programmed memory cells and the gates of unprogrammed memory cells, the first voltage being greater than the threshold voltage of the programmed memory cells.

In one possible implementation, the peripheral circuit is configured to apply a first voltage to the gate of a programmed memory cell, the first voltage being greater than the threshold voltage of the programmed memory cell, and a second voltage to the gate of an unprogrammed memory cell, the second voltage being greater than the threshold voltage of the unprogrammed memory cell and less than the first voltage.

In one possible implementation, the off-time of applying the first voltage to the gate of the programmed memory cell is earlier than the off-time of applying the precharge voltage to the source line connection.

In one possible implementation, the number of programmed memory cells is plural; the off time for applying the first voltage to the gates of programmed memory cells further from the source line connection is no later than the off time for applying the first voltage to the gates of programmed memory cells closer to the source line connection.

the memory array comprises unselected memory strings, a selection tube stack and a memory cell stack are arranged between a bit line connecting end and a source line connecting end of each unselected memory string, and the selection tube stack and the memory cell stack are connected through a doped region;

the peripheral circuit is configured to apply a precharge voltage to the bit line connection terminal; conducting channels of memory cells, which are positioned between a bit line connecting terminal and a target memory cell in a memory cell stack, wherein the memory cells positioned between the bit line connecting terminal and the target memory cell comprise programmed memory cells; the target memory cell is a memory cell coupled to the selected word line in the memory cell stack.

In an exemplary embodiment, there is also provided a memory system, the memory system comprising a memory and a controller coupled to the memory, the controller configured to control the memory;

the memory comprises a memory array and peripheral circuits in communication connection with the memory array;

It should be understood that reference to "a plurality" herein means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

The above description is only exemplary of the present application and should not be taken as limiting the present application, and any modifications, equivalents, improvements and the like that are made within the principles of the present application should be included in the protection scope of the present application.

Claims

1. A memory, comprising a memory array and peripheral circuitry communicatively coupled to the memory array;

2. The memory of claim 1, wherein the peripheral circuitry is configured to apply a first voltage to both the gates of the programmed memory cells and the gates of the unprogrammed memory cells, the first voltage being greater than the threshold voltage of the programmed memory cells.

3. The memory of claim 1, wherein the peripheral circuitry is configured to apply a first voltage to the gate of the programmed memory cell, and a second voltage to the gate of the unprogrammed memory cell, the first voltage being greater than the threshold voltage of the programmed memory cell, the second voltage being greater than the threshold voltage of the unprogrammed memory cell and less than the first voltage.

4. The memory of claim 3, wherein a turn-off time for applying the first voltage to the gate of the programmed memory cell is earlier than a turn-off time for applying the precharge voltage to the source line connection.

5. The memory according to claim 3 or 4, wherein the number of programmed memory cells is plural; the off time for applying the first voltage to the gates of programmed memory cells that are further from the source line connection is no later than the off time for applying the first voltage to the gates of programmed memory cells that are closer to the source line connection.

6. A storage system comprising a memory and a controller coupled to the memory, the controller configured to control the memory;

the peripheral circuit is configured to apply a precharge voltage to the source line connection terminal; applying a voltage to a gate of each memory cell in the memory cell stack; wherein the voltage applied to the gate of the programmed memory cell is greater than the threshold voltage of the programmed memory cell, and the voltage applied to the gate of the unprogrammed memory cell is greater than the threshold voltage of the unprogrammed memory cell.

7. The memory system of claim 6, wherein the peripheral circuitry is configured to apply a first voltage to both the gates of the programmed memory cells and the gates of the unprogrammed memory cells, the first voltage being greater than a threshold voltage of the programmed memory cells.

8. The memory system of claim 6, wherein the peripheral circuit is configured to apply a first voltage to the gate of the programmed memory cell and a second voltage to the gate of the unprogrammed memory cell, the first voltage being greater than the threshold voltage of the programmed memory cell, the second voltage being greater than the threshold voltage of the unprogrammed memory cell and less than the first voltage.

9. The memory system of claim 8, wherein a cutoff time for applying the first voltage to the gate of the programmed memory cell is earlier than a cutoff time for applying the precharge voltage to the source line connection terminal.

10. The memory system according to claim 8 or 9, wherein the number of programmed memory cells is plural; the off time for applying the first voltage to the gates of programmed memory cells that are further from the source line connection is no later than the off time for applying the first voltage to the gates of programmed memory cells that are closer to the source line connection.

11. A pre-charging method is characterized in that the pre-charging method is used for pre-charging unselected memory strings, a selection tube stack and a memory cell stack are arranged between a bit line connecting end and a source line connecting end of the unselected memory strings, the selection tube stack and the memory cell stack are connected through a doped region, and the memory cell stack comprises programmed memory cells and un-programmed memory cells; the method comprises the following steps:

applying a precharge voltage to the source line connection terminal;

applying a voltage to the gate of each memory cell in the memory cell stack;

12. The method of claim 11, wherein applying a voltage to the gate of each memory cell in the stack of memory cells comprises:

13. The method of claim 11, wherein applying a voltage to the gate of each memory cell in the stack of memory cells comprises:

14. The method of claim 13, wherein a cutoff time for applying the first voltage to the gate of the programmed memory cell is earlier than a cutoff time for applying the precharge voltage to the source line connection.

15. The method of claim 13 or 14, wherein the number of programmed memory cells is plural; the off time for applying the first voltage to the gates of programmed memory cells that are further from the source line connection is no later than the off time for applying the first voltage to the gates of programmed memory cells that are closer to the source line connection.