CN114446248B

CN114446248B - Gate drive circuit, display panel and display device

Info

Publication number: CN114446248B
Application number: CN202011199909.6A
Authority: CN
Inventors: 迟世鹏; 欧阳祥睿; 安亚斌; 贺海明
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-10-30
Filing date: 2020-10-30
Publication date: 2023-06-27
Anticipated expiration: 2040-10-30
Also published as: CN114446248A

Abstract

The embodiment of the application provides a gate driving circuit, a display panel and a display device, wherein the gate driving circuit is used for providing scanning signals for a pixel driving circuit comprising an N-type transistor and a P-type transistor; the shift register comprises a high-enable signal output end electrically connected with the first type of scanning signal lines and a low-enable signal output end electrically connected with the second type of scanning signal lines; the time for the high-level enable signal output end to output the high-level signal covers the time for the low-level enable signal output end to output the low-level signal, and the time for the low-level enable signal output end to output the low-level signal is less than the time for the high-level enable signal output end to output the high-level signal. In the gate driving circuit provided by the embodiment of the application, the shift register of the same stage can output low enabling signals and high enabling signals, and only one group of gate driving circuits are needed to control the pixel driving circuit, so that a complex algorithm is not needed, and a display panel and a display device are guaranteed to have narrower frames.

Description

Gate drive circuit, display panel and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a gate driving circuit, a display panel, and a display device.

Background

The application of the organic light-emitting display screen in the fields of mobile communication, wearing products and the like is growing increasingly, so that the research of the organic light-emitting display screen becomes a hot spot. In general, a switching transistor of a pixel driving circuit in an organic light emitting display screen adopts low-temperature polysilicon with mature preparation technology, however, the transistor prepared by the low-temperature polysilicon is easy to generate larger leakage current, so that the organic light emitting display screen can flash obviously when displaying at low frequency with lower power consumption. Therefore, in the prior art, a low-temperature polysilicon transistor and an oxide thin film transistor are included in a plurality of switching transistors of a pixel driving circuit in an organic light emitting display screen to improve a low-frequency flicker problem caused by leakage current.

The oxide thin film transistor is typically an N-type transistor with an off-state leakage current of less than 1fA, while the low temperature polysilicon transistor is typically a P-type transistor with a faster response speed. In the prior art, in order to drive the P-type transistor and the N-type transistor in the pixel driving circuit at the same time, two groups of gate driving circuits may be used to output signals for controlling the P-type transistor and signals for controlling the N-type transistor respectively, but the frame of the display screen may be increased.

Disclosure of Invention

The application provides a gate driving circuit, a display panel and a display device, so as to solve the problems.

In a first aspect, embodiments of the present application provide a gate driving circuit for providing a scanning signal to a pixel driving circuit; the pixel driving circuit comprises at least one N-type transistor and at least one P-type transistor, wherein the grid electrode of the at least one N-type transistor is electrically connected with the first type scanning line, and the grid electrode of the at least one P-type transistor is electrically connected with the second type scanning line; the grid driving circuit comprises N-stage cascaded shift registers, and N is a positive integer greater than or equal to 3; the shift register comprises a high-enable signal output end electrically connected with the first type of scanning signal lines and a low-enable signal output end electrically connected with the second type of scanning signal lines; the time for the high-level enable signal output end to output the high-level signal covers the time for the low-level enable signal output end to output the low-level signal, and the time for the low-level enable signal output end to output the low-level signal is less than the time for the high-level enable signal output end to output the high-level signal.

In a second aspect, embodiments of the present application provide a display panel including a display area and a non-display area surrounding the display area; wherein the non-display region includes the gate driving circuit as provided in the first aspect; the display area is provided with a pixel driving circuit and a light emitting device, the pixel driving circuit can control the light emitting device to emit light, and the grid driving circuit provides scanning signals for the pixel driving circuit.

In a third aspect, embodiments of the present application provide a display device including a display panel as provided in the second aspect.

In the gate driving circuit, the display panel and the display device provided by the embodiment of the application, the shift register of the same stage can output a low enabling signal to control the P-type transistor in the pixel driving circuit to work, and can also output a high enabling signal to control the N-type transistor in the pixel driving circuit to work. Therefore, the technical scheme of the application can complete the control of the pixel driving circuit PD by only using one group of gate driving circuits, does not need a complex algorithm, and ensures that the display panel has a narrower frame.

Drawings

Fig. 1 is a schematic diagram of a display panel according to an embodiment of the present application;

FIG. 2 is an enlarged view of a light emitting pixel in a display panel;

FIG. 3 is a schematic diagram of a shift register according to an embodiment of the present disclosure;

FIG. 4 is a timing diagram corresponding to the shift register shown in FIG. 3;

FIG. 5 is a schematic diagram of another shift register according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a shift register according to an embodiment of the present disclosure;

FIG. 7 is an equivalent circuit diagram of a shift register corresponding to FIG. 5;

FIG. 8 is an equivalent circuit diagram of a shift register corresponding to FIG. 6;

FIG. 9 is a timing diagram illustrating operation of the shift register of FIGS. 7 and 8;

fig. 10 is an equivalent circuit diagram of a shift register according to an embodiment of the present application;

FIG. 11 is a timing diagram corresponding to the shift register shown in FIG. 10;

FIG. 12 is a schematic diagram of a shift register according to an embodiment of the present disclosure;

FIG. 13 is an equivalent circuit diagram of a shift register corresponding to FIG. 12;

FIG. 14 is a timing diagram of a shift register of FIG. 13;

fig. 15 is a partial equivalent circuit diagram of a gate driving circuit according to an embodiment of the present application;

FIG. 16 is a partial equivalent circuit diagram of another gate drive circuit according to an embodiment of the present disclosure;

FIG. 17 is a partial equivalent circuit diagram of yet another gate drive circuit provided in an embodiment of the present application;

FIG. 18 is a timing diagram corresponding to the gate driving circuit shown in FIGS. 15 and 16;

FIG. 19 is a timing diagram corresponding to the gate driving circuit shown in FIG. 17;

fig. 20 is a schematic diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The terminology used in the description section of the present application is for the purpose of describing particular embodiments of the present application only and is not intended to be limiting of the present application.

The embodiment of the application provides a gate driving circuit, a display panel using the same and a display device.

Fig. 1 is a schematic diagram of a display panel according to an embodiment of the present application, and fig. 2 is an enlarged view of a light emitting pixel in the display panel. As shown in fig. 1, the display panel provided in the embodiment of the present application includes a display area AA and a non-display area BB surrounding the display area AA. The display area AA includes a plurality of light emitting pixels including a pixel driving circuit PD and a light emitting device EL, wherein the pixel driving circuit PD can generate a light emitting driving current or a light emitting driving voltage for driving the light emitting device EL to emit light during display. In the embodiments of the present application, the light emitting device EL may be an active light emitting device such as an organic light emitting diode, a micro light emitting diode, or the like.

As shown in fig. 2, the pixel driving circuit PD in the light emitting pixel includes a light emitting driving transistor TD, a data voltage writing transistor T01, a threshold grabbing transistor T02, a power supply voltage writing transistor T03, a light emitting control transistor T04, a reset transistor T05, and a first capacitor C0. The light-emitting driving transistor TD, the power supply voltage writing transistor T03, and the light-emitting control transistor T04 may be P-type transistors, and the threshold value grabbing transistor T02 may be an N-type transistor; the data voltage writing transistor T01 and the reset transistor T05 may be transistors of different types, for example, as shown in fig. 1 and 2, the data voltage writing transistor T01 is a P-type transistor, and the reset transistor T05 is an N-type transistor.

The source of the data voltage writing transistor T01 is electrically connected to the data signal line DL, and the drain of the data voltage writing transistor T01 is electrically connected to the source of the light emitting driving transistor TD. The source of the threshold value grasping transistor T02 is electrically connected to the drain of the light emission driving transistor TD, and the drain of the threshold value grasping transistor T02 is electrically connected to the gate of the light emission driving transistor TD. The source of the power supply voltage writing transistor T03 is electrically connected to the power supply voltage line PVDD, and the drain of the power supply voltage writing transistor T03 is electrically connected to the source of the light-emitting driving transistor TD. The source of the light emission control transistor T04 is electrically connected to the drain of the light emission driving transistor TD, and the drain of the light emission control transistor T04 is electrically connected to the light emitting device EL. The source of the reset transistor T05 is electrically connected to the reset signal line REF, and the drain of the reset transistor T05 is electrically connected to the drain of the threshold value grasping transistor T02. The first electrode of the first capacitor C0 is electrically connected to the gate of the light-emitting driving transistor TD, and the second electrode of the first capacitor C0 is electrically connected to the power supply voltage line PVDD.

The operation of the pixel driving circuit shown in fig. 2, which includes a reset phase, a data voltage writing phase, and a light emitting phase, is described below.

In the reset phase, the threshold grabbing transistor T02 and the reset transistor T05 are turned on, and the reset signal line REF transmits a reset signal, the reset signal is written into the gate of the light emitting driving transistor TD, the gate of the light emitting driving transistor TD is reset, and the first capacitor C0 stores the reset signal.

In the data voltage writing stage, the power supply voltage writing transistor T03 and the light emission control transistor T04 are turned off, the data voltage writing transistor T01 and the threshold value grabbing transistor T02 are turned on, and the data voltage is transmitted on the data signal line DL, and since the potential of the data voltage is higher than the potential of the reset signal, the light emission driving transistor TD is turned on and the data voltage is written into the gate of the light emission driving transistor TD;

in the light emitting stage, the threshold value grabbing transistor T02 is turned off, the power supply voltage writing transistor T03 and the light emitting control transistor T04 are turned on, the power supply voltage line PVDD transmits the power supply voltage, the power supply voltage is transmitted to the source electrode of the light emitting driving transistor TD, the potential of the power supply voltage is greater than the potential of the data voltage, and the light emitting driving transistor TD generates the light emitting driving current and transmits the light emitting driving current to the light emitting device EL.

In the light emission stage, when the potential of the gate electrode of the light emission driving transistor TD changes, the light emission driving current changes, and the display luminance is further affected. Since the gate of the light-emitting driving transistor TD is electrically connected to the threshold value grasping transistor T02, the leakage current generated by the threshold value grasping transistor T02 causes a change in the gate potential of the light-emitting driving transistor TD. Since the leakage current of the N-type transistor is small relative to that of the P-type transistor, in order to avoid that the leakage current of the threshold value grasping transistor T02 affects the gate potential of the light emission driving transistor TD in the light emission stage, the threshold value grasping transistor T02 is generally set as an N-type transistor. The pixel driving circuit PD has P-type transistors, for example, the power supply voltage writing transistor T03 and the light emission control transistor T04 are P-type transistors, and can be turned on in the light emission stage with a smaller driving voltage.

It should be noted that fig. 2 illustrates an equivalent circuit diagram of a pixel driving circuit PD in a light emitting pixel, and the pixel driving circuit PD provided in the embodiment of the present application may also have other circuit structures. However, the pixel driving circuit PD in the display panel and the display device provided in the embodiments of the present application includes a plurality of transistors, where the plurality of transistors includes a P-type transistor and an N-type transistor, and the P-type transistor is turned on at a different potential from a potential required for the N-type transistor to be turned on, so that the scan lines electrically connected to the gates of the plurality of transistors in the PD in the pixel driving circuit include a first type scan line and a second type scan line, and the first type scan line and the second type scan line can respectively control the N-type transistor and the P-type transistor by transmitting scan signals.

As shown in fig. 1, the display panel includes a plurality of first type scan lines SL11, SL21, … …, SLi1, … …, and SLN1, and a plurality of second type scan lines SL12, SL22, … …, SLi2, … …, and SLN2. In the pixel driving circuits PD located in the same row, at least one N-type transistor in each pixel driving circuit PD is electrically connected to the first type scanning line, and at least one P-type transistor in each pixel driving circuit PD is electrically connected to the second type scanning line. As shown in fig. 1, the display panel includes N rows of pixel driving circuits PD, N first type scan lines SL11, SL21, … …, SLi1, … …, SLN1, and N second type scan lines SL12, SL22, … …, SLi2, … …, SLN2. At least one N-type transistor, such as a threshold value grabbing transistor T02, in each pixel driving circuit PD in the ith row of pixel driving circuits PD is electrically connected to the ith first type scanning line SLi 1; at least one P-type transistor, for example, a power supply voltage writing transistor T03, in each of the pixel driving circuits PD located in the i-th row is electrically connected to the i-th second-type scanning line SLi 2. Wherein N is a positive integer greater than or equal to 3, i is greater than or equal to 1 and less than or equal to N, and i is a positive integer.

As can be seen from the above working process of the pixel driving circuit, the threshold grabbing transistor T02 and the power supply voltage writing transistor T03 and the light emitting control transistor T04 have different on and off times, and the threshold grabbing transistor T02 and the power supply voltage writing transistor T03 and the light emitting control transistor T04 have different transistor types, so that the threshold grabbing transistor T02, the power supply voltage writing transistor T03 and the light emitting control transistor T04 in the same row can be connected to the same first type scan line, for example, all the first type scan lines are electrically connected to SLi1; the reset transistor T05 and the data voltage writing transistor T01 have different on-times, and are different types of transistors, so that the reset transistor T05 and the data voltage writing transistor T0 in the same row can be connected to the same scan line, for example, all are electrically connected to the second type scan line SLi2, and it should be noted that, in the light emitting stage, the threshold value grabbing transistor T02 is turned off, so that the normal light emission of the light emitting device is not affected even if the reset transistor T05 is turned on.

In the embodiment of the application, as shown in fig. 1, the non-display area BB of the display panel includes a gate driving circuit, the gate driving circuit includes N-stage cascaded shift registers SR1, SR2, … …, SRi, … …, SRN, each stage of the cascaded shift registers SR1/SR2/… …/SRi/… …/SRN includes at least two output terminals, the at least two output terminals include a low enable signal output terminal GP1/GP2/… …/GPi/… …/GPN and a high enable signal output terminal GN1/GN2/… …/GNi/… …/GNN, wherein the low enable signal output terminal GP1/GP2/… …/GPi/… …/SLN is electrically connected to the second type scan lines SL12/SL22/… …/SLi2/… …/SLN2, and the high enable signal output terminal GN1/GN2/… …/GNi/… …/GNN is electrically connected to the first type scan lines SL11, 21, SL1, SL 84, sl1, sl95, respectively. The first type scan lines and the second type scan lines, which are electrically connected to the pixel driving circuits PD in the same row, are electrically connected to the high enable signal output terminal and the low enable signal output terminal of the same stage shift register, respectively. For example, as shown in fig. 1, the pixel driving circuit PD in the ith row is electrically connected to the first type scan line SLi1 and the second type scan line SLi2, which are correspondingly and electrically connected to the high enable signal output terminal GNi and the low enable signal output terminal GPi of the ith shift register SRi, respectively.

That is, the shift registers of the same stage may output a low enable signal and transmit it to the P-type transistors in the second type scan line control pixel driving circuit PD for operation, and may output a high enable signal and transmit it to the N-type transistors in the first type scan line control pixel driving circuit PD for operation. Therefore, the technical scheme of the application can complete the control of the pixel driving circuit PD by only using one group of gate driving circuits, does not need a complex algorithm, and ensures that the display panel has a narrower frame.

It should be noted that, the shift register further includes a first control terminal Si, and the shift register in multi-stage cascade connection refers to a two-stage shift register that is adjacently disposed, where one output terminal (for example, a low enable signal output terminal) of a previous stage shift register is electrically connected to the first control terminal Si of a next stage shift register, that is, a signal for controlling the next stage shift register to be turned on is derived from an output terminal of the previous stage shift register electrically connected to the first control terminal Si. Meanwhile, as shown in fig. 1, the first control terminal Si of the first stage shift register SR1 is electrically connected to the start signal line STV.

Fig. 3 is a schematic diagram of a shift register provided in the embodiment of the present application, and fig. 3 and the following figures illustrate the structure and the working principle of the shift register provided in the embodiment of the present application by taking the ith stage of shift register SRi in the gate driving circuit as an example. However, any one of the shift registers in the scan driving circuit provided in the present application may be the same as the i-th shift register SRi.

With continued reference to fig. 3, the shift register SRi provided in the embodiment of the present application includes a control unit CT, a first output unit K1, a second output unit K2, a first shutdown unit G1, a second shutdown unit G2, a first amplifier B1, and a second amplifier B2.

The control unit CT includes a first control output p3 and a second control output n3.

The first control output end p3 is electrically connected with the control end of the first output unit K1 and is electrically connected with the control end of the first turn-off unit G1, and is used for controlling the on and off of the first output unit K1 and the on and off of the first turn-off unit G1, wherein the on time of the first output unit K1 is different from the on time of the first turn-off unit G1. The input end of the first output unit K1 is electrically connected to the first signal line X1i, and the output end is electrically connected to the first amplification input end p2 of the first amplifier B1. The input end of the first turn-off unit G1 is electrically connected to the first potential signal line V1, and the output end is electrically connected to the first amplification input end p2 of the first amplifier B1. The output terminal of the first amplifier B1 is electrically connected to the low enable signal output terminal GPi.

When the first output unit K1 is turned on by the signal output by the first control output terminal p3 of the control unit CT, the signal on the first signal line X1i is transmitted to the first amplifying input terminal p2 of the first amplifier B1 through the first output unit K1, and then the low-level signal is output by the low enable signal output terminal GPi; when the first turn-off unit G1 is turned on by the signal output from the first control output terminal p3 of the control unit CT, the signal on the first potential signal line V1 is transmitted to the first amplifying input terminal p2 of the first amplifier B1 through the first turn-off unit G1, and the low enable signal output terminal GPi outputs the high level signal.

The second control output end n3 is electrically connected with the control end of the second output unit K2 and is electrically connected with the control end of the second turn-off unit G2, and is used for controlling the on and off of the second output unit K2 and the on and off of the second turn-off unit G2, and the on time of the second output unit K2 is different from the on time of the second turn-off unit G2. The input end of the second output unit K2 is electrically connected with the second signal line X2i, and the output end of the second output unit K2 is electrically connected with the second amplifying input end n2 of the second amplifier B2; the input end of the second turn-off unit G2 is electrically connected with the second potential signal line V2, and the output end of the second turn-off unit G2 is electrically connected with the second amplifying input end n2 of the second amplifier B2; the output terminal of the second amplifier B2 is electrically connected to the high enable signal output terminal GNi.

When the second output unit K2 is turned on by the signal output from the second control output terminal n3 of the control unit CT, the signal on the second signal line X2i is transmitted to the second amplifying input terminal n2 of the second amplifier B2 through the second output unit K2, and the high-level signal is further output from the high enable signal output terminal GNi; when the second turn-off unit G2 is turned on by the signal output from the second control output terminal n3 of the control unit CT, the signal on the second potential signal line V2 is transmitted to the second amplifying input terminal n2 of the second amplifier B2 through the second turn-off unit G2, and the low level signal is further output from the high enable signal output terminal GNi.

FIG. 4 is a timing diagram corresponding to the shift register shown in FIG. 3. Assume that the first control output terminal p3 outputs a high level signal, the first output unit K1 is turned on and the first turn-off unit G1 is turned off, and the first control output terminal p3 outputs a low level signal, the first output unit K1 is turned off and the first turn-off unit G1 is turned on; the second control output terminal n3 outputs the low level signal, the second output unit K2 is turned on and the second turn-off unit G2 is turned off, and the second control output terminal n3 outputs the high level signal, the second output unit K2 is turned off and the second turn-off unit G2 is turned on.

As shown in fig. 4, in the first working stage t1, the shift register SRi may output a low level signal at the low enable signal output end GPi, so that the P-type transistor controlled by the second type scan line SLi2 electrically connected to the low enable signal output end GPi in the pixel driving circuit PD is turned on; the high enable signal output terminal GNi can output a high level signal to turn on the N-type transistor controlled by the first scan line SLi1 electrically connected to the high enable signal output terminal GNi in the pixel driving circuit PD.

The following describes the operation of the shift register SRi provided in the embodiment of the present application in the first operation stage t1 with reference to fig. 3 and 4. In the low enable signal output stage t1p of the first operation stage t1, the first control output terminal p3 of the control unit CT outputs a high level signal to turn on the first output unit K1, and the first signal line X1i transmits a low level signal, the first amplification input terminal p2 of the first amplifier B1 receives the low level signal and the first amplifier B1 amplifies the low level signal and then outputs the amplified low level signal from the low enable signal output terminal GPi; in the high enable signal output stage t1n of the first operation stage t1, the second control output terminal n3 of the control unit CT outputs a low level signal such that the second output unit K2 is turned on, and the second signal line X2i transmits a high level signal, the second amplification input terminal n2 of the second amplifier B2 receives the high level signal and the second amplifier B2 amplifies the high level signal and then outputs it from the high enable signal output terminal GNi.

As shown in fig. 4, in the second operation stage t2, the shift register SRi outputs a high level signal at the low enable signal output end GPi, so that the P-type transistor controlled by the first type scan line SLi1 electrically connected to the low enable signal output end GPi in the pixel driving circuit PD is turned off; the high enable signal output terminal GNi outputs a low level signal to turn off the N-type transistor controlled by the second type scan line SLi2 electrically connected to the high enable signal output terminal GNi in the pixel driving circuit PD.

The following describes the operation of the shift register SRi provided in the embodiment of the present application in the second operation stage t2 with reference to fig. 3 and 4. The first control output terminal p3 of the control unit CT outputs a low level signal to turn on the first turn-off unit G1, and the first potential signal line V1 transmits a high level signal, so that the first amplifying input terminal p2 of the first amplifier B1 receives the high level signal and the first amplifier B1 amplifies the high level signal, and then the high level signal is output by the low enable signal output terminal GPi; the second control output terminal n3 of the control unit CT outputs a high level signal such that the second turn-off unit G2 is turned on, and the second potential signal line V2 transmits a low level signal, the second amplification input terminal n2 of the second amplifier B2 receives the low level signal and the second amplifier B2 amplifies the low level signal, and then the low level signal is output by the high enable signal output terminal GNi.

In one implementation of the present application, during the first operation stage t1, the first control output terminal p3 of the control unit CT may also output a low level signal to turn on the first output unit K1. In the first operation period t1, the output level signal of the first control output terminal p3 of the control unit CT should make the first output unit K1 conductive, and make the first output unit K1 continuously conductive in the first operation period t1, regardless of whether the first control output terminal p3 outputs a high level or a low level. In one implementation of the present application, during the first operation stage t1, the second control output terminal n3 of the control unit CT may also output a high level signal to turn on the second output unit K2. In the first operation period t1, the second control output terminal n3 of the control unit CT outputs a high level or a low level, and the output level signal should make the second output unit K2 conductive, and make the second output unit K2 continuously conductive in the first operation period t 1.

In one implementation of the present application, as shown in fig. 4, the first signal line X1i and the second signal line X2i may output pulse signals. It should be noted that, in the shift register SRi provided in the embodiment of the present application, the first signal line X1i may output a high level signal in the low enable signal output stage t1p of the first working stage t1, but no matter whether the first signal line X1i outputs a low level or a high level in the low enable signal output stage t1p of the first working stage t1, the first signal line X1 needs to be cooperatively set with the corresponding first amplifier B1 to ensure that the signal on the first signal line X1i is a low level signal after being output by the first output unit K1 and then passing through the first amplifier B1, and then the signal output by the low enable signal output end GPi is a low level signal. In the shift register SRi provided in this embodiment, the second signal line X2i may also output a low-level signal in the high enable signal output stage t1n of the first working stage t1, but no matter whether the second signal line X2i outputs a low level or a high level in the high enable signal output stage t1n of the first working stage t1, the second signal line X2i needs to be matched with the corresponding second amplifier B2 to ensure that the signal on the second signal line X2i is output through the second output unit K2 and then passes through the second amplifier B2 and then the high enable signal output end GNi outputs a high-level signal.

In one implementation of the present application, in the second operation stage t2, the first control output terminal p3 of the control unit CT may also output a high level signal to turn on the first turn-off unit G1. In the second operation period t2, the output level signal of the control unit CT should make the first turn-off unit G1 turned on no matter the first control output terminal p3 of the control unit CT outputs a high level or a low level, and make the first turn-off unit G1 continuously turned on in the second operation period t 2. In one implementation of the present application, during the second operation phase t2, the second control output terminal n3 of the control unit CT may also output a low level signal to turn on the second turn-off unit G2. In the second operation period t2, the output level signal of the second control output terminal n3 of the control unit CT should make the second turn-off unit G2 turned on, and make the second turn-off unit G2 continuously turned on in the second operation period t2, regardless of whether the second control output terminal n3 outputs a high level or a low level.

In one implementation of the present application, as shown in fig. 4, the first potential signal line V1 and the second potential signal line V2 may continuously output constant potential signals. It should be noted that, in the shift register SRi provided in this embodiment of the present application, the first potential signal line V1 may also transmit a low level signal, but no matter the first potential signal line V1 transmits a low level signal or a high level signal, the first potential signal line V1 needs to be cooperatively set with the corresponding first amplifier B1, so as to ensure that a signal on the first potential signal line V1 is output through the first turn-off unit G1 and then passes through the first amplifier B1 and then is output by the low enable signal output end GPi. In the shift register SRi provided in this embodiment, the second potential signal line V2 may also transmit a high level signal, but no matter the second potential signal line V2 transmits a low level signal or a high level signal, the second potential signal line V2 needs to be matched with the corresponding second amplifier B2, so as to ensure that the signal on the second potential signal line V2 is output through the second turn-off unit G2 and then passes through the second amplifier B2 and then is output by the high enable signal output end GNi.

In this embodiment of the present application, in the first working stage t1, the first control output terminal p3 and the second control output terminal n3 of the control unit CT in the shift register SRi output the enable signals for enabling the first output unit K1 to be turned on and the second output unit K2 to be turned on, respectively, and the first control output terminal p3 and the second control output terminal n3 of the control unit CT output the enable signals at the same time and with the same duration, and the time of the low-level signal output by the low-enable signal output terminal GPi and the time of the high-level signal output by the high-level enable signal output terminal GN are controlled by the change of the signal on the first signal line X1i and the change of the signal on the second signal line X2 i. In the second operation stage t2, the first control output terminal p3 and the second control output terminal n3 of the control unit CT in the shift register SRi output signals for turning on the first turn-off unit G1 and the second turn-off unit G2, respectively, and the first control output terminal p3 and the second control output terminal n3 of the control unit CT output the signals at the same time and for a same duration, and continuously output constant potential signals through the first potential signal line V1 and the second potential signal line V2 to realize continuous output of the high level signal and the high level signal output by the low enable signal output terminal GP and continuous output of the low level signal by the high enable signal output terminal GN. The shift register SR only needs to include one control unit CT, and the circuit structure of the shift register SRi is simplified.

Referring to fig. 1, 2, 3 and 4, the first operation stage t1 of the shift register may correspond to a reset stage and a data voltage writing stage of the pixel driving circuit PD, and the second operation stage t2 may correspond to a light emitting stage of the pixel driving circuit. The low enable signal output stage T1p of the first operation stage T1 specifically corresponds to the data voltage writing stage, and at this time, the high enable signal output terminal GNi outputs a high level to turn on the threshold grabbing transistor T02, and the low enable signal output terminal GPi outputs a low level to turn on the data voltage writing transistor T01. The phase before the low enable signal output phase T1p of the first working phase T1 corresponds to a reset phase, at this time, the high enable signal output terminal GNi outputs a high level to turn on the threshold grabbing transistor T02, and the low enable signal output terminal GPi outputs a high level to turn on the reset transistor T05. The second operation period T2 corresponds to a light emitting period, and the high enable signal output terminal GNi outputs a low level to turn on the power supply voltage writing transistor T03 and the light emitting control transistor T04.

It should be noted that, the high enable signal output terminal GNi outputs a high level in both the reset phase and the data voltage writing phase, and the low enable signal output terminal GPi outputs a low level signal only in the data voltage writing phase, the low enable signal output terminal GPi outputs a low level signal for a time shorter than the high enable signal output terminal GNi outputs a high level signal in the first operation phase, and the high enable signal output terminal Gni outputs a high level signal for a time longer than the low enable signal output terminal GPi outputs a low level signal. In the first operation stage t1, since the first output unit K1 and the second output unit K2 are continuously turned on, the time for the first signal line X1i to transmit the effective signal in the first operation stage t1 is less than the time for the second signal line X2i to transmit the effective signal in the first operation stage t 1.

Fig. 5 is a schematic diagram of another shift register according to an embodiment of the present application, and fig. 6 is a schematic diagram of another shift register according to an embodiment of the present application. As shown in fig. 5 and 6, the control unit CT provided in the embodiment of the present application includes a latch LT, a third amplifier B3, and a fourth amplifier B4, where the output end of the latch LT is electrically connected to the input end of the third amplifier B3 and the input end of the fourth amplifier B4, respectively, and the output end of the third amplifier B3 is electrically connected to the first control output end p3 of the control unit CT, and the output end of the fourth amplifier B4 is electrically connected to the second control output end n3 of the control unit CT. That is, the signal transmitted to the control terminal of the first output unit K1 and the signal transmitted to the control terminal of the first shutdown unit G1 are delayed and amplified by the third amplifier B3, the signal transmitted to the control terminal of the second output unit K2 and the signal transmitted to the control terminal of the second shutdown unit G2 are delayed and amplified by the fourth amplifier B4, and the signal accuracy is higher.

Fig. 7 is an equivalent circuit diagram of a shift register corresponding to fig. 5, fig. 8 is an equivalent circuit diagram of a shift register corresponding to fig. 6, and fig. 9 is a timing chart of operations corresponding to the shift registers shown in fig. 7 and 8.

As shown in fig. 7 and 8, the latch LT in the control unit CT may be configured by a first nand gate NA1 and a second nand gate NA2, and a set terminal of the latch LT is electrically connected to the first control terminal Si of the control unit CT, and a reset terminal of the latch LT is electrically connected to the second control terminal Ri of the control unit CT.

As shown in fig. 7 and 8, the first nand gate NA1 includes a first transistor T11, a second transistor T12, a third transistor T13, and a fourth transistor T14. The first transistor T11 and the second transistor T12 are P-type transistors, and the source of the first transistor T11 and the source of the second transistor T12 are electrically connected to a high-level signal line, for example, the first potential signal line V1 is electrically connected to the first potential signal line V1, and the first potential signal line V1 transmits a high-level signal, and the drain of the first transistor T11 and the drain of the second transistor T12 are electrically connected to the first output terminal n1 of the first nand gate NA 1. The third transistor T13 and the fourth transistor T14 are both N-type transistors, and the source of the third transistor T13 is electrically connected to the drain of the fourth transistor T14, and the drain of the third transistor T13 is electrically connected to the first output terminal N1 of the first nand gate NA 1; the source of the fourth transistor T14 is electrically connected to a low-level signal line, for example, to the second potential signal line V2 and the second potential signal line V2 transmits a low-level signal. The grid electrode of the first transistor T11 and the grid electrode of the fourth transistor T14 are electrically connected with the second output end p1 of the second NAND gate NA 2; the gates of the second transistor T12 and the third transistor T13 are electrically connected to the set terminal of the latch LT, i.e., to the first control terminal Si of the control unit CT.

As shown in fig. 7 and 8, the second nand gate NA2 includes a fifth transistor T15, a sixth transistor T16, a seventh transistor T17, and an eighth transistor T18. The fifth transistor T15 and the sixth transistor T16 are P-type transistors, and the source of the fifth transistor T15 and the source of the sixth transistor T16 are electrically connected to a high-level signal line, for example, electrically connected to the first potential signal line V1 and the first potential signal line V1 transmits a high-level signal; the drain of the fifth transistor T15 and the drain of the sixth transistor T16 are electrically connected to the second output terminal p1 of the second nand gate NA 2. The seventh transistor T17 and the eighth transistor T18 are both N-type transistors, and the source of the seventh transistor T17 is electrically connected to the drain of the eighth transistor T18, and the drain of the seventh transistor T17 is electrically connected to the second output terminal p1 of the second nand gate NA 2; the source of the eighth transistor T18 is electrically connected to a low-level signal line, for example, to the second potential signal line V2 and the second potential signal line V2 transmits a low-level signal. The gate of the fifth transistor T15 and the gate of the eighth transistor T18 are electrically connected to the first output terminal n1 of the first nand gate NA 1; the gates of the sixth transistor T16 and the seventh transistor T17 are electrically connected to the reset terminal of the latch LT, i.e., to the second control terminal Ri of the control unit CT.

In the latch LT, the first output terminal n1 of the first nand gate NA1 may output and latch a high level signal or a low level signal, the second output terminal p1 of the second nand gate NA2 may output and latch a high level signal or a low level signal, and the first output terminal n1 is complementary to the potential of the signal output by the second output terminal p 1.

Referring to fig. 7 and 9, and fig. 8 and 9, in the beginning of the first working phase T1, the first control terminal Si starts to receive the low level signal to turn on the second transistor T12, the second control terminal Ri transmits the high level signal to turn on the seventh transistor T17, the first output terminal n1 of the first nand gate NA1 outputs the high level signal and the high level signal is transmitted to the gate of the eighth transistor T18 to turn on the eighth transistor T18, the second output terminal p1 of the second nand gate NA2 outputs the low level signal and is transmitted to the gate of the first transistor T11 to turn on the first transistor T11, and the first output terminal n1 of the first nand gate NA1 outputs the high level signal. In this way, when the set-end signal of the first nand gate NA1 and the reset-end signal of the second nand gate NA2 are unchanged, that is, the first control end Si continuously receives the low-level signal and the second control end Ri continuously receives the high-level signal, the first output end n1 of the first nand gate NA1 continuously outputs the high-level signal and the second output end p1 of the second nand gate NA2 continuously outputs the low-level signal. In the subsequent stage of the first operation stage T1, the first control terminal Si starts to transmit the high level signal such that the third transistor T13 is turned on, but does not affect the first transistor T11 to be turned on continuously and the first output terminal n1 of the first nand gate NA1 to output the high level signal continuously, and does not affect the seventh transistor T17 and the eighth transistor T18 to be turned on continuously and the second output terminal p1 of the second nand gate NA2 to output the low level signal continuously. That is, the state that the first output terminal n1 of the first nand gate NA1 continuously outputs the high level signal and the second output terminal p1 of the second nand gate NA2 continuously outputs the low level signal in the latch LT is latched, and is not affected by the signal received by the first control terminal Si.

With continued reference to fig. 7 and 9, and fig. 8 and 9, in the beginning of the second operation period T2, the first control terminal Si keeps outputting the high level signal such that the third transistor T13 is turned on, the second control terminal Ri transmits the low level signal such that the sixth transistor T16 is turned on, the second output terminal p1 of the second nand gate NA2 outputs the high level signal and the high level signal is transmitted to the gate of the fourth transistor T14 such that the fourth transistor T14 is turned on, the first output terminal n1 of the first nand gate NA1 outputs the low level signal and is transmitted to the gate of the fifth transistor T15 such that the fifth transistor T15 is turned on, and the second output terminal p1 of the second nand gate NA2 outputs the high level signal. In this way, when the set-end signal of the first nand gate NA1 and the reset-end signal of the second nand gate NA2 are unchanged, that is, the first control end Si continuously receives the high-level signal and the second control end Ri continuously receives the low-level signal, the first output end n1 of the first nand gate NA1 continuously outputs the low-level signal and the second output end p1 of the second nand gate NA2 continuously outputs the high-level signal. In the subsequent stage of the second operation stage T2, the second control terminal Ri starts to transmit the high level signal so that the seventh transistor T17 is turned on, but the fifth transistor T15 is not affected to be turned on continuously and the second output terminal p1 of the second nand gate NA2 continuously outputs the high level signal, and the third transistor T13 and the fourth transistor T14 are not affected to be turned on continuously and the first output terminal n1 of the first nand gate NA1 continuously outputs the low level signal. That is, the state that the first output terminal n1 of the first nand gate NA1 continuously outputs the low level signal and the second output terminal p1 of the second nand gate NA2 continuously outputs the high level signal in the latch LT is latched, and is not affected by the signal received by the second control terminal Ri.

As shown in fig. 7 and 8, the first output unit K1 is a transmission gate structure, and the second output unit K2 is also a transmission gate structure. The input end of the transmission gate in the first output unit K1 is used as the input end of the first output unit K1 and is electrically connected with the first signal line X1i, and the output end of the transmission gate in the first output unit K1 is used as the output end of the first output unit K1 and is electrically connected with the first amplifying input end p2 of the first amplifier B1. The input end of the transmission gate in the second output unit K2 is used as the input end of the second output unit K2 and is electrically connected with the second signal line X2i, and the output end of the transmission gate in the second output unit K2 is used as the output end of the second output unit K2 and is electrically connected with the second amplifying input end n2 of the second amplifier B2. In one implementation of the present application, the first control output P3 of the control unit CT is electrically connected to the gates of the transistors of the same channel type in the transmission gate of the first output unit K1 and in the transmission gate of the second output unit K2, for example, the first control output P3 of the control unit CT is electrically connected to the gate of the P-type transistor of the transmission gate of the first output unit K1 and to the gate of the P-type transistor of the transmission gate of the second output unit K2; the second control output N3 of the control unit CT is electrically connected to the gates of the same type of transistors in the transmission gate of the first output unit K1 and in the transmission gate of the second output unit K2, for example, the first control output p3 of the control unit CT is electrically connected to the gate of the N type transistor of the transmission gate of the first output unit K1 and to the gate of the N type transistor of the transmission gate of the second output unit K2. The first output unit K1 and the second output unit K2 can be turned on or off simultaneously, so as to improve the signal transmission efficiency and reduce the risk of leakage current.

As shown in fig. 7 and 8, the first turn-off unit G1 is a first turn-off transistor T21, and the second turn-off unit G2 is a second turn-off transistor T22. The gate of the first turn-off transistor T21 is electrically connected to the first control output terminal p3 of the control unit CT as the control terminal of the first turn-off unit G1, and the gate of the second turn-off transistor T22 is electrically connected to the second control output terminal n3 of the control unit CT as the control terminal of the second turn-off unit G2. The source electrode of the first turn-off transistor T21 is used as the input end of the first turn-off unit G1 and is electrically connected with the first potential signal line V1, and the drain electrode of the first turn-off transistor T21 is used as the output end of the first turn-off unit G1 and is electrically connected with the first amplifying input end p2 of the first amplifier B1; the source of the second turn-off transistor T2 serves as an input terminal of the second turn-off unit G2 and is electrically connected to the second potential signal line V2, and the drain of the second turn-off transistor T2 serves as an output terminal of the second turn-off unit G2 and is electrically connected to the second amplification input terminal n2 of the second amplifier B2.

The type of the first turn-off transistor T21 is different from the type of the transistor electrically connected to the first control output terminal p3 in the first output unit K1, and the type of the second turn-off transistor T22 is different from the type of the transistor electrically connected to the second control output terminal n3 in the second output unit K2. For example, the first turn-off transistor T21 is a P-type transistor, and the transistor electrically connected to the first control output terminal P3 in the first output unit K1 is an N-type transistor; the second turn-off transistor T22 is an N-type transistor, and the transistor electrically connected to the second control output terminal N3 in the second output unit K2 is a P-type transistor.

In one embodiment of the present application, as shown in fig. 5 and 7, the input terminal of the third amplifier B3 and the input terminal of the fourth amplifier B4 are electrically connected to the same output terminal of the control unit CT, for example, are electrically connected to the second output terminal p1 of the control unit CT. The operation of the shift register shown in fig. 7 is described below with reference to fig. 9.

In the beginning of the first working phase t1, when the first control terminal Si receives a low level signal and the second control terminal Ri receives a high level signal, the first output terminal n1 of the first nand gate NA1 outputs a high level signal, and the second output terminal p1 of the second nand gate NA2 outputs a low level signal. After the first control terminal Si starts to receive the high level signal in the subsequent stage of the first working stage t1, the first control terminal Ri still receives the high level signal, the first output terminal n1 of the first nand gate NA1 still outputs the high level signal, and the second output terminal p1 of the second nand gate NA2 still outputs the low level signal. That is, in the first operation phase t1, the first output terminal n1 of the first nand gate NA1 continuously outputs the high level signal, and the second output terminal p1 of the second nand gate NA2 continuously outputs the low level signal in the latch LT. The third amplifier B3 includes an odd number of inverters, and the low-level signal output by the second output terminal p1 in the latch LT is output by the first control output terminal p3 of the control unit CT after passing through the third amplifier B3; the fourth amplifier B4 includes an even number of inverters, and the low level signal output from the second output terminal p1 in the latch LT is output from the second control output terminal n3 of the control unit CT after passing through the fourth amplifier B4. In the first working stage t1, the first control output terminal p3 of the control unit CT continuously outputs a high-level signal so that the first output unit K1 and the second output unit K2 are continuously turned on, and the second control output terminal n3 of the control unit CT outputs a low-level signal so that the first output unit K1 and the second output unit K2 are continuously turned on.

In the low enable signal output stage of the first working stage t1, the first signal line X1i continuously outputs a low level signal, and then the output end of the first output unit K1 continuously outputs a low level signal; in the high enable signal output stage of the first operation stage t1, the second signal line X2i continuously outputs the high level signal, and the output terminal of the second output unit K2 continuously outputs the high level signal. The first amplifier B1 and the second amplifier B2 each include an even number of inverters, and the low-level signal continuously received by the first amplifying input terminal p2 of the first amplifier B1 is output by the low enable signal output terminal GP after passing through the first amplifier B1, and the high-level signal continuously received by the second amplifying input terminal n2 of the second amplifier B2 is output by the high enable signal output terminal GN after passing through the second amplifier B2.

In the beginning of the second operation phase t2, the first control terminal Si still receives the high level signal, and the second control terminal Ri receives the low level signal, the first output terminal n1 of the first nand gate NA1 outputs the low level signal, and the second output terminal p1 of the second nand gate NA2 outputs the high level signal. In the subsequent stage of the second operation stage t2, after the signal of the second control terminal Ri starts to change, the first output terminal n1 of the first nand gate NA1 still outputs the low level signal, and the second output terminal p1 of the second nand gate NA2 still outputs the high level signal. That is, in the second operation phase t2, the first output terminal n1 of the first nand gate NA1 continuously outputs the low level signal in the latch LT, and the second output terminal p1 of the second nand gate NA2 continuously outputs the high level signal. The high level signal output from the second output terminal p1 in the latch LT is output by the first control output terminal p3 of the control unit CT after passing through the third amplifier B3, and the high level signal output from the second output terminal p1 in the latch LT is output by the second control output terminal n3 of the control unit CT after passing through the fourth amplifier B4. In the first working phase t1, the first control output terminal p3 of the control unit CT continuously outputs a low level signal so that the first turn-off unit G1 is continuously turned on, and the second control output terminal n3 of the control unit CT continuously outputs a high level signal so that the second turn-off unit G2 is continuously turned on.

In the second operation phase t2, the first turn-off unit G1 is continuously turned on, so that the first amplification input terminal p2 of the first amplifier B1 continuously receives the high level signal transmitted by the first potential signal line V1, and the high level signal is output by the low enable signal output terminal GP; the second turn-off unit G2 is continuously turned on, so that the second amplification input terminal n2 of the second amplifier B2 continuously receives the low level signal transmitted by the second potential signal line V2, and the low level signal is output by the high enable signal output terminal GN.

In another embodiment of the present application, as shown in fig. 6 and 8, the input end of the third amplifier B3 and the input end of the fourth amplifier B4 are electrically connected to two output ends of the control unit CT, for example, the input end of the third amplifier B3 is electrically connected to the first output end n1 of the control unit CT, and the input end of the fourth amplifier B4 is electrically connected to the second output end p1 of the control unit CT. The operation of the shift register shown in fig. 8 is substantially the same as that of the shift register shown in fig. 7, and the difference between the operation of the shift register shown in fig. 8 and that of the shift register shown in fig. 7 will be described below with reference to fig. 9.

The shift register shown in fig. 8 is also different from the shift register shown in fig. 7 in that the third amplifier B3 and the fourth amplifier B4 each include an even number of inverters or an odd number of inverters, and as shown in fig. 8, the third amplifier B3 and the fourth amplifier B4 each include an even number of inverters.

Then in the first working stage t1, the high level signal output by the first output terminal n1 in the latch LT passes through the third amplifier B3 and then is output by the first control output terminal p3 of the control unit CT; the low level signal output from the second output terminal p1 in the latch LT is output from the second control output terminal n3 of the control unit CT after passing through the fourth amplifier B4.

In the second operation stage t2, the low-level signal output by the first output terminal n1 of the latch LT is output by the first control output terminal p3 of the control unit CT after passing through the third amplifier B3, and the high-level signal output by the second output terminal p1 of the latch LT is output by the second control output terminal n3 of the control unit CT after passing through the fourth amplifier B4.

In one embodiment of the present application, as shown in fig. 7, when the input terminal of the third amplifier B3 and the input terminal of the fourth amplifier B4 are electrically connected to the same output terminal of the control unit CT, the third amplifier B3 and the fourth amplifier B4 may share a part of the inverter. As shown in fig. 7, when the number of inverters in the fourth amplifier B4 is greater than the number of inverters in the third amplifier B3, the inverters in the third amplifier B3 may be an odd number of inverters in the fourth amplifier B4 and the odd number of inverters are inverters directly electrically connected to the latch LT and the inverters sequentially connected in series. Further, when the number of inverters in the fourth amplifier B4 is smaller than the number of inverters in the third amplifier B3, the inverters in the fourth amplifier B4 may be an even number of inverters in the third amplifier B3 and the even number of inverters are inverters directly electrically connected to the latch LT and inverters connected in series in order thereof.

In another embodiment of the present application, as shown in fig. 8, when the input terminal of the third amplifier B3 and the input terminal of the fourth amplifier B4 are electrically connected to the two output terminals of the control unit CT, the third amplifier B3 and the fourth amplifier B4 each include a corresponding number of inverters, that is, the inverters in the third amplifier B3 and the fourth amplifier B4 are not shared.

Fig. 10 is an equivalent circuit diagram of a shift register according to an embodiment of the present application, and fig. 11 is a timing chart corresponding to the shift register shown in fig. 10.

As shown in fig. 7, 8 and 10, the first, second, third and fourth amplifiers B1, B2, B3 and B4 are each composed of inverters connected in series. The number of inverters connected in series in the first amplifier B1 is determined by the signal of the first amplifying input terminal p2 of the first amplifier B1 and the signal to be outputted from the low-level enable signal output terminal GP.

As shown in fig. 7 and 8, when the signal at the first amplifying input terminal p2 of the first amplifier B1 and the signal to be output at the low-level enable signal output terminal GP are both in phase, the number of inverters connected in series in the first amplifier B1 is an even number. When the signal at the second amplifying input terminal n2 of the second amplifier B2 and the signal to be outputted at the high-level enable signal output terminal GN are both in phase, the number of inverters connected in series in the second amplifier B2 is an even number.

Fig. 10 is different from fig. 8 in that the second output terminal p1 of the second nand gate NA2 is electrically connected to the input terminal of the third amplifier B3, and the first output terminal n1 of the first nand gate NA1 is electrically connected to the input terminal of the fourth amplifier B4; the first turn-off transistor T21 is an N-type transistor and is electrically connected to the second potential signal line V2, and the second turn-off transistor T22 is a P-type transistor and is electrically connected to the first potential signal line V1. As shown in fig. 11, in the high enable signal output stage of the first operation stage t1, the second signal line X2 outputs the low enable signal, and the high enable signal output terminal GN needs to output the high enable signal; in the second working stage t2, the second control output terminal n3 outputs a low level signal to control the second turn-off unit G2 to turn on, and the high level signal on the first potential signal line V1 should be outputted by the high enable signal output terminal GN after passing through the second amplifier B2; the second amplifier B2 comprises an odd number of inverters. In the low enable signal output stage t1p of the first working stage t1, the first signal line X1i outputs a high enable signal, and the low enable signal output terminal GP needs to output a low enable signal; in the second working stage t2, the first control output end p3 outputs a high level signal to control the first turn-off unit G1 to turn on, and the low level signal on the second potential signal line V2 should be outputted by the low enable signal output end GP after passing through the second amplifier B2; the first amplifier B1 page includes an odd number of inverters. That is, when the signal of the first amplifying input terminal p2 of the first amplifier B1 and the signal to be outputted from the low-level enable signal output terminal GP are inverted signals, the number of inverters connected in series in the first amplifier B1 is an odd number; when the signal of the second amplifying input terminal n2 of the second amplifier B2 and the signal to be outputted from the high-level enable signal output terminal GN are inverted signals, the number of inverters connected in series in the second amplifier B2 is an odd number.

Based on the same principle, the number of inverters connected in series in the third amplifier B3 is determined by the signal at the input end of the third amplifier B3 and the signal to be output at the output end of the third amplifier B3, that is, the signal to be output at the first control output end p3 of the control unit CT; the number of inverters connected in series in the fourth amplifier B4 is determined by the signal at the input terminal of the fourth amplifier B4 and the signal to be output at the output terminal of the fourth amplifier B4, i.e. the signal to be output at the second control output terminal n3 of the control unit CT.

Fig. 12 is a schematic diagram of still another shift register provided in the embodiment of the present application, in one embodiment of the present application, as shown in fig. 12, the control unit CT provided in the embodiment of the present application may further include an initialization unit RT, in an initialization stage t0 before the first operation stage t1, after a signal output by the initialization unit RT is output through a first control output terminal p3 of the control unit CT, the first turn-off unit G1 is turned on, and a low enable signal output terminal GP outputs a high level signal; the signal output by the initializing unit RT is output through the second control output terminal n3 of the control unit CT, so that the second turn-off unit G2 is turned on, and the high enable signal output terminal GN outputs a low level signal.

Fig. 13 is an equivalent circuit diagram of a shift register corresponding to fig. 12, and fig. 14 is a timing diagram of a search operation corresponding to the shift register shown in fig. 13. As shown in fig. 12 and 13, the initializing unit RT is disposed between the third amplifier B3 and the fourth amplifier B4 and the latch LT, that is, the output terminal of the initializing unit RT is electrically connected to the input terminal of the third amplifier B3 and the input terminal of the fourth amplifier B4, respectively.

In one embodiment of the present application, as shown in fig. 13, when the signals received by the input terminal of the third amplifier B3 and the input terminal of the fourth amplifier B4 in the first working stage t1 originate from the same output terminal of the control unit CT, the shift register may include an initializing unit RT, and the output terminal of the initializing unit RT is electrically connected to the input terminal of the third amplifier B3 and the input terminal of the fourth amplifier B4.

In another embodiment of the present application, when the signals received by the input terminal of the third amplifier B3 and the input terminal of the fourth amplifier B4 in the first operation phase t1 originate from two different output terminals of the control unit CT, the shift register may include two initializing units RT. And the output terminal of one of the two initializing units RT may be electrically connected to the input terminal of the third amplifier B3, and the output terminal of the other initializing unit RT may be electrically connected to the input terminal of the fourth amplifier B4.

The operation of the initialization stage t0 is described below by taking an example in which the input terminal of the third amplifier B3 and the input terminal of the fourth amplifier B4 are shared and the shift register includes an initialization unit RT.

As shown in fig. 13, the initialization unit RT may be a nand gate, and specifically, the initialization unit RT may include a ninth transistor T31, a tenth transistor T32, an eleventh transistor T33, and a twelfth transistor T34. The ninth transistor T31 and the tenth transistor T32 are P-type transistors, and the source of the ninth transistor T31 and the source of the tenth transistor T32 are electrically connected to the initialization signal line RL, and the drain of the ninth transistor T31 and the drain of the tenth transistor T32 are electrically connected to the output terminal of the nand gate corresponding to the initialization unit RT. The eleventh transistor T33 and the twelfth transistor T34 are both N-type transistors, and the source of the eleventh transistor T33 is electrically connected to the drain of the twelfth transistor T34, and the drain of the eleventh transistor T33 is electrically connected to the output terminal of the nand gate corresponding to the initializing unit RT; the source of the twelfth transistor T34 is electrically connected to the low-level signal line, for example, to the second potential signal line V2 and the second potential signal line V2 transmits a low-level signal. The gate of the ninth transistor T31 and the gate of the twelfth transistor T34 are electrically connected to one control terminal of the nand gate corresponding to the initializing unit RT; the gates of the tenth transistor T32 and the eleventh transistor T33 are electrically connected to the other control terminal of the nand gate corresponding to the initializing unit RT and to the initializing control line RKi.

Referring to fig. 13 and 14, in the initialization stage t0, the initialization control line RKi transmits a low level signal, the initialization signal line RL transmits a high level signal, and the output terminal of the initialization unit RT outputs the high level signal. After passing through the third amplifier B3, the high-level signal output by the output end of the initializing unit RT is output by the first control output end p3 of the control unit CT to further control the first turn-off unit G1 to turn on, and the low enable signal output end GP outputs the high-level signal; after passing through the fourth amplifier B4, the high-level signal output by the output end of the initialization unit RT is output by the second control output end n3 of the control unit CT, so as to control the second turn-off unit G2 to turn on, and make the high enable signal output end GN output the low-level signal.

Note that, when the initialization signal line RL transmits a high level signal in the initialization stage t0, the initialization signal line RL may be multiplexed with the first potential signal line V1.

When the initializing unit RT is a nand gate structure, one control terminal of the nand gate structure is electrically connected to the initializing control line RKi, and a signal received by the other control terminal may be provided by the latch LT. In the shift register shown in fig. 13, the initialization unit RT needs to turn on the P-type transistor in the initialization stage t0, so that both control terminals of the nand gate corresponding to the initialization unit RT can receive the low level signal, one control terminal can receive the low level signal transmitted by the initialization control line RKi, and the low level signal received by the other control terminal can be provided by the latch LT. Specifically, a first inverter IT is disposed between the second output terminal p1 of the latch LT and one control terminal of the nand gate corresponding to the initializing unit RT, and the second output terminal p1 of the latch LT outputs a high-level signal in the initializing stage t0, and the high-level signal is changed into a low-level signal after passing through the first inverter IT and is transmitted to one control terminal of the nand gate corresponding to the initializing unit RT.

Referring to fig. 13 and 14, in the first working stage t1, the low level signal output by the second output terminal p1 in the latch LT is changed to the high level signal after passing through the first inverter IT, and meanwhile, the initialization control line RKi transmits the high level signal, so that the nand gate corresponding to the initialization unit RT outputs the low level signal. After passing through the third amplifier B3, the first control output terminal p3 of the control unit CT outputs a high-level signal, after passing through the fourth amplifier B4, the second control output terminal n3 of the control unit CT outputs a low-level signal, so that the first output unit K1 and the second output unit K2 are turned on, and then the low enable signal output terminal GP outputs a low-level signal in the low enable signal output stage t1p, and the high enable signal output terminal GN outputs a high-level signal in the high enable signal output stage.

Referring to fig. 13 and 14, in the second working stage t2, the high level signal output from the second output terminal p1 of the latch LT is changed to the low level signal after passing through the first inverter IT, and the nand gate corresponding to the initializing unit RT outputs the high level signal. The first control output end p3 of the control unit CT outputs a low-level signal after passing through the third amplifier B3, the second control output end n3 of the control unit CT outputs a high-level signal after passing through the fourth amplifier B4, so that the first turn-off unit G1 and the second turn-off unit G2 are turned on, the low enable signal output end GP outputs a high-level signal, and the high enable signal output end GN outputs a low-level signal. And as shown in fig. 14, the initialization control line RKi may transmit a high level signal; in addition, the initialization control line RKi may also transmit a low level signal.

As can be seen from the timing diagrams of fig. 9 and 14, the signal received by the second control terminal Ri is the same as the signal received by the second signal line X2i, and the second control terminal Ri in fig. 8 and 13 can be electrically connected to the second signal line X2i and the same signal terminal. As can be seen from the timing chart of fig. 11, the signal received by the second control terminal Ri and the signal received by the second signal line X2i are complementary signals, and then an inverter may be connected before the second control terminal Ri in fig. 10, and an output terminal of the inverter is electrically connected to the second control terminal Ri, and an input terminal is electrically connected to the second signal line X2i and the same signal terminal.

Fig. 15 is a partial equivalent circuit diagram of a gate driving circuit according to an embodiment of the present application, fig. 16 is a partial equivalent circuit diagram of another gate driving circuit according to an embodiment of the present application, and fig. 17 is a partial equivalent circuit diagram of another gate driving circuit according to an embodiment of the present application.

As shown in fig. 15 to 17, in the gate driving circuit provided in the embodiment of the present application, adjacent shift registers are cascaded, that is, one output terminal of the shift register of the previous stage is electrically connected to one control terminal of the shift register of the next stage. As shown in fig. 15 and 17, the low enable signal output terminal of the shift register of the upper stage is electrically connected to the first control terminal of the shift register of the lower stage. For example, the low enable signal output terminal GPi-1 of the i-1 st stage shift register SRi-1 is electrically connected to the first control terminal Si of the i-th stage shift register SRi, and the low enable signal output terminal GPi of the i-th stage shift register SRi is electrically connected to the first control terminal Si+1 of the i+1 th stage shift register SRi+1.

As shown in fig. 15 to 17, the non-display area BB of the display panel provided in the embodiment of the present application further includes three clock signal lines, which are a first clock signal line L1, a second clock signal line L2, and a third clock signal line L3, respectively. In the gate driving circuit provided by the embodiment of the application, each of three shift registers sequentially cascaded is a shift register group, and among the three shift registers in the shift register group, the second control end of each shift register is electrically connected with different clock signal lines, the first signal line X1i of each shift register is electrically connected with different clock signal lines, and the second control end and the second signal line of the same shift register are electrically connected with different clock signal lines. In addition, a second signal line in the same shift register is electrically connected to the second control terminal. As shown in fig. 15 to 17, in the i-1 st stage shift register SRi-1, the second signal line X2i-1 is electrically connected to the second control terminal Ri-1, the second control terminal Ri-1 is electrically connected to the first clock signal line L1, and the first signal line X1i-1 is electrically connected to the third clock signal line L3; in the ith shift register SRi, a second signal line X2i is electrically connected to a second control terminal Ri, the second control terminal Ri is electrically connected to a second clock signal line L2, and a first signal line X1i is electrically connected to a first clock signal line L1; in the i+1-th shift register sri+1, the second signal line x2i+1 is electrically connected to the second control terminal ri+1, the second control terminal ri+1 is electrically connected to the third clock signal line L3, and the first signal line x1i+1 is electrically connected to the second clock signal line L2.

The gate driving circuit shown in fig. 15 is formed by cascading shift registers shown in fig. 13, and the gate driving circuit shown in fig. 16 is formed by cascading shift registers shown in fig. 8.

Fig. 18 is a timing chart corresponding to the gate driving circuit shown in fig. 15 and 16, and it can be seen that the first clock signal line L1, the second clock signal line L2 and the third clock signal line L3 output pulse signals, and the times when the three start to output high level signals are sequentially performed, and the times when the three start to output low level signals are sequentially performed; correspondingly, the time when the high enable signal output end of the shift register of the adjacent stage outputs the high level signal is sequentially performed, and the time when the low enable signal output end of the shift register of the adjacent stage outputs the low level signal is sequentially performed. Referring to the timing diagrams shown in fig. 9, 14 and 18, the first clock signal line L1 provides signals to the second control terminal Ri-1 and the second signal line X2i-1 of the i-1 st stage shift register SRi-1 and provides signals to the first signal line X1i of the i-1 st stage shift register SRi, the second clock signal line L2 provides signals to the second control terminal Ri and the second signal line X2i of the i-1 st stage shift register SRi-1 and provides signals to the first signal line x1i+1 of the i+1 st stage shift register sri+1, and the third clock signal line L3 provides signals to the second control terminal ri+1 and the second signal line x2i+1 of the i+1 st stage shift register SRi-1.

The gate driving circuit shown in fig. 17 is formed by cascading shift registers shown in fig. 10.

Fig. 19 is a timing chart corresponding to the gate driving circuit shown in fig. 17, in which the first clock signal line L1, the second clock signal line L2 and the third clock signal line L3 output pulse signals, and the three start to output high level signals and the time to start to output low level signals also start to sequentially; correspondingly, the time when the high enable signal output end of the shift register of the adjacent stage outputs the high level signal is sequentially performed, and the time when the low enable signal output end of the shift register of the adjacent stage outputs the low level signal is sequentially performed. Referring to the timing diagrams shown in fig. 11 and 19, the first clock signal line L1 provides signals to the second control terminal Ri-1 and the second signal line X2i-1 of the i-1 stage shift register SRi-1 through an inverter, the first clock signal line L1 directly provides signals to the first signal line X1i of the i-1 stage shift register SRi, the second clock signal line L2 provides signals to the second control terminal Ri and the second signal line X2i of the i-1 stage shift register SRi through an inverter, the second clock signal line L2 directly provides signals to the first signal line x1i+1 of the i+1 stage shift register sri+1 through an inverter, the third clock signal line L3 provides signals to the second control terminal ri+1 and the second signal line x2i+1 of the i+1 stage shift register sri+1 through an inverter, and the third clock signal line L3 directly provides signals to the first signal line X1i-1 of the i-1 stage shift register SRi-1.

The application further provides an electronic device, and fig. 20 is a schematic diagram of the electronic device provided in the embodiment of the application, and as shown in fig. 20, the electronic device includes a display panel provided in any embodiment of the application. The specific structure of the display panel has been described in detail in the above embodiments, and will not be described herein. Of course, the electronic device shown in fig. 20 is only illustrative, and may be any electronic device having a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic book, a television, and a smart watch. In addition, the electronic device provided in the embodiment of the present application also includes a display area AA and a non-display area BB corresponding to the display area AA and the non-display area BB of the display panel.

The foregoing is merely specific embodiments of the present application, and any person skilled in the art may easily conceive of changes or substitutions within the technical scope of the present application, which should be covered by the protection scope of the present application. The protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A gate driving circuit for supplying a scanning signal to a pixel driving circuit;

the pixel driving circuit comprises at least one N-type transistor and at least one P-type transistor, wherein the grid electrode of the at least one N-type transistor is electrically connected with a first type scanning line, and the grid electrode of the at least one P-type transistor is electrically connected with a second type scanning line;

The grid driving circuit comprises N-stage cascaded shift registers, and N is a positive integer greater than or equal to 3; the shift register includes:

the high-enable signal output end is electrically connected with the first type of scanning lines;

the low-enable signal output end is electrically connected with the second type of scanning lines;

the first type scanning lines and the second type scanning lines which are electrically connected with the same pixel driving circuit are respectively electrically connected with the high enabling signal output end and the low enabling signal output end of the same shift register; in the same shift register, the time when the high enable signal output end outputs the high level signal covers the time when the low enable signal output end outputs the low level signal, and the time when the low enable signal output end outputs the low level signal is less than the time when the high enable signal output end outputs the high level signal.

2. The gate drive circuit according to claim 1, wherein the shift register includes:

the output end of the first amplifier is electrically connected with the low-enable signal output end;

the input end of the first output unit is electrically connected with the first signal wire, and the output end of the first output unit is electrically connected with the input end of the first amplifier; when the first output unit is conducted and the signal on the first signal line passes through the first output unit and the first amplifier, the low-level signal is output by the low-enable signal output end;

The input end of the first turn-off unit is electrically connected with the first potential signal line, and the output end of the first turn-off unit is electrically connected with the input end of the first amplifier; when the first turn-off unit is turned on and the signal on the first potential signal line passes through the first turn-off unit and the first amplifier, the low enable signal output end outputs a high level signal;

the output end of the second amplifier is electrically connected with the high-enable signal output end;

the input end of the second output unit is electrically connected with the second signal wire, and the output end of the second output unit is electrically connected with the input end of the second amplifier; when the second output unit is conducted and the signal on the second signal line passes through the second output unit and the second amplifier, the high-level signal is output by the high-enable signal output end;

the input end of the second turn-off unit is electrically connected with the second potential signal line, and the output end of the second turn-off unit is electrically connected with the input end of the second amplifier; when the second turn-off unit is turned on and the signal on the second potential signal line passes through the second turn-off unit and the second amplifier, the high enable signal output end outputs a low level signal.

3. The gate drive circuit according to claim 2, wherein the shift register further includes a control unit including:

The first control output end is respectively and electrically connected with the control end of the first output unit and the control end of the first turn-off unit and is used for controlling the on and off of the first output unit and the first turn-off unit, and the on time of the first output unit is different from that of the first turn-off unit;

the second control output end is respectively and electrically connected with the control end of the second output unit and the control end of the second turn-off unit and is used for controlling the second output unit and the second turn-off unit to be turned on and turned off, and the conduction time of the second output unit and the second turn-off unit is different.

4. The gate driving circuit according to claim 3, wherein,

the first output unit is of a transmission gate structure, the input end of the transmission gate corresponding to the first output unit is used as the input end of the first output unit, and the output end of the transmission gate corresponding to the first output unit is used as the output end of the first output unit;

the second output unit is of a transmission gate structure, the input end of the transmission gate corresponding to the second output unit is used as the input end of the second output unit, and the output end of the transmission gate corresponding to the second output unit is used as the output end of the second output unit.

5. The gate driving circuit of claim 4, wherein the gate driving circuit comprises a gate driver circuit,

the first control output end is electrically connected with the grid electrode of the transistor with the same channel type in the transmission gate structure corresponding to the first output unit and the transmission gate structure corresponding to the second output unit;

the second control output end is electrically connected with the transmission gate structure corresponding to the first output unit and the grid electrode of the transistor of the other channel type in the transmission gate structure corresponding to the second output unit;

the first output unit and the second output unit are simultaneously turned on or turned off.

6. The gate driving circuit of claim 5, wherein the gate driving circuit comprises a gate driver circuit,

the first turn-off unit is of a transistor structure, a grid electrode of a transistor corresponding to the first turn-off unit is used as a control end of the first turn-off unit, a source electrode of the transistor corresponding to the first turn-off unit is used as an input end of the first turn-off unit, and a drain electrode of the transistor corresponding to the first turn-off unit is used as an output end of the first turn-off unit;

the second turn-off unit is of a transistor structure, a grid electrode of a transistor corresponding to the second turn-off unit is used as a control end of the second turn-off unit, a source electrode of the transistor corresponding to the second turn-off unit is used as an input end of the second turn-off unit, and a drain electrode of the transistor corresponding to the second turn-off unit is used as an output end of the second turn-off unit.

7. The gate driving circuit according to claim 6, wherein,

the channel type of the transistor structure corresponding to the first turn-off unit is different from the channel type of the transistor electrically connected with the first control output end in the transmission gate structure corresponding to the first output unit;

and the channel type of the transistor structure corresponding to the second turn-off unit is different from the channel type of the transistor electrically connected with the second control output end in the transmission gate structure corresponding to the second output unit.

8. A gate drive circuit as recited in claim 3, wherein the control unit comprises a latch, a third amplifier, and a fourth amplifier, the output of the latch being electrically connected to the input of the third amplifier and the input of the fourth amplifier, respectively, the output of the third amplifier being electrically connected to the first control output of the control unit, the output of the fourth amplifier being electrically connected to the second control output of the control unit.

9. The gate drive circuit of claim 8, wherein the input of the third amplifier is electrically connected to the input of the fourth amplifier and the same output of the latch.

10. The gate drive circuit of claim 9, wherein the third amplifier and the fourth amplifier are each comprised of a plurality of inverters, at least a portion of the inverters in the third amplifier being common with at least a portion of the inverters in the fourth amplifier;

when the number of the inverters in the third amplifier is even, the number of the inverters in the fourth amplifier is odd; when the number of the inverters in the third amplifier is an odd number, the number of the inverters in the fourth amplifier is an even number.

11. The gate drive circuit of claim 8, wherein the input of the third amplifier and the input of the fourth amplifier are electrically connected to two outputs of the latch, respectively.

12. The gate driving circuit according to claim 3, wherein the control unit further comprises a latch, an initializing unit, a third amplifier, and a fourth amplifier;

the initialization unit is arranged between the latch and the third amplifier and between the latch and the fourth amplifier, the output end of the initialization unit is electrically connected with the input end of the third amplifier and the input end of the fourth amplifier respectively, the output end of the third amplifier is electrically connected with the first control output end of the control unit, and the output end of the fourth amplifier is electrically connected with the second control output end of the control unit.

13. The gate drive circuit of claim 12, wherein the third amplifier and the fourth amplifier are each comprised of a plurality of inverters, at least a portion of the inverters in the third amplifier being common with at least a portion of the inverters in the fourth amplifier;

14. The gate driving circuit according to claim 3, wherein the control unit further comprises a latch, two initializing units, a third amplifier, and a fourth amplifier;

the initialization unit is arranged between the latch and the third amplifier and between the initialization unit and the fourth amplifier, one output end of the initialization unit is electrically connected with the input end of the third amplifier, and the other output end of the initialization unit is electrically connected with the input end of the fourth amplifier.

15. The gate driving circuit according to claim 12 or 14, wherein the initialization unit is a nand gate circuit, one control terminal of the nand gate structure corresponding to the initialization unit is electrically connected to an initialization control line, and a signal of the other control terminal of the nand gate structure corresponding to the initialization unit is provided by the latch.

16. The gate driving circuit according to claim 2, wherein in the shift register of the N-stage cascade, the low enable signal output terminal or the high enable signal output terminal of the shift register of a previous stage is electrically connected to the first control terminal of the shift register of a next stage;

the N-stage cascaded shift register is electrically connected with three clock signal lines;

wherein, each three shift registers which are sequentially cascaded are a shift register group; in one of the shift register groups, the second control end of each shift register is electrically connected with different clock signal lines, the second signal line in the same shift register is electrically connected with the second control end, the first signal line of each shift register is electrically connected with different clock signal lines, and the second control end and the second signal line of the same shift register are electrically connected with different clock signal lines.

17. The gate driver circuit according to claim 16, wherein a time when the three clock signal lines start outputting the high level signal is sequentially performed and a time when the low level signal is sequentially outputted is also sequentially performed.

18. A display panel comprising a display region and a non-display region surrounding the display region;

the non-display region including the gate driving circuit as claimed in any one of claims 1 to 17;

the display area is provided with a pixel driving circuit and a light emitting device, the pixel driving circuit can control the light emitting device to emit light, and the grid driving circuit provides scanning signals for the pixel driving circuit.

19. An electronic device comprising the display panel of claim 18.