CN114446248A

CN114446248A - Grid driving circuit, display panel and display device

Info

Publication number: CN114446248A
Application number: CN202011199909.6A
Authority: CN
Inventors: 迟世鹏; 欧阳祥睿; 安亚斌; 贺海明
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-10-30
Filing date: 2020-10-30
Publication date: 2022-05-06
Anticipated expiration: 2040-10-30
Also published as: CN114446248B

Abstract

The embodiment of the application provides a grid drive circuit, a display panel and a display device, wherein the grid drive circuit is used for providing scanning signals for a pixel drive circuit which simultaneously comprises an N-type transistor and a P-type transistor; the shift register comprises a high enable signal output end electrically connected with the first type of scanning signal line and a low enable signal output end electrically connected with the second type of scanning signal line; the time of the high-level signal output end outputting the high-level signal covers the time of the low-level signal output end outputting the low-level signal, and the time of the low-level signal output end outputting the low-level signal is less than the time of the high-level signal output end outputting the high-level signal. In the gate driving circuit provided by the embodiment of the application, the shift register at the same stage can output both a low enable signal and a high enable signal, and only one group of gate driving circuits is needed to control the pixel driving circuit, so that a complex algorithm is not needed, and the display panel and the display device are ensured to have narrower frames.

Description

Grid driving circuit, display panel and display device

Technical Field

The application relates to the technical field of display, in particular to a gate driving circuit, a display panel and a display device.

Background

The organic light emitting display is increasingly applied in the fields of mobile communication, wearable products and the like, so that the research of the organic light emitting display becomes a hotspot. Generally, a switching transistor of a pixel driving circuit in an organic light emitting display screen adopts low-temperature polysilicon which is prepared by a mature preparation technology, but the transistor prepared by the low-temperature polysilicon easily generates large leakage current, so that the organic light emitting display screen obviously flickers during low-frequency display with low power consumption. Therefore, in the prior art, a plurality of switching transistors of a pixel driving circuit in an organic light emitting display screen include a low temperature polysilicon transistor and an oxide thin film transistor, so as to improve the problem of low frequency flicker caused by leakage current.

Oxide thin film transistors are typically N-type transistors with off-state leakage currents on the order of less than 1fA, while low temperature polysilicon transistors are typically P-type transistors with faster response speeds. In the prior art, in order to simultaneously drive the P-type transistor and the N-type transistor in the pixel driving circuit, two sets of gate driving circuits may be used to respectively output a signal for controlling the P-type transistor and a signal for controlling the N-type transistor, but the frame of the display screen may be increased.

Disclosure of Invention

The application provides a gate driving circuit, a display panel and a display device, which are used for solving the problems.

In a first aspect, an embodiment of the present application provides a gate driving circuit, configured to provide a scanning signal for a pixel driving circuit; the pixel driving circuit comprises at least one N-type transistor and at least one P-type transistor, wherein the grid electrode of the at least one N-type transistor is electrically connected with the first type of scanning line, and the grid electrode of the at least one P-type transistor is electrically connected with the second type of scanning line; the grid driving circuit comprises N stages of cascaded shift registers, wherein N is a positive integer greater than or equal to 3; the shift register comprises a high enable signal output end electrically connected with the first type of scanning signal line and a low enable signal output end electrically connected with the second type of scanning signal line; the time of the high-level signal output end outputting the high-level signal covers the time of the low-level signal output end outputting the low-level signal, and the time of the low-level signal output end outputting the low-level signal is less than the time of the high-level signal output end outputting the high-level signal.

In a second aspect, an embodiment of the present application provides a display panel, including a display area and a non-display area surrounding the display area; wherein the non-display region comprises a gate drive circuit as provided in the first aspect; the display area is provided with a pixel driving circuit and a light-emitting device, the pixel driving circuit can control the light-emitting device to emit light, and the grid driving circuit provides scanning signals for the pixel driving circuit.

In a third aspect, embodiments of the present application provide a display device, including the display panel provided in the second aspect.

In the gate driving circuit, the display panel and the display device provided in the embodiments of the present application, the shift register of the same stage may output a low enable signal to control a P-type transistor in the pixel driving circuit to operate, and may output a high enable signal to control an N-type transistor in the pixel driving circuit to operate. Therefore, the technical scheme of the application can control the pixel driving circuit PD only by using one group of gate driving circuits, does not need a complex algorithm and ensures that the display panel has a narrower frame.

Drawings

Fig. 1 is a schematic view of a display panel according to an embodiment of the present disclosure;

FIG. 2 is an enlarged view of a light-emitting pixel in a display panel;

fig. 3 is a schematic diagram of a shift register according to an embodiment of the present application;

FIG. 4 is a timing diagram of the shift register shown in FIG. 3;

FIG. 5 is a diagram illustrating another shift register according to an embodiment of the present disclosure;

FIG. 6 is a diagram illustrating another shift register according to an embodiment of the present application;

FIG. 7 is an equivalent circuit diagram of a shift register corresponding to FIG. 5;

FIG. 8 is an equivalent circuit diagram of a shift register corresponding to FIG. 6;

FIG. 9 is a timing diagram illustrating operation of the shift register shown in FIG. 7 and FIG. 8;

fig. 10 is an equivalent circuit diagram of a shift register according to an embodiment of the present application;

FIG. 11 is a timing diagram of the shift register shown in FIG. 10;

FIG. 12 is a diagram illustrating another shift register according to an embodiment of the present application;

FIG. 13 is an equivalent circuit diagram of a shift register corresponding to FIG. 12;

FIG. 14 is a timing diagram illustrating the operation of the shift register shown in FIG. 13;

fig. 15 is a partial equivalent circuit diagram of a gate driving circuit according to an embodiment of the present disclosure;

fig. 16 is a partial equivalent circuit diagram of another gate driving circuit provided in the embodiment of the present application;

fig. 17 is a partial equivalent circuit diagram of another gate driving circuit according to an embodiment of the present application;

FIG. 18 is a timing diagram of the gate driving circuit shown in FIG. 15 and FIG. 16;

FIG. 19 is a timing diagram of the gate driving circuit of FIG. 17;

fig. 20 is a schematic view of an electronic device provided in an embodiment of the present application.

Detailed Description

The terminology used in the description of the embodiments section of the present application is for the purpose of describing particular embodiments of the present application only and is not intended to be limiting of the present application.

The embodiment of the application provides a grid driving circuit, and a display panel and a display device using the grid driving circuit.

Fig. 1 is a schematic view of a display panel according to an embodiment of the present disclosure, and fig. 2 is an enlarged view of a light-emitting pixel in the display panel. As shown in fig. 1, a display panel provided in an embodiment of the present application includes a display area AA and a non-display area BB surrounding the display area AA. The display area AA includes a plurality of light-emitting pixels including a pixel driving circuit PD and a light-emitting device EL, wherein the pixel driving circuit PD can generate a light-emission driving current or a light-emission driving voltage for driving the light-emitting device EL to emit light during a display process. In embodiments of the present application, the light emitting device EL may be an active light emitting device, such as an organic light emitting diode, a micro light emitting diode, or the like.

As shown in fig. 2, the pixel driving circuit PD in the light emitting pixel includes a light emitting driving transistor TD, a data voltage writing transistor T01, a threshold grabbing transistor T02, a power voltage writing transistor T03, a light emission controlling transistor T04, a reset transistor T05, and a first capacitor C0. The light emitting driving transistor TD, the power voltage writing transistor T03, and the light emitting control transistor T04 may be P-type transistors, and the threshold grasping transistor T02 may be N-type transistors; the data voltage writing transistor T01 and the reset transistor T05 may be different types of transistors, for example, as shown in fig. 1 and 2, the data voltage writing transistor T01 is a P-type transistor, and the reset transistor T05 is an N-type transistor.

The source of the data voltage writing transistor T01 is electrically connected to the data signal line DL, and the drain of the data voltage writing transistor T01 is electrically connected to the source of the light emission driving transistor TD. The source of the threshold grasping transistor T02 is electrically connected to the drain of the light emission driving transistor TD, and the drain of the threshold grasping transistor T02 is electrically connected to the gate of the light emission driving transistor TD. The source of the power supply voltage writing transistor T03 is electrically connected to a power supply voltage line PVDD, and the drain of the power supply voltage writing transistor T03 is electrically connected to the source of the light emission driving transistor TD. The source of the light emission controlling transistor T04 is electrically connected to the drain of the light emission driving transistor TD, and the drain of the light emission controlling transistor T04 is electrically connected to the light emitting device EL. The source of the reset transistor T05 is electrically connected to a reset signal line REF, and the drain of the reset transistor T05 is electrically connected to the drain of the threshold grasping transistor T02. A first plate of the first capacitor C0 is electrically connected to the gate of the light-emitting drive transistor TD, and a second plate of the first capacitor C0 is electrically connected to the power supply voltage line PVDD.

The operation of the pixel driving circuit shown in fig. 2, which includes a reset phase, a data voltage writing phase and a light emitting phase, will be described.

In the reset phase, the threshold grasping transistor T02 and the reset transistor T05 are turned on, and the reset signal line REF transmits a reset signal, so that the reset signal is written into the gate of the light emitting driving transistor TD, the gate of the light emitting driving transistor TD is reset, and the first capacitor C0 stores the reset signal.

In the data voltage writing phase, the power voltage writing transistor T03 and the light emitting control transistor T04 are turned off, the data voltage writing transistor T01 and the threshold grasping transistor T02 are turned on, and the data voltage is transmitted on the data signal line DL, and since the potential of the data voltage is higher than that of the reset signal, the light emitting driving transistor TD is turned on and the data voltage is written into the gate electrode of the light emitting driving transistor TD;

in the light emitting period, the threshold grabbing transistor T02 is turned off, the power voltage writing transistor T03 and the light emitting control transistor T04 are turned on, the power voltage line PVDD transmits the power voltage, the power voltage is transmitted to the source of the light emitting driving transistor TD, and the power voltage is greater than the data voltage, and the light emitting driving transistor TD generates the light emitting driving current and transmits the light emitting driving current to the light emitting device EL.

In the light emitting stage, if the potential of the gate of the light emitting driving transistor TD changes, the light emitting driving current will change, and the display brightness will be affected. Since the gate of the light-emitting driving transistor TD is electrically connected to the threshold grasping transistor T02, the leakage current generated by the threshold grasping transistor T02 is a factor of the change in the gate potential of the light-emitting driving transistor TD. Since the leakage current of the N-type transistor is small relative to the P-type transistor, the threshold grasping transistor T02 is usually set as an N-type transistor in order to avoid the leakage current of the threshold grasping transistor T02 affecting the gate potential of the light emission driving transistor TD during the light emission phase. Some transistors in the pixel driving circuit PD are P-type transistors, for example, the power voltage writing transistor T03 and the light emitting control transistor T04 are P-type transistors, and can be turned on by using a smaller driving voltage in the light emitting stage.

It should be noted that fig. 2 illustrates an equivalent circuit diagram of a pixel driving circuit PD in a light-emitting pixel, and the pixel driving circuit PD provided in this embodiment may also have other circuit structures. However, the pixel driving circuit PD in the display panel and the display device provided in the embodiment of the present application includes a plurality of transistors, the plurality of transistors includes a P-type transistor and an N-type transistor, and the potentials required for turning on the P-type transistor and turning on the N-type transistor are different, so that the scan lines electrically connected to the gates of the plurality of transistors in the pixel driving circuit PD include a first type scan line and a second type scan line, and the N-type transistor and the P-type transistor can be controlled by transmitting scan signals on the first type scan line and the second type scan line, respectively.

As shown in fig. 1, the display panel includes a plurality of first scan lines SL11, SL21, … …, SLi1, … …, and SLN1, and a plurality of second scan lines SL12, SL22, … …, SLi2, … …, and SLN 2. In the pixel driving circuits PD located in the same row, at least one N-type transistor in each pixel driving circuit PD is electrically connected to the first type scanning line, and at least one P-type transistor in each pixel driving circuit PD is electrically connected to the second type scanning line. As shown in fig. 1, the display panel includes N rows of pixel driving circuits PD, N scan lines of the first type SL11, SL21, … …, SLi1, … …, SLN1, and N scan lines of the second type SL12, SL22, … …, SLi2, … …, and SLN 2. At least one N-type transistor, such as a threshold grabbing transistor T02, in each pixel driving circuit PD in the pixel driving circuits PD in the ith row is electrically connected with the ith first-type scanning line SLi 1; at least one P-type transistor, for example, the power supply voltage writing transistor T03, in each of the pixel driving circuits PD in the ith row is electrically connected to the ith second-type scanning line SLi 2. Wherein N is a positive integer greater than or equal to 3, i is greater than or equal to 1 and less than or equal to N, and i is a positive integer.

As can be known from the working process of the pixel driving circuit, the threshold grabbing transistor T02 and the power voltage writing transistor T03, and the light emitting control transistor T04 have different on and off times, and the threshold grabbing transistor T02 and the power voltage writing transistor T03, and the light emitting control transistor T04 have different transistor types, so that the threshold grabbing transistor T02, the power voltage writing transistor T03, and the light emitting control transistor T04 in the same row may be connected to the same first type scan line, for example, all connected to the first type scan line SLi 1; in addition, the turn-on time of the reset transistor T05 is different from that of the data voltage writing transistor T01, and the two transistors are different types of transistors, so that the reset transistor T05 and the data voltage writing transistor T0 in the same row can be connected to the same scan line, for example, both of them are electrically connected to the second type scan line SLi2, and it should be noted that, since the threshold grabbing transistor T02 is turned off in the light emitting stage, the normal light emission of the light emitting device is not affected even if the reset transistor T05 is turned on.

In the embodiment of the present application, as shown in fig. 1, the non-display area BB of the display panel includes a gate driving circuit, the gate driving circuit includes N stages of cascaded shift registers SR1, SR2, … …, SRi, … …, and SRN, the cascaded shift registers SR … …/… …/SRi/… …/SRN of each stage include at least two output terminals, the at least two output terminals include a low enable signal output terminal GP … …/… …/… …/… …/GPN and a high enable signal output terminal GN … …/… …/… …/… …/GNN, wherein the low enable signal output terminal GP … …/… …/GPi/… …/… …/685n is electrically connected to the second-type scanning line SL … …/… …/… …/i … …/… …/… …/… …/SLN, and the first-type SLs … …/… …/… …/N and the second-type of the second-type The scanning lines SL11, SL21, … …, SLi1, … …, and SLN1 are electrically connected, respectively. And the first scanning lines and the second scanning lines which are correspondingly and electrically connected with the pixel driving circuits PD in the same row are respectively and electrically connected with the high enable signal output end and the low enable signal output end of the same-stage shift register. For example, as shown in fig. 1, the first-type scan line SLi1 and the second-type scan line SLi2 electrically connected to the pixel driving circuits PD in the ith row are electrically connected to the high enable signal output terminal GNi and the low enable signal output terminal GPi of the ith stage shift register SRi, respectively.

That is, the shift register of the same stage can output a low enable signal and transmit the low enable signal to the P-type transistor in the second-type scan line control pixel driving circuit PD for operation, and can output a high enable signal and transmit the high enable signal to the N-type transistor in the first-type scan line control pixel driving circuit PD for operation. Therefore, the technical scheme of the application can control the pixel driving circuit PD only by using one group of gate driving circuits, does not need a complex algorithm and ensures that the display panel has a narrower frame.

The shift register further includes a first control terminal Si, and the shift register with multiple cascaded stages means that, in two shift registers arranged adjacently, one output terminal (for example, a low enable signal output terminal) of a shift register of a previous stage is electrically connected to the first control terminal Si of a shift register of a next stage, that is, a signal for controlling the next stage to be turned on is derived from the output terminal of the shift register of the previous stage electrically connected thereto. Meanwhile, as shown in fig. 1, the first control terminal Si of the first stage shift register SR1 is electrically connected to the start signal line STV.

Fig. 3 is a schematic diagram of a shift register provided in an embodiment of the present application, and fig. 3 and the following drawings illustrate a structure and an operating principle of the shift register provided in the embodiment of the present application by taking an ith stage of shift register SRi in a gate driving circuit as an example. However, any one stage of shift register in the scan driver circuit provided in the present application may be the same as the ith stage of shift register SRi.

Referring to fig. 3, the shift register SRi provided in the embodiment of the present application includes a control unit CT, a first output unit K1, a second output unit K2, a first turn-off unit G1, a second turn-off unit G2, a first amplifier B1, and a second amplifier B2.

Wherein the control unit CT comprises a first control output p3 and a second control output n 3.

The first control output terminal p3 is electrically connected to a control terminal of the first output unit K1 and to a control terminal of the first turn-off unit G1, and is configured to control on and off of the first output unit K1 and on and off of the first turn-off unit G1, where the first output unit K1 and the first turn-off unit G1 are turned on for different time periods. The input terminal of the first output unit K1 is electrically connected to the first signal line X1i, and the output terminal is electrically connected to the first amplification input terminal p2 of the first amplifier B1. The input terminal of the first turn-off unit G1 is electrically connected to the first potential signal line V1, and the output terminal is electrically connected to the first amplification input terminal p2 of the first amplifier B1. The output terminal of the first amplifier B1 is electrically connected to the low enable signal output terminal GPi.

When the first output unit K1 is turned on by the signal output from the first control output terminal p3 of the control unit CT, the signal on the first signal line X1i is transmitted to the first amplification input terminal p2 of the first amplifier B1 through the first output unit K1, and then a low-level signal is output from the low-enable signal output terminal GPi; when the first turn-off unit G1 is turned on by the signal output from the first control output terminal p3 of the control unit CT, the signal on the first potential signal line V1 is transmitted to the first amplification input terminal p2 of the first amplifier B1 through the first turn-off unit G1, and then the low-enable signal output terminal GPi outputs a high-level signal.

The second control output terminal n3 is electrically connected to the control terminal of the second output unit K2 and to the control terminal of the second turn-off unit G2, and is used to control the on and off of the second output unit K2 and the on and off of the second turn-off unit G2, and the on times of the second output unit K2 and the second turn-off unit G2 are different. An input end of the second output unit K2 is electrically connected to the second signal line X2i, and an output end thereof is electrically connected to the second amplification input end n2 of the second amplifier B2; an input end of the second turn-off unit G2 is electrically connected to the second potential signal line V2, and an output end thereof is electrically connected to the second amplification input end n2 of the second amplifier B2; the output of the second amplifier B2 is electrically connected to the high enable signal output GNi.

When the second output unit K2 is turned on by the signal output from the second control output terminal n3 of the control unit CT, the signal on the second signal line X2i is transmitted to the second amplification input terminal n2 of the second amplifier B2 through the second output unit K2, and then the high-level signal is output from the high-enable signal output terminal GNi; when the second switch-off unit G2 is turned on by the signal output from the second control output terminal n3 of the control unit CT, the signal on the second potential signal line V2 is transmitted to the second amplification input terminal n2 of the second amplifier B2 through the second switch-off unit G2, and then the high enable signal output terminal GNi outputs a low level signal.

Fig. 4 is a timing diagram of the shift register shown in fig. 3. It is assumed that the first output unit K1 is turned on and the first turn-off unit G1 is turned off when the first control output terminal p3 outputs a high level signal, and the first output unit K1 is turned off and the first turn-off unit G1 is turned on when the first control output terminal p3 outputs a low level signal; when the second control output terminal n3 outputs a low level signal, the second output unit K2 is turned on and the second turn-off unit G2 is turned off, and when the second control output terminal n3 outputs a high level signal, the second output unit K2 is turned off and the second turn-off unit G2 is turned on.

As shown in fig. 4, in the first operation phase t1, the low enable signal output terminal GPi of the shift register SRi can output a low level signal, so that the P-type transistor controlled by the second type scanning line SLi2 electrically connected to the low enable signal output terminal GPi in the pixel driving circuit PD is turned on; the high enable signal output terminal GNi can output a high level signal to turn on the N-type transistor controlled by the first scan line SLi1 electrically connected to the high enable signal output terminal GNi in the pixel driving circuit PD.

The operation of the shift register SRi in the first operation phase t1 according to the embodiment of the present application is described below with reference to fig. 3 and 4. In the low enable signal output phase t1p of the first operation phase t1, the first control output terminal p3 of the control unit CT outputs a high level signal to turn on the first output unit K1, and the first signal line X1i transmits a low level signal, then the first amplification input terminal p2 of the first amplifier B1 receives the low level signal and the first amplifier B1 amplifies the low level signal and outputs the amplified low level signal through the low enable signal output terminal GPi; in the high enable signal output phase t1n of the first operation phase t1, the second control output terminal n3 of the control unit CT outputs a low level signal to turn on the second output unit K2, and the second signal line X2i transmits a high level signal, then the second amplification input terminal n2 of the second amplifier B2 receives the high level signal and the second amplifier B2 amplifies the high level signal and outputs the amplified high level signal from the high enable signal output terminal GNi.

As shown in fig. 4, in the second operation phase t2, the low enable signal output terminal GPi of the shift register SRi outputs a high level signal, so that the P-type transistor controlled by the first-type scan line SLi1 electrically connected to the low enable signal output terminal GPi in the pixel driving circuit PD is turned off; the high enable signal output terminal GNi outputs a low level signal to turn off the N-type transistor controlled by the second type scan line SLi2 electrically connected to the high enable signal output terminal GNi in the pixel driving circuit PD.

The operation of the shift register SRi in the second operation phase t2 according to the embodiment of the present application is described below with reference to fig. 3 and 4. The first control output terminal p3 of the control unit CT outputs a low level signal to turn on the first turn-off unit G1, and the first potential signal line V1 transmits a high level signal, then the first amplification input terminal p2 of the first amplifier B1 receives the high level signal and after the first amplifier B1 amplifies the high level signal, the high level signal is output by the low enable signal output terminal GPi; the second control output terminal n3 of the control unit CT outputs a high level signal to turn on the second turn-off unit G2, and the second potential signal line V2 transmits a low level signal, then the second amplification input terminal n2 of the second amplifier B2 receives the low level signal and the second amplifier B2 amplifies the low level signal, and then the low level signal is output from the high enable signal output terminal GNi.

In one implementation manner of the present application, in the first operation phase t1, the first control output p3 of the control unit CT may also output a low level signal to turn on the first output unit K1. In the first operation phase t1, whether the first control output terminal p3 of the control unit CT outputs a high level or a low level, the output level signal should make the first output unit K1 conduct, and make the first output unit K1 conduct continuously in the first operation phase t 1. In one implementation manner of the present application, in the first operation phase t1, the second control output terminal n3 of the control unit CT may also output a high-level signal to turn on the second output unit K2. In the first operation phase t1, whether the second control output terminal n3 of the control unit CT outputs a high level or a low level, the output level signal should make the second output unit K2 conduct, and make the second output unit K2 conduct continuously in the first operation phase t 1.

In one implementation of the present application, as shown in fig. 4, the first signal line X1i and the second signal line X2i may output pulse signals. It should be noted that, in the shift register SRi provided in the embodiment of the present application, the first signal line X1i may also output a high level signal in the low enable signal output stage t1p of the first operation stage t1, but no matter whether the first signal line X1i outputs a low level or a high level in the low enable signal output stage t1p of the first operation stage t1, the first signal line X1 needs to be configured to cooperate with the corresponding first amplifier B1, so as to ensure that the signal on the first signal line X1i is a low level signal after the signal is output through the first output unit K1 and then passes through the first amplifier B1 and is output by the low enable signal output terminal GPi. In the shift register SRi provided in the embodiment of the present application, the second signal line X2i may also output a low level signal at the high enable signal output stage t1n of the first working stage t1, but no matter the second signal line X2i outputs a low level or a high level at the high enable signal output stage t1n of the first working stage t1, the second signal line X2i needs to be configured in cooperation with the corresponding second amplifier B2, so as to ensure that the signal on the second signal line X2i is output by the second output unit K2 and then output by the second amplifier B2 and then output a high level signal by the high enable signal output terminal GNi.

In one implementation manner of the present application, in the second operation phase t2, the first control output p3 of the control unit CT may also output a high-level signal to turn on the first turn-off unit G1. In the second operation phase t2, whether the first control output terminal p3 of the control unit CT outputs a high level or a low level, the output level signal should make the first turn-off unit G1 turn on, and make the first turn-off unit G1 turn on continuously in the second operation phase t 2. In one implementation manner of the present application, in the second operation phase t2, the second control output n3 of the control unit CT may also output a low level signal to turn on the second turn-off unit G2. In the second operation phase t2, whether the second control output n3 of the control unit CT outputs a high level or a low level, the output level signal should make the second turn-off unit G2 turn on, and make the second turn-off unit G2 turn on continuously in the second operation phase t 2.

In one implementation of the present application, as shown in fig. 4, the first potential signal line V1 and the second potential signal line V2 may continuously output constant potential signals. It should be noted that, in the shift register SRi provided in the embodiment of the present application, the first potential signal line V1 may also transmit a low-level signal, but no matter the first potential signal line V1 transmits a low-level signal or a high-level signal, the first potential signal line V1 needs to be arranged in cooperation with the corresponding first amplifier B1, so as to ensure that the signal on the first potential signal line V1 is output through the first shutdown unit G1, then passes through the first amplifier B1, and then is output through the low-level enable signal output terminal GPi. In the shift register SRi provided by the embodiment of the application, the second potential signal line V2 can also transmit a high level signal, but no matter the second potential signal line V2 transmits a low level signal or a high level signal, the second potential signal line V2 needs to be matched with the corresponding second amplifier B2, so as to ensure that the signal on the second potential signal line V2 is output by the second turn-off unit G2 and then output by the high enable signal output end GNi after passing through the second amplifier B2.

In the embodiment of the present application, in the first operation phase t1, the first control output terminal p3 and the second control output terminal n3 of the control unit CT in the shift register SRi respectively output the enable signals for turning on the first output unit K1 and the second output unit K2, the times at which the first control output terminal p3 and the second control output terminal n3 of the control unit CT output the enable signals are the same and the time lasts, and the time of the low level signal output by the low enable signal output terminal GPi and the time of the high level signal output by the high enable signal output terminal GN are controlled by the change of the signal on the first signal line X1i and the change of the signal on the second signal line X2 i. In the second working phase t2, the first control output terminal p3 and the second control output terminal n3 of the control unit CT in the shift register SRi respectively output signals for turning on the first turn-off unit G1 and the second turn-off unit G2, the time when the first control output terminal p3 and the second control output terminal n3 of the control unit CT output the signals is the same and the time lasts, and the constant potential signals are continuously output through the first potential signal line V1 and the second potential signal line V2, so that the high level signal continuously output from the low enable signal output terminal GP and the low level signal continuously output from the high enable signal output terminal GN are realized. Only one control unit CT is included in the shift register SR, simplifying the circuit structure of the shift register SRi.

With reference to fig. 1, 2, 3 and 4, the first operating phase t1 of the shift register may correspond to a reset phase and a data voltage writing phase of the pixel driving circuit PD, and the second operating phase t2 may correspond to a light emitting phase of the pixel driving circuit. The low-enable signal output stage T1p of the first operating stage T1 specifically corresponds to the data voltage write-in stage, at this time, the high-enable signal output terminal GNi outputs a high level to turn on the threshold capture transistor T02, and the low-enable signal output terminal GPi outputs a low level to turn on the data voltage write-in transistor T01. The stage before the low enable signal output stage T1p of the first operating stage T1 corresponds to the reset stage, at this time, the high enable signal output terminal GNi outputs a high level to turn on the threshold grabbing transistor T02, and the low enable signal output terminal GPi outputs a high level to turn on the reset transistor T05. The second operation period T2 may correspond to a light-emitting period, in which the high-enable signal output terminal GNi outputs a low level to turn on the power voltage writing transistor T03 and the light-emitting control transistor T04.

It should be noted that, the high-enable signal output terminal GNi outputs high level during both the reset phase and the data voltage writing phase, and the low-enable signal output terminal GPi outputs low level signal only during the data voltage writing phase, in the first operation phase, the time for the low-enable signal output terminal GPi to output low level signal is less than the time for the high-enable signal output terminal GNi to output high level signal, and the time for the high-enable signal output terminal Gni to output high level signal overlaps the time for the low-enable signal output terminal GPi to output low level signal. Since the first output unit K1 and the second output unit K2 are continuously turned on during the first operation period t1, the time for the first signal line X1i to transmit the active signal during the first operation period t1 is less than the time for the second signal line X2i to transmit the active signal during the first operation period t 1.

Fig. 5 is a schematic diagram of another shift register provided in the embodiment of the present application, and fig. 6 is a schematic diagram of another shift register provided in the embodiment of the present application. As shown in fig. 5 and fig. 6, the control unit CT provided in the embodiment of the present application includes a latch LT, a third amplifier B3, and a fourth amplifier B4, wherein an output terminal of the latch LT is electrically connected to an input terminal of the third amplifier B3 and an input terminal of the fourth amplifier B4, respectively, an output terminal of the third amplifier B3 is electrically connected to the first control output terminal p3 of the control unit CT, and an output terminal of the fourth amplifier B4 is electrically connected to the second control output terminal n3 of the control unit CT. That is, the signal transmitted to the control terminal of the first output unit K1 and the signal transmitted to the control terminal of the first shutdown unit G1 are delayed and amplified by the third amplifier B3, and the signal transmitted to the control terminal of the second output unit K2 and the signal transmitted to the control terminal of the second shutdown unit G2 are delayed and amplified by the fourth amplifier B4, so that the accuracy of the signals is higher.

Fig. 7 is an equivalent circuit diagram of a shift register corresponding to fig. 5, fig. 8 is an equivalent circuit diagram of a shift register corresponding to fig. 6, and fig. 9 is an operation timing diagram corresponding to the shift registers shown in fig. 7 and 8.

As shown in fig. 7 and 8, the latch LT in the control unit CT may be composed of a first nand gate NA1 and a second nand gate NA2, and the set terminal of the latch LT is electrically connected to the first control terminal Si of the control unit CT, and the reset terminal of the latch LT is electrically connected to the second control terminal Ri of the control unit CT.

As shown in fig. 7 and 8, the first nand gate NA1 includes a first transistor T11, a second transistor T12, a third transistor T13 and a fourth transistor T14. The first transistor T11 and the second transistor T12 are both P-type transistors, and the source of the first transistor T11 and the source of the second transistor T12 are electrically connected to a high-level signal line, for example, the first potential signal line V1 is electrically connected and the first potential signal line V1 transmits a high-level signal, and the drain of the first transistor T11 and the drain of the second transistor T12 are electrically connected to the first output terminal n1 of the first nand gate NA 1. The third transistor T13 and the fourth transistor T14 are both N-type transistors, and the source of the third transistor T13 is electrically connected to the drain of the fourth transistor T14, and the drain of the third transistor T13 is electrically connected to the first output terminal N1 of the first nand gate NA 1; the source of the fourth transistor T14 is electrically connected to a low-level signal line, for example, the second potential signal line V2 and the second potential signal line V2 transmits a low-level signal. The gate of the first transistor T11 and the gate of the fourth transistor T14 are electrically connected to the second output p1 of the second nand gate NA 2; the gate of the second transistor T12 and the gate of the third transistor T13 are electrically connected to the set terminal of the latch LT, i.e., to the first control terminal Si of the control unit CT.

As shown in fig. 7 and 8, the second nand gate NA2 includes a fifth transistor T15, a sixth transistor T16, a seventh transistor T17 and an eighth transistor T18. The fifth transistor T15 and the sixth transistor T16 are both P-type transistors, and the source of the fifth transistor T15 and the source of the sixth transistor T16 are electrically connected to a high-level signal line, for example, the first potential signal line V1 is electrically connected and the first potential signal line V1 transmits a high-level signal; the drain of the fifth transistor T15 and the drain of the sixth transistor T16 are electrically connected to the second output p1 of the second nand gate NA 2. The seventh transistor T17 and the eighth transistor T18 are both N-type transistors, a source of the seventh transistor T17 is electrically connected to a drain of the eighth transistor T18, and a drain of the seventh transistor T17 is electrically connected to the second output terminal p1 of the second nand gate NA 2; the source of the eighth transistor T18 is electrically connected to a low-level signal line, for example, the second potential signal line V2 and the second potential signal line V2 transmits a low-level signal. The gate of the fifth transistor T15 and the gate of the eighth transistor T18 are electrically connected to the first output n1 of the first nand gate NA 1; the gate of the sixth transistor T16 and the gate of the seventh transistor T17 are electrically connected to the reset terminal of the latch LT, i.e., the second control terminal Ri of the control unit CT.

In the latch LT, the first output terminal n1 of the first nand gate NA1 may output and latch a high level signal or a low level signal, the second output terminal p1 of the second nand gate NA2 may output and latch a high level signal or a low level signal, and the first output terminal n1 is complementary to the potential of the signal output by the second output terminal p 1.

Referring to fig. 7 and 9, 8 and 9, in the beginning stage of the first operation phase T1, the first control terminal Si starts to receive the low level signal to turn on the second transistor T12, the second control terminal Ri transmits the high level signal to turn on the seventh transistor T17, the first output terminal n1 of the first nand gate NA1 outputs the high level signal and the high level signal is transmitted to the gate of the eighth transistor T18 to turn on the eighth transistor T18, the second output terminal p1 of the second nand gate NA2 outputs the low level signal and transmits the low level signal to the gate of the first transistor T11 to turn on the first transistor T11, and the first output terminal n1 of the first nand gate NA1 outputs the high level signal. In this way, when the set terminal of the first nand gate NA1 and the reset terminal of the second nand gate NA2 have no change, i.e., the first control terminal Si continuously receives the low signal and the second control terminal Ri continuously receives the high signal, the first output terminal n1 of the first nand gate NA1 continuously outputs the high signal, and the second output terminal p1 of the second nand gate NA2 continuously outputs the low signal. In the subsequent phase of the first operation phase T1, the first control terminal Si starts to transmit the high signal, so that the third transistor T13 is turned on, but does not affect the first transistor T11 to be turned on continuously and the first output terminal n1 of the first nand gate NA1 to output the high signal continuously, and does not affect the seventh transistor T17 and the eighth transistor T18 to be turned on continuously and the second output terminal p1 of the second nand gate NA2 to output the low signal continuously. That is, the state in which the first output n1 of the first nand gate NA1 continues to output the high signal and the second output p1 of the second nand gate NA2 continues to output the low signal in the latch LT is latched without being affected by the signal received by the first control terminal Si.

With reference to fig. 7, 9, 8 and 9, in the beginning stage of the second operation phase T2, the first control terminal Si keeps outputting the high level signal to turn on the third transistor T13, the second control terminal Ri transmits the low level signal to turn on the sixth transistor T16, the second output terminal p1 of the second nand gate NA2 outputs the high level signal and the high level signal is transmitted to the gate of the fourth transistor T14 to turn on the fourth transistor T14, the first output terminal n1 of the first nand gate NA1 outputs the low level signal and transmits the low level signal to the gate of the fifth transistor T15 to turn on the fifth transistor T15, and the second output terminal p1 of the second nand gate NA2 outputs the high level signal. In this way, when the set terminal of the first nand gate NA1 and the reset terminal of the second nand gate NA2 have no change, i.e., the first control terminal Si continuously receives the high signal and the second control terminal Ri continuously receives the low signal, the first output terminal n1 of the first nand gate NA1 continuously outputs the low signal, and the second output terminal p1 of the second nand gate NA2 continuously outputs the high signal. In the subsequent phase of the second operating phase T2, the second control terminal Ri starts to transmit the high signal, so that the seventh transistor T17 is turned on, but does not influence the fifth transistor T15 to be turned on continuously and the second output terminal p1 of the second nand gate NA2 to output the high signal continuously, nor the third transistor T13 and the fourth transistor T14 to be turned on continuously and the first output terminal n1 of the first nand gate NA1 to output the low signal continuously. That is, the state in which the first output terminal n1 of the first nand gate NA1 continues to output the low signal and the second output terminal p1 of the second nand gate NA2 continues to output the high signal in the latch LT is latched without being affected by the signal received by the second control terminal Ri.

As shown in fig. 7 and 8, the first output unit K1 has a transmission gate structure, and the second output unit K2 also has a transmission gate structure. An input terminal of the transfer gate in the first output unit K1 serves as an input terminal of the first output unit K1 and is electrically connected to the first signal line X1i, and an output terminal of the transfer gate in the first output unit K1 serves as an output terminal of the first output unit K1 and is electrically connected to the first amplification input terminal p2 of the first amplifier B1. An input terminal of the transfer gate in the second output unit K2 serves as an input terminal of the second output unit K2 and is electrically connected to the second signal line X2i, and an output terminal of the transfer gate in the second output unit K2 serves as an output terminal of the second output unit K2 and is electrically connected to the second amplification input terminal n2 of the second amplifier B2. In one implementation of the present application, the first control output terminal P3 of the control unit CT is electrically connected to gates of transistors of the same channel type in the transmission gate of the first output unit K1 and in the transmission gate of the second output unit K2, for example, the first control output terminal P3 of the control unit CT is electrically connected to a gate of a P-type transistor of the transmission gate of the first output unit K1 and to a gate of a P-type transistor of the transmission gate of the second output unit K2; the second control output terminal N3 of the control unit CT is electrically connected to the gates of the transistors of the same type in the transfer gates of the first output unit K1 and the second output unit K2, for example, the first control output terminal p3 of the control unit CT is electrically connected to the gate of the N-type transistor of the transfer gate of the first output unit K1 and to the gate of the N-type transistor of the transfer gate of the second output unit K2. The first output unit K1 and the second output unit K2 can be turned on or off simultaneously, so as to improve the efficiency of signal transmission and reduce the risk of leakage current.

As shown in fig. 7 and 8, the first turn-off unit G1 is a first turn-off transistor T21, and the second turn-off unit G2 is a second turn-off transistor T22. The gate of the first turn-off transistor T21 is electrically connected to the first control output terminal p3 of the control unit CT as the control terminal of the first turn-off unit G1, and the gate of the second turn-off transistor T22 is electrically connected to the second control output terminal n3 of the control unit CT as the control terminal of the second turn-off unit G2. A source of the first turn-off transistor T21 is an input terminal of the first turn-off unit G1 and is electrically connected to the first potential signal line V1, and a drain of the first turn-off transistor T21 is an output terminal of the first turn-off unit G1 and is electrically connected to the first amplification input terminal p2 of the first amplifier B1; a source of the second turn-off transistor T2 serves as an input terminal of the second turn-off unit G2 and is electrically connected to the second potential signal line V2, and a drain of the second turn-off transistor T2 serves as an output terminal of the second turn-off unit G2 and is electrically connected to the second amplification input terminal n2 of the second amplifier B2.

The type of the first turn-off transistor T21 is different from that of a transistor electrically connected to the first control output terminal p3 in the first output unit K1, and the type of the second turn-off transistor T22 is different from that of a transistor electrically connected to the second control output terminal n3 in the second output unit K2. For example, the first turn-off transistor T21 is a P-type transistor, and the transistor of the first output unit K1 electrically connected to the first control output terminal P3 is an N-type transistor; the second turn-off transistor T22 is an N-type transistor, and the transistor electrically connected to the second control output terminal N3 in the second output unit K2 is a P-type transistor.

In one embodiment of the present application, as shown in fig. 5 and 7, the input terminal of the third amplifier B3 and the input terminal of the fourth amplifier B4 are electrically connected to the same output terminal of the control unit CT, for example, both are electrically connected to the second output terminal p1 of the control unit CT. The operation of the shift register shown in fig. 7 will be described with reference to fig. 9.

When the first control terminal Si receives a low signal and the second control terminal Ri receives a high signal in the beginning of the first operation phase t1, the first output terminal n1 of the first nand gate NA1 outputs a high signal, and the second output terminal p1 of the second nand gate NA2 outputs a low signal. In the subsequent stage of the first operation period t1, after the first control terminal Si starts to receive the high signal, the first control terminal Ri still receives the high signal, the first output terminal n1 of the first nand gate NA1 still outputs the high signal, and the second output terminal p1 of the second nand gate NA2 still outputs the low signal. That is, in the first operation phase t1, the first output n1 of the first nand gate NA1 in the latch LT continuously outputs a high signal, and the second output p1 of the second nand gate NA2 continuously outputs a low signal. The third amplifier B3 includes an odd number of inverters, so that the low level signal output from the second output terminal p1 of the latch LT passes through the third amplifier B3 and then the first control output terminal p3 of the control unit CT outputs a high level signal; the fourth amplifier B4 includes an even number of inverters, so that the low level signal outputted from the second output terminal p1 of the latch LT passes through the fourth amplifier B4, and then the low level signal is outputted from the second control output terminal n3 of the control unit CT. In the first operation phase t1, the first control output terminal p3 of the control unit CT continuously outputs the high level signal to continuously turn on the first output unit K1 and the second output unit K2, and the second control output terminal n3 of the control unit CT outputs the low level signal to continuously turn on the first output unit K1 and the second output unit K2.

In the low enable signal output stage of the first operating stage t1, the first signal line X1i continuously outputs a low level signal, and the output end of the first output unit K1 continuously outputs a low level signal; in the high-enable signal output phase of the first operation phase t1, the second signal line X2i continuously outputs the high-level signal, and the output terminal of the second output unit K2 continuously outputs the high-level signal. The first amplifier B1 and the second amplifier B2 both include an even number of inverters, so that the low level signal continuously received by the first amplification input terminal p2 of the first amplifier B1 passes through the first amplifier B1 and then outputs the low level signal from the low enable signal output terminal GP, and the high level signal continuously received by the second amplification input terminal n2 of the second amplifier B2 passes through the second amplifier B2 and then outputs the high level signal from the high enable signal output terminal GN.

In the beginning of the second operation period t2, the first control terminal Si still receives the high signal, and the second control terminal Ri receives the low signal, the first output terminal n1 of the first nand gate NA1 outputs the low signal, and the second output terminal p1 of the second nand gate NA2 outputs the high signal. In the subsequent phase of the second operation phase t2, after the signal of the second control terminal Ri starts to change, the first output terminal n1 of the first nand gate NA1 still outputs a low signal, and the second output terminal p1 of the second nand gate NA2 still outputs a high signal. That is, in the second operation phase t2, the first output n1 of the first nand gate NA1 in the latch LT continuously outputs a low signal, and the second output p1 of the second nand gate NA2 continuously outputs a high signal. The high level signal outputted from the second output terminal p1 of the latch LT passes through the third amplifier B3 and then is outputted as the low level signal from the first control output terminal p3 of the control unit CT, and the high level signal outputted from the second output terminal p1 of the latch LT passes through the fourth amplifier B4 and then is outputted as the high level signal from the second control output terminal n3 of the control unit CT. Then, in the first operation phase t1, the first control output terminal p3 of the control unit CT continuously outputs the low level signal to make the first turn-off unit G1 continuously turned on, and the second control output terminal n3 of the control unit CT continuously outputs the high level signal to make the second turn-off unit G2 continuously turned on.

In the second operation phase t2, the first turn-off unit G1 is continuously turned on, so that the first amplification input terminal p2 of the first amplifier B1 continuously receives the high-level signal transmitted by the first potential signal line V1, and the low-level signal is output from the low-enable signal output terminal GP; the second turn-off unit G2 is continuously turned on, so that the second amplification input terminal n2 of the second amplifier B2 continuously receives the low-level signal transmitted from the second potential signal line V2, and the low-level signal is output from the high-enable signal output terminal GN.

In another embodiment of the present application, as shown in fig. 6 and 8, an input terminal of the third amplifier B3 and an input terminal of the fourth amplifier B4 are electrically connected to two output terminals of the control unit CT, for example, an input terminal of the third amplifier B3 is electrically connected to the first output terminal n1 of the control unit CT, and an input terminal of the fourth amplifier B4 is electrically connected to the second output terminal p1 of the control unit CT. The operation of the shift register shown in fig. 8 is substantially the same as that of the shift register shown in fig. 7, and the difference between the operation of the shift register shown in fig. 8 and that of the shift register shown in fig. 7 will be described with reference to fig. 9.

The shift register shown in fig. 8 is also different from the shift register shown in fig. 7 in that the third amplifier B3 and the fourth amplifier B4 each include an even number of inverters or an odd number of inverters, and as shown in fig. 8, the third amplifier B3 and the fourth amplifier B4 each include an even number of inverters.

Then, in the first operation phase t1, the high level signal outputted from the first output terminal n1 of the latch LT passes through the third amplifier B3 and then is outputted from the first control output terminal p3 of the control unit CT; the low level signal outputted from the second output terminal p1 of the latch LT passes through the fourth amplifier B4, and then the second control output terminal n3 of the control unit CT outputs a low level signal.

Then in the second operating phase t2, the low level signal outputted from the first output terminal n1 of the latch LT is outputted by the first control output terminal p3 of the control unit CT after passing through the third amplifier B3, and the high level signal outputted from the second output terminal p1 of the latch LT is outputted by the second control output terminal n3 of the control unit CT after passing through the fourth amplifier B4.

In one embodiment of the present application, as shown in fig. 7, when the input terminal of the third amplifier B3 and the input terminal of the fourth amplifier B4 are electrically connected to the same output terminal of the control unit CT, the third amplifier B3 and the fourth amplifier B4 may share a partial inverter. As shown in fig. 7, when the number of inverters in the fourth amplifier B4 is greater than that of inverters in the third amplifier B3, the inverters in the third amplifier B3 may be an odd number of inverters in the fourth amplifier B4 and the odd number of inverters are inverters directly electrically connected to the latch LT and inverters sequentially connected in series. Further, when the number of inverters in the fourth amplifier B4 is less than the number of inverters in the third amplifier B3, the inverters in the fourth amplifier B4 may be an even number of inverters in the third amplifier B3 and the even number of inverters are inverters directly electrically connected to the latch LT and inverters sequentially connected in series.

In another embodiment of the present application, as shown in fig. 8, when the input terminal of the third amplifier B3 and the input terminal of the fourth amplifier B4 are electrically connected to the two output terminals of the control unit CT, the third amplifier B3 and the fourth amplifier B4 each include a corresponding number of inverters, i.e., the inverters in the third amplifier B3 and the fourth amplifier B4 are not shared.

Fig. 10 is an equivalent circuit diagram of a shift register according to an embodiment of the present application, and fig. 11 is a timing diagram of the shift register shown in fig. 10.

As shown in fig. 7, 8 and 10, the first amplifier B1, the second amplifier B2, the third amplifier B3 and the fourth amplifier B4 are each composed of inverters connected in series. The number of the inverters connected in series in the first amplifier B1 is determined by the signal at the first amplification input terminal p2 of the first amplifier B1 and the signal that needs to be output at the low level enable signal output terminal GP.

As shown in fig. 7 and 8, when the signal at the first amplification input end p2 of the first amplifier B1 and the signal that needs to be output by the low level enable signal output end GP are both signals with the same phase, the number of the inverters connected in series in the first amplifier B1 is even. When the signal at the second amplification input terminal n2 of the second amplifier B2 and the signal that needs to be output by the high-level enable signal output terminal GN are both signals with the same phase, the number of the inverters connected in series in the second amplifier B2 is even.

Fig. 10 differs from fig. 8 in that the second output p1 of the second nand gate NA2 is electrically connected to the input of the third amplifier B3, and the first output n1 of the first nand gate NA1 is electrically connected to the input of the fourth amplifier B4; the first off transistor T21 is an N-type transistor and is electrically connected to the second potential signal line V2, and the second off transistor T22 is a P-type transistor and is electrically connected to the first potential signal line V1. As shown in fig. 11, in the high enable signal output phase of the first operation phase t1, the second signal line X2 outputs a low enable signal, and the high enable signal output terminal GN needs to output a high enable signal; in the second operation period t2, the second control output terminal n3 outputs a low level signal to control the second turn-off unit G2 to turn on, and a low level signal should be output from the high enable signal output terminal GN after the high level signal on the first potential signal line V1 passes through the second amplifier B2; the second amplifier B2 includes an odd number of inverters. In the low enable signal output phase t1p of the first operating phase t1, the first signal line X1i outputs a high enable signal, and the low enable signal output end GP needs to output a low enable signal; in the second operation period t2, the first control output terminal p3 outputs a high level signal to control the first turn-off unit G1 to turn on, and the low level signal on the second potential signal line V2 should output a high level signal from the low enable signal output terminal GP after passing through the second amplifier B2; the first amplifier B1 page includes an odd number of inverters. That is, when the signal at the first amplification input terminal p2 of the first amplifier B1 and the signal that needs to be output by the low level enable signal output terminal GP are inverted signals, the number of the inverters connected in series in the first amplifier B1 is an odd number; when the signal at the second amplification input terminal n2 of the second amplifier B2 and the signal that needs to be output by the high-level enable signal output terminal GN are inverted signals, the number of inverters connected in series in the second amplifier B2 is an odd number.

Based on the same reason, the number of the inverters connected in series in the third amplifier B3 is determined by the signal at the input terminal of the third amplifier B3 and the signal required to be output by the output terminal of the third amplifier B3, i.e. the signal required to be output by the first control output terminal p3 of the control unit CT; the number of inverters connected in series in the fourth amplifier B4 is determined by the signal at the input terminal of the fourth amplifier B4 and the signal required to be output by the output terminal of the fourth amplifier B4, i.e., the signal required to be output by the second control output terminal n3 of the control unit CT.

Fig. 12 is a schematic diagram of another shift register according to an embodiment of the present application, in an embodiment of the present application, as shown in fig. 12, the control unit CT according to the embodiment of the present application may further include an initialization unit RT, and in an initialization stage t0 before the first operating stage t1, after a signal output by the initialization unit RT is output through the first control output terminal p3 of the control unit CT, the first turn-off unit G1 is turned on, and the low enable signal output terminal GP outputs a high level signal; the signal output by the initialization unit RT is output through the second control output terminal n3 of the control unit CT, so that the second turn-off unit G2 is turned on, and the high enable signal output terminal GN outputs a low level signal.

Fig. 13 is an equivalent circuit diagram of a shift register corresponding to fig. 12, and fig. 14 is a timing chart of the shift register corresponding to fig. 13. As shown in fig. 12 and 13, the initialization unit RT is disposed between the third and fourth amplifiers B3 and B4 and the latch LT, that is, the output terminal of the initialization unit RT is electrically connected to the input terminals of the third and fourth amplifiers B3 and B4, respectively.

In an embodiment of the present application, as shown in fig. 13, when the input terminal of the third amplifier B3 and the input terminal of the fourth amplifier B4 receive signals from the same output terminal of the control unit CT during the first operation phase t1, the shift register may include an initialization unit RT, and the output terminal of the initialization unit RT is electrically connected to the input terminal of the third amplifier B3 and the input terminal of the fourth amplifier B4.

In another embodiment of the present application, when the input terminal of the third amplifier B3 and the input terminal of the fourth amplifier B4 receive signals from two different output terminals of the control unit CT during the first operation phase t1, the shift register may include two initialization units RT. And of the two initialization units RT, an output terminal of one initialization unit RT may be electrically connected to an input terminal of the third amplifier B3, and an output terminal of the other initialization unit RT may be electrically connected to an input terminal of the fourth amplifier B4.

The operation of the initialization stage t0 is described below by taking the example that the input terminal of the third amplifier B3 and the input terminal of the fourth amplifier B4 are shared and the shift register includes an initialization unit RT.

As shown in fig. 13, the initialization unit RT may be a nand gate circuit, and in particular, the initialization unit RT may include a ninth transistor T31, a tenth transistor T32, an eleventh transistor T33, and a twelfth transistor T34. The ninth transistor T31 and the tenth transistor T32 are both P-type transistors, the source of the ninth transistor T31 and the source of the tenth transistor T32 are electrically connected to the initialization signal line RL, and the drain of the ninth transistor T31 and the drain of the tenth transistor T32 are electrically connected to the output terminal of the nand gate corresponding to the initialization unit RT. The eleventh transistor T33 and the twelfth transistor T34 are both N-type transistors, a source of the eleventh transistor T33 is electrically connected to a drain of the twelfth transistor T34, and a drain of the eleventh transistor T33 is electrically connected to an output terminal of the nand gate corresponding to the initialization unit RT; the source of the twelfth transistor T34 is electrically connected to a low-level signal line, for example, the second potential signal line V2 and the second potential signal line V2 transmits a low-level signal. The gate of the ninth transistor T31 and the gate of the twelfth transistor T34 are electrically connected to one control end of the nand gate corresponding to the initialization unit RT; the gates of the tenth transistor T32 and the eleventh transistor T33 are electrically connected to the other control terminal of the nand gate corresponding to the initialization unit RT and to the initialization control line RKi.

Referring to fig. 13 and 14, in the initialization stage t0, the initialization control line RKi transmits a low level signal, the initialization signal line RL transmits a high level signal, and the output end of the initialization unit RT outputs a high level signal. After the high-level signal output by the output end of the initialization unit RT passes through the third amplifier B3, the first control output end p3 of the control unit CT outputs a low-level signal to control the first turn-off unit G1 to turn on, and the low-enable signal output end GP outputs a high-level signal; after the high level signal output from the output terminal of the initialization unit RT passes through the fourth amplifier B4, the second control output terminal n3 of the control unit CT outputs a high level signal to control the second turn-off unit G2 to turn on, and the high enable signal output terminal GN outputs a low level signal.

Note that, when the initialization signal line RL transmits a high-level signal in the initialization period t0, the initialization signal line RL may be multiplexed with the first potential signal line V1.

When the initialization unit RT is a nand gate structure, one control terminal of the nand gate structure is electrically connected to the initialization control line RKi, and a signal received by the other control terminal may be provided by the latch LT. In the shift register shown in fig. 13, the initialization unit RT needs to turn on the P-type transistor in the initialization stage t0, so that both control terminals of the nand gate circuit corresponding to the initialization unit RT can receive the low level signal, one of the control terminals can receive the low level signal transmitted by the initialization control line RKi, and the low level signal received by the other control terminal can be provided by the latch LT. Specifically, a first inverter IT is disposed between the second output terminal p1 of the latch LT and a control terminal of the nand gate corresponding to the initialization unit RT, and the second output terminal p1 of the latch LT outputs a high-level signal in the initialization period t0, and the high-level signal is changed into a low-level signal after passing through the first inverter IT and is transmitted to a control terminal of the nand gate corresponding to the initialization unit RT.

Referring to fig. 13 and 14, in the first operation phase t1, the low level signal output from the second output terminal p1 of the latch LT changes to the high level signal after passing through the first inverter IT, and the initialization control line RKi transmits the high level signal, so that the nand gate corresponding to the initialization unit RT outputs the low level signal. After passing through the third amplifier B3, the first control output terminal p3 of the control unit CT outputs a high level signal, and after passing through the fourth amplifier B4, the second control output terminal n3 of the control unit CT outputs a low level signal, so that the first output unit K1 and the second output unit K2 are turned on, the low enable signal output terminal GP outputs a low level signal at the low enable signal output stage t1p, and the high enable signal output terminal GN outputs a high level signal at the high enable signal output stage.

Referring to fig. 13 and 14, in the second operation phase t2, the high level signal output from the second output terminal p1 of the latch LT changes to a low level signal after passing through the first inverter IT, and the nand gate corresponding to the initialization unit RT outputs a high level signal. After passing through the third amplifier B3, the first control output terminal p3 of the control unit CT outputs a low level signal, and after passing through the fourth amplifier B4, the second control output terminal n3 of the control unit CT outputs a high level signal, so that the first turn-off unit G1 and the second turn-off unit G2 are turned on, the low-enable signal output terminal GP outputs a high level signal, and the high-enable signal output terminal GN outputs a low level signal. As shown in fig. 14, the initialization control line RKi may transmit a high level signal; furthermore, the initialization control line RKi may also transmit a low level signal.

As can be seen from the timing diagrams of fig. 9 and 14, the signal received by the second control terminal Ri is the same as the signal received by the second signal line X2i, and the second control terminal Ri in fig. 8 and 13 can be electrically connected to the second signal line X2i and the same signal terminal. As can be seen from the timing diagram of fig. 11, if the signal received by the second control terminal Ri and the signal received by the second signal line X2i are complementary signals, an inverter may be connected to the second control terminal Ri in fig. 10, and the output terminal of the inverter is electrically connected to the second control terminal Ri, and the input terminal is electrically connected to the second signal line X2i and the same signal terminal.

Fig. 15 is a partial equivalent circuit diagram of a gate driving circuit according to an embodiment of the present application, fig. 16 is a partial equivalent circuit diagram of another gate driving circuit according to the embodiment of the present application, and fig. 17 is a partial equivalent circuit diagram of another gate driving circuit according to the embodiment of the present application.

As shown in fig. 15 to 17, in the gate driving circuit provided in the embodiment of the present application, adjacent shift registers are cascaded, that is, one output terminal of a shift register in a previous stage is electrically connected to one control terminal of a shift register in a next stage. As shown in fig. 15 and 17, the low enable signal output terminal of the previous stage shift register is electrically connected to the first control terminal of the next stage shift register. For example, the low enable signal output terminal GPi-1 of the i-1 th stage shift register SRi-1 is electrically connected to the first control terminal Si of the i-th stage shift register SRi, and the low enable signal output terminal GPi of the i-th stage shift register SRi is electrically connected to the first control terminal Si +1 of the i +1 th stage shift register SRi + 1.

As shown in fig. 15-17, the non-display area BB of the display panel according to the embodiment of the present invention further includes three clock signal lines, which are the first clock signal line L1, the second clock signal line L2, and the third clock signal line L3. In the gate driving circuit provided in the embodiment of the present application, each sequentially cascaded three shift registers is a shift register group, and in the three shift registers in one shift register group, the second control end of each shift register is electrically connected to a different clock signal line, the first signal line X1i of each shift register is electrically connected to a different clock signal line, and the second control end and the second signal line of the same shift register are electrically connected to a different clock signal line. In addition, a second signal line in the same shift register is electrically connected to a second control terminal. As shown in fig. 15-17, in the i-1 th stage of the shift register SRi-1, the second signal line X2i-1 is electrically connected to the second control terminal Ri-1, the second control terminal Ri-1 is electrically connected to the first clock signal line L1, and the first signal line X1i-1 is electrically connected to the third clock signal line L3; in the ith stage of shift register SRi, the second signal line X2i is electrically connected to the second control terminal Ri, the second control terminal Ri is electrically connected to the second clock signal line L2, and the first signal line X1i is electrically connected to the first clock signal line L1; in the i +1 th stage shift register SRi +1, the second signal line X2i +1 is electrically connected to the second control terminal Ri +1, the second control terminal Ri +1 is electrically connected to the third clock signal line L3, and the first signal line X1i +1 is electrically connected to the second clock signal line L2.

The gate driver circuit shown in fig. 15 is formed by cascading the shift registers shown in fig. 13, and the gate driver circuit shown in fig. 16 is formed by cascading the shift registers shown in fig. 8.

Fig. 18 is a timing chart corresponding to the gate driving circuit shown in fig. 15 and 16, and it can be seen that the first clock signal line L1, the second clock signal line L2, and the third clock signal line L3 output pulse signals, and the timings of the three start outputting high level signals are sequentially performed, and the timings of the three start outputting low level signals are also sequentially performed; correspondingly, the time when the high enable signal output terminal of the shift register of the adjacent stage outputs the high level signal is sequentially performed, and the time when the low enable signal output terminal of the shift register of the adjacent stage outputs the low level signal is sequentially performed. Referring to the timing diagrams shown in FIG. 9, FIG. 14 and FIG. 18, the first clock line L1 provides signals to the second control terminal Ri-1 and the second signal line X2i-1 of the i-1 th stage of shift register SRi-1 and provides signals to the first signal line X1i of the i-th stage of shift register SRi, the second clock line L2 provides signals to the second control terminal Ri and the second signal line X2i of the i-th stage of shift register SRi and provides signals to the first signal line X1i +1 of the i +1 th stage of shift register SRi +1, and the third clock line L3 provides signals to the second control terminal Ri +1 and the second signal line X2i +1 of the i +1 th stage of shift register SRi +1 and provides signals to the first signal line X1i-1 of the i-1 th stage of shift register SRi-1.

The gate driver circuit shown in fig. 17 is formed by cascading the shift registers shown in fig. 10.

Fig. 19 is a timing chart corresponding to the gate driving circuit shown in fig. 17, in which the first clock signal line L1, the second clock signal line L2, and the third clock signal line L3 output pulse signals, and the three start outputting high-level signals in time sequence, and the start outputting low-level signals in time sequence; correspondingly, the time when the high enable signal output terminal of the shift register of the adjacent stage outputs the high level signal is sequentially performed, and the time when the low enable signal output terminal of the shift register of the adjacent stage outputs the low level signal is sequentially performed. Referring to the timing diagrams shown in FIG. 11 and FIG. 19, the first clock line L1 provides signals to the second control terminal Ri-1 and the second signal line X2i-1 of the i-1 th stage of the shift register SRi-1 through an inverter and the first clock line L1 provides signals to the first signal line X1i of the i-th stage of the shift register SRi directly, the second clock line L2 provides signals to the second control terminal Ri of the i-th stage of the shift register SRi and the second signal line X2i through an inverter and the second clock line L2 provides signals to the first signal line X1i +1 of the i +1 th stage of the shift register SRi +1 directly, the third clock signal line L3 supplies signals to the second control terminal Ri +1 of the i +1 th stage shift register SRi +1 and the second signal line X2i +1 through an inverter and the third clock signal line L3 directly supplies signals to the first signal line X1i-1 of the i-1 th stage shift register SRi-1.

Fig. 20 is a schematic view of an electronic device provided in an embodiment of the present application, and as shown in fig. 20, the electronic device includes a display panel provided in any embodiment of the present application. The specific structure of the display panel has been described in detail in the above embodiments, and is not described herein again. Of course, the electronic device shown in fig. 20 is only a schematic illustration, and may be any electronic device with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic book, a television, a smart watch, and the like. In addition, the electronic device provided by the embodiment of the application also comprises a display area AA and a non-display area BB corresponding to the display area AA and the non-display area BB of the display panel.

The above description is only for the specific embodiments of the present application, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered by the protection scope of the present application. The protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A gate driving circuit is characterized in that the gate driving circuit is used for providing scanning signals for a pixel driving circuit;

the pixel driving circuit comprises at least one N-type transistor and at least one P-type transistor, wherein the grid electrode of the at least one N-type transistor is electrically connected with a first type of scanning line, and the grid electrode of the at least one P-type transistor is electrically connected with a second type of scanning line;

the grid driving circuit comprises N stages of cascaded shift registers, wherein N is a positive integer greater than or equal to 3; the shift register includes:

a high enable signal output terminal electrically connected to the first type of scanning signal line;

a low enable signal output terminal electrically connected to the second type scan line;

the time of the high-level signal output end outputting the high-level signal covers the time of the low-level signal output end outputting the low-level signal, and the time of the low-level signal output end outputting the low-level signal is less than the time of the high-level signal output end outputting the high-level signal.

2. The gate driver circuit according to claim 1, wherein the shift register comprises:

the output end of the first amplifier is electrically connected with the low enable signal output end;

a first output unit, an input end of which is electrically connected with the first signal line, and an output end of which is electrically connected with the input end of the first amplifier; when the first output unit is conducted and the signal on the first signal line passes through the first output unit and the first amplifier, the low-level signal is output by the low-enable signal output end;

the input end of the first turn-off unit is electrically connected with the first potential signal wire, and the output end of the first turn-off unit is electrically connected with the input end of the first amplifier; when the first turn-off unit is turned on and a signal on the first potential signal line passes through the first turn-off unit and the first amplifier, the low enable signal output end outputs a high level signal;

the output end of the second amplifier is electrically connected with the high enable signal output end;

the input end of the second output unit is electrically connected with the second signal line, and the output end of the second output unit is electrically connected with the input end of the second amplifier; when the second output unit is conducted and the signal on the second signal line passes through the second output unit and the second amplifier, the high-level signal is output by the high-enable signal output end;

the input end of the second turn-off unit is electrically connected with the second potential signal line, and the output end of the second turn-off unit is electrically connected with the input end of the second amplifier; and when the second turn-off unit is turned on and the signal on the second potential signal line passes through the second turn-off unit and the second amplifier, the high enable signal output end outputs a low level signal.

3. The gate driving circuit according to claim 2, wherein the shift register further comprises a control unit, the control unit comprising:

the first control output end is respectively and electrically connected with the control end of the first output unit and the control end of the first turn-off unit and is used for controlling the on and off of the first output unit and the first turn-off unit, and the on time of the first output unit is different from that of the first turn-off unit;

and the second control output end is respectively and electrically connected with the control end of the second output unit and the control end of the second turn-off unit and is used for controlling the on and off of the second output unit and the second turn-off unit, and the on time of the second output unit is different from that of the second turn-off unit.

4. A gate drive circuit as claimed in claim 3,

the first output unit is of a transmission gate structure, an input end of a transmission gate corresponding to the first output unit is used as an input end of the first output unit, and an output end of the transmission gate corresponding to the first output unit is used as an output end of the first output unit;

the second output unit is of a transmission gate structure, an input end of a transmission gate corresponding to the second output unit is used as an input end of the second output unit, and an output end of the transmission gate corresponding to the second output unit is used as an output end of the second output unit.

5. A gate drive circuit as claimed in claim 4,

the first control output end is electrically connected with the gates of the transistors with the same channel type in the transmission gate structure corresponding to the first output unit and the transmission gate structure corresponding to the second output unit;

the second control output end is electrically connected with the grid electrode of the transistor with the other channel type in the transmission gate structure corresponding to the first output unit and the transmission gate structure corresponding to the second output unit;

the first output unit and the second output unit are simultaneously turned on or off.

6. A gate drive circuit as claimed in claim 5,

the first turn-off unit is of a transistor structure, a gate of a transistor corresponding to the first turn-off unit is used as a control end of the first turn-off unit, a source of the transistor corresponding to the first turn-off unit is used as an input end of the first turn-off unit, and a drain of the transistor corresponding to the first turn-off unit is used as an output end of the first turn-off unit;

the second turn-off unit is of a transistor structure, a gate of a transistor corresponding to the second turn-off unit is used as a control end of the second turn-off unit, a source of the transistor corresponding to the second turn-off unit is used as an input end of the second turn-off unit, and a drain of the transistor corresponding to the second turn-off unit is used as an output end of the second turn-off unit.

7. A gate drive circuit as claimed in claim 6,

the channel type of the transistor structure corresponding to the first turn-off unit is different from the channel type of a transistor electrically connected with the first control output end in the transmission gate structure corresponding to the first output unit;

the channel type of the transistor structure corresponding to the second turn-off unit is different from the channel type of a transistor electrically connected with the second control output end in the transmission gate structure corresponding to the second output unit.

8. A gate driving circuit as claimed in claim 3, wherein the control unit comprises a latch, a third amplifier and a fourth amplifier, an output terminal of the latch is electrically connected to an input terminal of the third amplifier and an input terminal of the fourth amplifier, respectively, an output terminal of the third amplifier is electrically connected to the first control output terminal of the control unit, and an output terminal of the fourth amplifier is electrically connected to the second control output terminal of the control unit.

9. A gate drive circuit as claimed in claim 8, wherein the input of the third amplifier and the input of the fourth amplifier are electrically connected to the same output of the latch.

10. A gate drive circuit as claimed in claim 9, wherein the third amplifier and the fourth amplifier are each formed by a plurality of inverters, at least some of the inverters in the third amplifier being common to at least some of the inverters in the fourth amplifier;

when the number of the inverters in the third amplifier is even, the number of the inverters in the fourth amplifier is odd; and when the number of the inverters in the third amplifier is odd, the number of the inverters in the fourth amplifier is even.

11. A gate drive circuit as claimed in claim 8, wherein the input terminals of the third and fourth amplifiers are electrically connected to the two output terminals of the latch, respectively.

12. The gate driving circuit according to claim 3, wherein the control unit further comprises a latch, an initialization unit, a third amplifier, and a fourth amplifier;

the initialization unit is arranged between the latch and the third amplifier and between the latch and the fourth amplifier, the output end of the initialization unit is electrically connected with the input end of the third amplifier and the input end of the fourth amplifier respectively, the output end of the third amplifier is electrically connected with the first control output end of the control unit, and the output end of the fourth amplifier is electrically connected with the second control output end of the control unit.

13. A gate drive circuit as claimed in claim 12, wherein the third and fourth amplifiers are each formed from a plurality of inverters, at least some of the inverters in the third amplifier being common with at least some of the inverters in the fourth amplifier;

14. The gate driving circuit of claim 3, wherein the control unit further comprises a latch, two initialization units, a third amplifier and a fourth amplifier;

the initialization units are arranged between the latch and the third amplifier and the fourth amplifier, the output end of one initialization unit is electrically connected with the input end of the third amplifier, and the output end of the other initialization unit is electrically connected with the input end of the fourth amplifier.

15. The gate driving circuit according to claim 12 or 14, wherein the initialization unit is a nand gate, one control terminal of the nand gate structure corresponding to the initialization unit is electrically connected to an initialization control line, and a signal of the other control terminal of the nand gate structure corresponding to the initialization unit is provided by the latch.

16. The gate driving circuit according to claim 2, wherein in the N cascaded shift registers, the low enable signal output terminal or the high enable signal output terminal of the previous shift register is electrically connected to the first control terminal of the next shift register;

the N-stage cascaded shift register is electrically connected with three clock signal lines;

wherein, each three shift registers which are cascaded in sequence are a shift register group; in one shift register group, the second control end of each shift register is electrically connected to a different clock signal line, the second signal line in the same shift register is electrically connected to the second control end, the first signal line of each shift register is electrically connected to a different clock signal line, and the second control end and the second signal line of the same shift register are electrically connected to a different clock signal line.

17. The gate driving circuit according to claim 16, wherein the three clock signal lines start outputting the high level signal sequentially and output the low level signal sequentially.

18. A display panel characterized by comprising a display area and a non-display area surrounding the display area;

the non-display region includes a gate driving circuit according to any one of claims 1 to 17;

the display area is provided with a pixel driving circuit and a light-emitting device, the pixel driving circuit can control the light-emitting device to emit light, and the grid driving circuit provides scanning signals for the pixel driving circuit.

19. An electronic device characterized by comprising the display panel according to claim 18.