CN114442860A

CN114442860A - Display device

Info

Publication number: CN114442860A
Application number: CN202210179551.3A
Authority: CN
Inventors: 王蓉; 胡明; 仝可蒙; 董向丹; 李宇婧
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2022-02-25
Filing date: 2022-02-25
Publication date: 2022-05-06

Abstract

The embodiment of the application provides a display device, which comprises a display panel and a touch panel, wherein the touch panel is of an organic flexible multilayer covering surface type structure; display panel includes display area and non-display area, the non-display area includes first stitch district and second stitch district and stitch joining region, be provided with the connection in the stitch joining region first stitch district with the connection of stitch is walked the line in the second stitch district, just it is covered by inorganic insulating layer to connect to walk the line. In the display device that this application embodiment provided, connect and walk the line and be covered by inorganic insulating layer, consequently remove the process at the etching of organic FMLOC technology section, even there is metal to remain in the gap of connecting the line, can not lead to connecting the short of walking the line yet. In addition, the inorganic insulating layer has good water and oxygen barrier property, and can ensure the reliability of the connecting wiring in a high-temperature and high-humidity environment.

Description

Display device

Technical Field

The embodiment of the application relates to the technical field of display and touch equipment, in particular to a display device.

Background

The Flexible Multi-Layer cover surface type (FMLOC for short) refers to a touch panel with mutually-compatible touch devices manufactured outside a display panel film packaging Layer, and the FMLOC can integrate a display structure and a touch structure together, has the advantages of being light, thin, foldable and the like, and can meet the product requirements of Flexible folding, narrow frames and the like. The organic FMLOC is a type of FMLOC, and includes a first organic layer, a first touch layer, a second organic layer, a second touch layer, and an organic layer, which are stacked.

The display panel comprises a display area and a non-display area, the non-display area comprises a first stitch area, a second stitch area and a connecting area located between the first stitch area and the second stitch area, and connecting lines of stitches in the first stitch area and the second stitch area are arranged in the connecting area.

In the related art, the connection trace is located on a metal layer covered by an organic layer. Because the organic layer in the organic FMLOC and the organic layer in the display panel have poor adhesion, the organic layer in the FMLOC process stage and the organic layer in the display panel may have a peeling problem during the organic FMLOC process, and thus the organic layer in the organic FMLOC needs to be removed; however, in the removing process, the connection wires are affected, and the reliability is damaged.

Disclosure of Invention

In view of the above, an object of the embodiments of the present application is to provide a display device.

The display device comprises a display panel and a touch panel, wherein the touch panel is of an organic flexible multilayer covering surface type structure;

display panel includes display area and non-display area, the non-display area includes first stitch district and second stitch district and stitch joining region, be provided with the connection in the stitch joining region first stitch district with the connection of stitch is walked the line in the second stitch district, just it is covered by inorganic insulating layer to connect to walk the line.

In the display device that this application embodiment provided, connect and walk the line and be covered by inorganic insulating layer, consequently get rid of the process at the sculpture of organic FMLOC technology section, even there is metal to remain in the gap of connecting the line, can not lead to connecting the short of walking the line yet. In addition, the inorganic insulating layer has good water and oxygen barrier property, and can ensure the reliability of the connecting wiring in a high-temperature and high-humidity environment.

In one possible implementation, the touch panel includes a first organic layer, a first touch layer, a second organic layer, a second touch layer and a third organic layer, which are stacked in a direction away from the display panel;

the first organic layer, the first touch layer, the second organic layer, the second touch layer and the third organic layer are removed from the stitch connecting area.

In one possible embodiment, the first organic layer, the second organic layer and the third organic layer are all made of negative photosensitive glue.

In one possible implementation, one of the first touch layer and the second touch layer is provided with a plurality of connecting bridges, and the other is provided with a plurality of first touch electrodes arranged along a first direction and a plurality of second touch electrodes arranged at intervals along a second direction perpendicular to the first direction;

two adjacent first touch electrodes along the first direction are integrally connected, and two adjacent second touch electrodes along the second direction are connected with the connecting bridge through via holes formed in the second organic layer.

In one possible embodiment, the first touch layer and the second touch layer include at least one of indium tin oxide, a metal mesh, and nano silver wires.

In one possible embodiment, the display device includes a control chip and a flexible circuit board, the first stitch area is a binding area bound to the control chip, and the second stitch area is a binding area bound to the flexible circuit board.

In one possible embodiment, the inorganic insulating layer has a single-layer or multi-layer structure including at least one of silicon oxide, silicon nitride, and silicon oxynitride.

In one possible implementation, the display panel includes a substrate, and a barrier layer, an active layer, a first gate insulating layer, a gate layer, a second gate insulating layer, a first metal layer, an interlayer insulating layer, a first flat layer, a passivation layer, a second metal layer, a second flat layer, a pixel defining layer, and a thin film encapsulation layer stacked on a side of the substrate adjacent to the touch panel; the touch panel is arranged on the thin film packaging layer;

the passivation layer is an inorganic insulating layer, the connecting wires are located in the first metal layer in the stitch connecting area, and the passivation layer extends to the outer sides of the connecting wires to cover the connecting wires.

In a possible embodiment, the passivation layer is provided with the second planar layer on the side of the stitch connection region facing away from the first metal layer.

In one possible embodiment, the display device includes a first electrode, a second electrode, and an organic light emitting layer between the first electrode and the second electrode; the first electrode is arranged between the pixel defining layer and the second flat layer, and the second electrode is positioned on one side of the organic light-emitting layer far away from the first electrode.

In one possible embodiment, the display panel includes a thin film transistor connected to the first electrode, the thin film transistor including a gate electrode, a source electrode, and a drain electrode;

the grid electrode is positioned on the grid electrode layer, and the drain electrode and the source electrode are positioned on the first metal layer; the second metal layer includes an electrode connection part connecting the drain electrode and the first electrode.

In one possible embodiment, the display panel includes a scan line, a data line, and a power signal line connected to the thin film transistor, the scan line is located in the gate layer, and the data line and the power signal line are located in the second metal layer. .

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or related technologies of the present application, the drawings needed to be used in the description of the embodiments or related technologies are briefly introduced below, it is obvious that the drawings in the following description are only one or more embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present disclosure;

fig. 2 is a schematic diagram of a pixel circuit in a display device according to an embodiment of the present disclosure;

fig. 3 is a schematic diagram of a display panel according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a FMOLC according to an embodiment of the present application;

fig. 5 is a partial schematic view of a display panel in a non-display area according to an embodiment of the present disclosure;

FIG. 6 is a first cross-sectional view of a related art display device at the stitch bond area;

FIG. 7 is a cross-sectional view of a related art display device in the stitch bond area;

fig. 8 is a cross-sectional view of a display device in the stitch bond area in an embodiment of the present application.

Description of the reference numerals:

1-display panel, 2-display area, 3-non-display area, 4-pixel unit, 5-sub-pixel, 6-first electrode, 7-scanning line, 8-data line, 9-thin film transistor, 10-barrier layer, 11-second gate insulating layer, 12-interlayer insulating layer, 13-first flat layer, 14-second flat layer, 15-pixel defining layer, 16-first inorganic packaging layer, 17-organic packaging layer, 18-second inorganic packaging layer, 19-thin film packaging layer, 20-second electrode, 21-organic light emitting layer, 22-second metal layer, 23-passivation layer, 24-first metal layer, 25-first insulating layer gate, 26-gate layer, 27-active layer, 28-substrate, 29-first organic layer, 30-first touch layer, 31-second organic layer, 32-second touch layer, 33-third organic layer;

100: first stitch area, 200: stitch connection area, 300-second stitch area.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The embodiment of the application provides a display device which comprises a display panel and a touch panel.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure, and as shown in fig. 1, the display panel 1 includes a display Area 2 (an Active Area, AA Area for short) and a non-display Area 3 located outside the display Area 2.

The display panel 1 is provided with a plurality of pixel units 4 in the display area 2, and the plurality of pixel units 4 are arranged in an array to form a pixel array. Each pixel unit 4 includes a plurality of sub-pixels 5, and the sub-pixels 5 are light emitting devices capable of emitting a single color, for example, the pixel unit 4 includes a first sub-pixel, which is a G sub-pixel capable of emitting Green (Green) light, a second sub-pixel, which is an R sub-pixel capable of emitting Red (Red) light, and a third sub-pixel, which is a B sub-pixel capable of emitting Blue (Blue) light. When the display panel 1 performs display, color display is realized by controlling the light emission of the various sub-pixels 5 in each pixel unit 4.

The pixel unit 4 may be an OLED (Organic Light-Emitting Diode), a QLED (Quantum Dot Light Emitting Diode), a Mini LED (sub-millimeter Light Emitting Diode), or a Micro-LED (Micro Light Emitting Diode), and the description is given by taking the pixel unit 4 as an OLED pixel unit, where the OLED pixel unit includes OLED sub-pixels capable of Emitting different colors.

The OLED sub-pixel comprises a first electrode, an organic light emitting layer and a second electrode, wherein the organic light emitting layer is located between the first electrode and the second electrode, and light emission of the organic light emitting layer can be achieved by controlling the first electrode and the second electrode. The organic light emitting layers corresponding to the OLED subpixels of different colors are different. At least one of a Hole Transport Layer (HTL), a Hole Injection Layer (HIL), an Electron Transport Layer (ETL), and/or an Electron Injection Layer (EIL) may be further disposed between the first electrode and the second electrode to improve the light emitting efficiency of the organic light emitting layer.

In a display panel 1 having OLED pixel units, the display panel 1 includes a pixel circuit for controlling OLED sub-pixels and a first electrode connected to the pixel circuit, fig. 2 is a schematic diagram of the pixel circuit in a display device provided in an embodiment of the present application, and as shown in fig. 2, the pixel circuit includes a plurality of scan lines (gates) 7 and a plurality of Data lines (Data)8 arranged in a crossing manner, and further includes a plurality of Thin Film Transistors (TFTs) 9 corresponding to the OLED sub-pixels. The thin film transistor 9 comprises a grid electrode, a source electrode and a drain electrode, the drain electrode of the thin film transistor 9 is connected with the first electrode 6 of the corresponding OLED sub-pixel, the grid electrode of the thin film transistor 9 is connected with the scanning line 7, and the source electrode of the thin film transistor 9 is connected with the data line 8.

The scanning lines 7 are provided corresponding to pixel rows in the pixel array, and the gates of the thin film transistors 9 of the pixel units 4 in the same pixel row are connected to the same scanning line 7. The data lines 8 are arranged corresponding to pixel columns in the pixel array, and the sources of the thin film transistors 9 of the pixel units 4 in the same pixel column are connected with the same data line 8.

Fig. 3 is a schematic view of a display panel according to an embodiment of the present disclosure, and as shown in fig. 3, the display panel 1 includes a substrate 28, and a barrier Layer (Buffer)10, an active Layer 27, a first gate insulating Layer (GI)25, a gate Layer 26, a second gate insulating Layer 11, an interlayer Insulating Layer (ILD) 12, a first metal Layer 24, a first Planarization Layer 13 (PLN), a passivation Layer (PVX) 23, a second metal Layer 22, a second Planarization Layer 14, a Pixel Definition Layer 15 (PDL), an OLED subpixel, and a Thin-Film Encapsulation Layer (TFE) 19, which are stacked on one side of the substrate 28 in a direction close to a touch panel.

The substrate 28 may be a rigid plate, such as a glass plate, a quartz plate, or an acrylic plate; the substrate 28 is also a flexible substrate capable of being bent, and the flexible substrate may be made of a polymer material such as Polyimide (PI), Polycarbonate (PC), Polyethersulfone (PES), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), Polyarylate (PAR), or glass Fiber Reinforced Plastic (FRP). In the present embodiment, the substrate 28 is described by taking a flexible board manufactured by PI as an example.

The barrier layer 10 is disposed on one side of the substrate 28 close to the touch panel, and is an inorganic insulating film layer, which may be made of a silicon-containing inorganic material, and may be a multilayer or single-layer structure, where the silicon-containing inorganic material may be at least one of silicon oxide SiO2, silicon nitride SiNx, and silicon oxynitride SiON. By such a design, the flexible substrate and the structure on the flexible substrate are isolated, penetration of foreign substances, moisture, or external air from below the flexible substrate is reduced or blocked, and a flat surface can be provided, by using material characteristics of the inorganic material.

The active layer 27 is disposed on a side of the barrier layer 10 away from the substrate 28, and may be made of Amorphous silicon (abbreviated as α -Si), polysilicon (abbreviated as Poly-Si), Low-temperature polysilicon (LTPS), or metal oxide (abbreviated as IGZO).

The first gate insulating layer 25 is disposed on a side of the active layer 27 away from the substrate 28, and a gate layer 26 is disposed on a side of the first gate insulating layer 25 away from the substrate 28, the gate layer 26 including a gate electrode and the scan line 7. The active layer 27 includes a channel region corresponding to the gate electrode.

The second gate insulating layer 11 is disposed on a side of the gate electrode layer 26 away from the substrate base 28, and the interlayer insulating layer 12 is disposed on a side of the second gate insulating layer away from the substrate base 28. The first metal layer 24 is disposed on a side of the interlayer insulating layer 12 away from the substrate 28. The side of the first metal layer 24 away from the substrate base plate 28 is provided with the first planarization layer 13 and the passivation layer 23, and the side of the passivation layer 23 away from the substrate base plate 28 is provided with the second metal layer 22.

The first metal layer 24 and the second metal layer 22 are metal layers at different heights, and the source and drain electrodes of the thin film transistor 9, and the data line 8, the power supply signal line VDD, and the like of the display panel 1 may be selectively provided in the first metal layer 24 or the second metal layer 22, and for some signal lines, may be provided in both the first metal layer 24 and the second metal layer 22. Through the mode of routing in different metal layers, the influence of coupling capacitance on signals can be reduced, and the adaptive scene of high refresh rate is facilitated to adapt.

In the present embodiment, the first metal layer 24 is used for forming a source electrode and a drain electrode of the thin film transistor 9, and the second metal layer 22 is used for forming signal lines such as the data line 8 and the power signal line VDD and for connecting the first electrode 6 and the drain electrode.

The second metal layer 22 is provided with a second flat layer 14 on the side away from the substrate 28, and the side of the second flat layer 14 away from the substrate 28 has a flat surface, which facilitates the fabrication and formation of the structure thereon.

The pixel defining layer 15 is disposed on a side of the second flat layer 14 away from the flexible substrate, and has a pixel opening, and the first electrode 6 in the OLED sub-pixel is disposed between the pixel defining layer 15 and the second flat layer 14 and is exposed through the pixel opening. The first electrode 6 is connected to an electrode connection portion in the second metal layer 22 through a via hole, the electrode connection portion being for connecting the first electrode 6 and the drain electrode. The organic light emitting layer 21 is disposed in the pixel opening. The second electrode 20 is located on a side of the organic light-emitting layer 21 remote from the first electrode 6.

In the above embodiments, the first gate insulating layer 25, the second gate insulating layer 11, the interlayer insulating layer 12, and the passivation layer 23 are all inorganic insulating film layers, and may be made of silicon-containing inorganic materials, and may have a multilayer or single-layer structure, and the silicon-containing inorganic material may be at least one of silicon oxide SiO2, silicon nitride SiNx, and silicon oxynitride SiON.

The thin film encapsulation layer 19 of the display panel 1 covers one side of the OLED pixel unit, which is far away from the substrate base plate 28, so that the OLED pixel unit is hermetically wrapped. The film encapsulation layer 19 includes an organic encapsulation layer and an inorganic encapsulation layer which are stacked, and the inorganic encapsulation layer is at least hermetically wrapped on one side of the organic encapsulation layer 17 far away from the flexible substrate, namely the outer side of the organic encapsulation layer.

The inorganic packaging layer is made of a silicon-containing inorganic material, and the silicon-containing inorganic material can be at least one of silicon oxide SiO2, silicon nitride SiNx and silicon oxynitride SiON. The material of the organic encapsulation layer can be polymers such as acrylic-based polymers and silicon-based polymers. The inorganic packaging layer has good water and oxygen blocking performance, and the influence of external water and oxygen on organic materials in the OLED pixel units is prevented. The organic encapsulating layer 17 can absorb and disperse the stress between layers well, and prevent the compact inorganic encapsulating layer from generating cracks to reduce the barrier property to water and oxygen.

Referring to fig. 3, in the present embodiment, the thin film encapsulation layer 19 includes a first inorganic encapsulation layer 16, an organic encapsulation layer 17 and a second inorganic encapsulation layer 18 stacked along a direction away from the substrate 28, and the first inorganic encapsulation layer 16 and the second inorganic encapsulation layer 18 are disposed on two sides of the organic encapsulation layer 17 and seal-wrap the organic encapsulation layer 17 to fully exert the water blocking performance of the inorganic encapsulation layer.

In order to meet the stress requirement of large-angle bending, one or more organic layers and inorganic layers can be added on the side of the thin film encapsulation layer 19 away from the substrate 28.

The touch panel in the display device is arranged at the outer side of the thin film packaging Layer 19 to form a Flexible Multi-Layer cover surface type (FMLOC for short) structure, and the FMLOC integrates the touch panel and the display panel 1 together, so that the display device has the advantages of being light, thin, foldable and the like, and can meet the product requirements of Flexible folding, narrow frames and the like.

Fig. 4 is a schematic structural diagram of an FMLOC according to an embodiment of the present disclosure, as shown in fig. 4, the FMLOC includes a first organic layer 29, a first touch layer 30, a second organic layer 31, a second touch layer 32, and a third organic layer 33 stacked along a direction away from a thin film encapsulation layer 19. In this embodiment, a negative photoresist (OC paste) may be used for each of the first, second, and third

organic layers

29, 31, and 33.

The first touch layer 30, the second organic layer 31, and the second touch layer 32 form a mutual capacitance touch device, and in a specific example, the first touch layer 30 includes a plurality of connection bridges, and the second touch layer 32 may include a plurality of first touch electrodes arranged in a first direction and a plurality of second touch electrodes arranged at intervals in a second direction perpendicular to the first direction. Two adjacent first touch electrodes are integrally connected, and two adjacent second touch electrodes are connected with a connecting bridge through via holes formed in the touch insulating layer, namely the two adjacent second touch electrodes are connected by the connecting bridge.

In a possible embodiment, the connecting bridge may be disposed on the second touch layer 32, and accordingly, the first touch layer 30 has a first touch electrode and a second touch electrode disposed therein.

The first touch layer 30 and the second touch layer 32 include at least one of Indium Tin Oxide (ITO), Metal Mesh, and nano silver wires.

The FMLOC is disposed outside the thin film encapsulation layer 19, and the touch area having the mutually compatible touch device may be overlapped with the display area 2 or slightly larger than the display area 2.

Fig. 5 is a partial schematic view of a non-display area of a display panel provided in an embodiment of the present application, as shown in fig. 5, the non-display area includes a first stitch area 100, a second stitch area 300 and a stitch connecting area 200, a plurality of stitches are arranged in the first stitch area 100 and the second stitch area 300 side by side, and the stitch connecting area 200 is provided with a connection routing of stitches in the first stitch area 100 and the second stitch area 300.

In the present embodiment, the display device is packaged by COP, and includes a control chip and a Flexible Printed Circuit (FPC), where the first pin area 100 is a bonding area bonded to the control chip, and the second pin area 300 is a bonding area bonded to the Flexible Circuit.

In the stitch bond area 200, the passivation layer 23 in the display panel 1 remains, the first planarization layer 13 is removed, the second planarization layer 14 remains, the pixel definition layer 15 is removed, and the second planarization layer 14 is located on the outer side away from the substrate base plate 28. The second flat layer 14 is over-etched once during the post PDL development Descum dry etch process.

Since the organic layer in the organic FMLOC has poor adhesion with the organic layer in the display panel 1, a peeling problem may occur between the organic layer of the organic FMLOC process stage and the organic layer in the display panel 1 during the organic FMLOC process. Therefore, in order to avoid such Peeling, the first organic layer 29, the second organic layer 31, and the second organic layer 31 are removed. Moreover, since the stitch connecting area 200 is located outside the touch area, the first touch layer 30 and the second touch layer 32 in the touch panel are also removed.

That is, in the pin connection region 200, the process flow of the organic FMLOC is as follows: the first organic layer 29 is removed by exposure and development, the first touch layer 30 is removed by dry etching, the second organic layer 31 is removed by exposure and development, the second touch layer 32 is removed by dry etching, and the third organic layer 33 is removed by exposure and development.

Fig. 6 is a cross-sectional view of a related art display device at a pin connection area, as shown in fig. 6, in the related art, connection traces of a pin connection area 200 are formed in a second metal layer 22, and the outside of the connection traces is covered by a second planarization layer 14. However, in the process of the organic FMLOC process, the second flat layer 14 is over-etched, and multiple over-etches lead to that only a part of the second flat layer 14 is left in the gap of the connection trace, and a short of the connection trace is easily caused by the residue of the second touch layer 32 in the gap. And the surface of the connecting wire is not protected, and the reliability is poor.

Fig. 7 is a first cross-sectional view of the display device in the related art at the stitch connection area, as shown in fig. 7, even if the thickness of the second flat layer 14 is increased to ensure that the second flat layer 14 still maintains the ideal film thickness at the outer side of the connection trace after multiple over-etching, in this case, only the second flat layer 14 is at the outer side of the connection trace, and the reliability is easily lost under high temperature and high humidity.

In view of this, in the display device provided in the embodiment of the present application, the connection traces located at the stitch connecting area 200 are fabricated in the first metal layer 24.

Fig. 8 is a cross-sectional view of the display device in the embodiment of the present application at the stitch bonding area, as shown in fig. 8, the passivation layer 23 and the second planarization layer 14 are covered outside the first metal layer 24 where the connection trace is located at the stitch bonding area. Therefore, in the organic FMLOC process segment, even if the second planarization layer 14 is etched for multiple times, due to the passivation layer 23, even if there is metal residue in the gap of the connection trace, a short of the connection trace is not caused. Moreover, the passivation layer 23 is made of at least one of silicon oxide SiO2, silicon nitride SiNx and silicon oxynitride SiON, has good water and oxygen barrier property, and can ensure the reliability of the connection wiring in a high-temperature and high-humidity environment.

The above embodiment has been described by taking the connection trace formed in the first metal layer 24 as an example, but the application is not limited thereto, and the above-mentioned defects in the related art can be overcome by covering the connection trace with an inorganic insulating layer. The inorganic insulating layer covering the connecting wires can be a passivation layer, and also can be a part of other inorganic insulating layers in the display area extending to the pin wire area; it may also be a separately provided inorganic insulating layer.

For example, the connection trace is formed in the gate layer 26, and at least one inorganic insulating layer of the first gate insulating layer 25, the second gate insulating layer 11, the interlayer insulating layer 12, the passivation layer 23, the first inorganic packaging layer 16, and the second inorganic packaging layer 18 is formed on the outer side of the connection trace.

In addition, in the above embodiments, the first stitch area 100 is a binding area bound with the control chip, and the second stitch area 300 is a binding area bound with the flexible circuit board. However, the embodiments of the present application are not limited thereto, for example, the first stitch area may be a binding area, and the second stitch area may be a test area having test stitches.

In the description of the embodiments of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the referred device or element must have a specific orientation, be configured in a specific orientation, and operate, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the embodiments of the present application, it should be noted that the terms "mounted," "connected," and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected unless explicitly stated or limited otherwise; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. Specific meanings of the above terms in the embodiments of the present application can be understood in specific cases by those of ordinary skill in the art.

In addition, the technical features mentioned in the different embodiments of the present application can be combined with each other as long as they do not conflict with each other.

So far, the technical solutions of the present application have been described in connection with the preferred embodiments shown in the drawings, but it is easily understood by those skilled in the art that the scope of the present application is obviously not limited to these specific embodiments. Equivalent changes or substitutions of related technical features can be made by those skilled in the art without departing from the principle of the present application, and the technical scheme after the changes or substitutions will fall into the protection scope of the present application.

Claims

1. The display device is characterized by comprising a display panel and a touch panel, wherein the touch panel is of an organic flexible multilayer covering surface type structure;

the display panel comprises a display area and a non-display area, the non-display area comprises a first stitch area, a second stitch area and a stitch connecting area, the stitch connecting area is internally provided with a connecting wire for connecting stitches in the first stitch area and the second stitch area, and the connecting wire is covered by the inorganic insulating layer.

2. The display device according to claim 1, wherein the touch panel includes a first organic layer, a first touch layer, a second organic layer, a second touch layer, and a third organic layer which are stacked in a direction away from the display panel;

3. The display device according to claim 2, wherein the first organic layer, the second organic layer, and the third organic layer each use a negative type photoresist.

4. The display device according to claim 2, wherein one of the first touch layer and the second touch layer is provided with a plurality of connecting bridges, and the other is provided with a plurality of first touch electrodes arranged in a first direction and a plurality of second touch electrodes arranged at intervals in a second direction perpendicular to the first direction;

5. The display device according to claim 4, wherein the first touch layer and the second touch layer comprise at least one of indium tin oxide, a metal mesh, and nano silver wires.

6. The display device according to claim 1, wherein the display device comprises a control chip and a flexible circuit board, the first stitch area is a binding area bound with the control chip, and the second stitch area is a binding area bound with the flexible circuit board.

7. The display device according to claim 1, wherein the inorganic insulating layer has a single-layer or multi-layer structure and comprises at least one of silicon oxide, silicon nitride, and silicon oxynitride.

8. The display device according to any one of claims 1 to 7, wherein the display panel comprises a substrate base plate, and a barrier layer, an active layer, a first gate insulating layer, a gate layer, a second gate insulating layer, a first metal layer, an interlayer insulating layer, a first flat layer, a passivation layer, a second metal layer, a second flat layer, a pixel defining layer, and a thin film encapsulation layer, which are stacked on a side of the substrate base plate adjacent to the touch panel; the touch panel is arranged on the thin film packaging layer;

the passivation layer is an inorganic insulating layer, the connecting wires are located in the first metal layer in the pin connecting area, and the passivation layer extends to the outer sides of the connecting wires to cover the connecting wires.

9. A display device as claimed in claim 8, characterized in that the passivation layer is provided with the second planar layer at the side of the stitch connection region facing away from the first metal layer.

10. The display device according to claim 7, wherein the display device comprises a first electrode, a second electrode, and an organic light-emitting layer between the first electrode and the second electrode; the first electrode is arranged between the pixel defining layer and the second flat layer, and the second electrode is positioned on one side of the organic light-emitting layer far away from the first electrode.

11. The display device according to claim 10, wherein the display panel comprises a thin film transistor connected to the first electrode, the thin film transistor comprising a gate electrode, a source electrode, and a drain electrode;

12. The display device according to claim 11, wherein the display panel comprises a scan line, a data line, and a power signal line connected to the thin film transistor, wherein the scan line is located in the gate layer, and wherein the data line and the power signal line are located in the second metal layer.