CN114442736B

CN114442736B - Clock configurator based on dynamic configuration interface and FPGA system

Info

Publication number: CN114442736B
Application number: CN202011204534.8A
Authority: CN
Inventors: 阴智昊; 卢笙; 范凯
Original assignee: Xinqiyuan Shanghai Semiconductor Technology Co ltd
Current assignee: Xinqiyuan Shanghai Semiconductor Technology Co ltd
Priority date: 2020-11-02
Filing date: 2020-11-02
Publication date: 2023-09-05
Anticipated expiration: 2040-11-02
Also published as: CN114442736A

Abstract

The application provides a clock configurator based on a dynamic configuration interface and an FPGA system, wherein the clock configurator comprises: one or more protocol interfaces to obtain address information of the host representing the read-write request; a path manager for assigning paths to corresponding state managers; a state manager, comprising: a configuration register, a status register corresponding to the PLL, and a DRP switch corresponding to the DRP control logic; the state manager is used for detecting the PLL state and the DRP control logic state in real time and storing the PLL state and the DRP control logic state into the state register; the configuration register is used for receiving and analyzing the write request so as to update the configuration register and the state register, and judging the state of the PLL according to the DRP control logic so as to configure the configuration register. The clock configurator based on the dynamic interface can adjust various parameters of the PLL in real time, effectively saves bit stream file compiling time consumed by adjusting clock frequency or various parameters of the clock, and is a more efficient FPGA clock management scheme.

Description

Clock configurator based on dynamic configuration interface and FPGA system

Technical Field

The present application relates to the field of clock dynamic configuration technology, and in particular, to a clock configurator and an FPGA system based on a dynamic configuration interface.

Background

Currently, FPGAs are widely used in various industries, and the resources of FPGAs are very important for certain products, and clock resources are the most important part. Most PLLs within FPGAs leave a dynamic configuration port for changing the configuration of the PLL when needed.

But the time consumed for large-scale FPGA systems to generate bit stream files can be very long. Because the clock frequency or clock parameters cannot be modified when generating the bit stream file, the bit stream file is re-uploaded when the clock frequency needs to be adjusted, which results in more time consumption.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present application is to provide a clock configurator and FPGA system based on a dynamic configuration interface, so as to effectively save the bit stream file compiling time consumed by adjusting the clock frequency or each parameter of the clock.

To achieve the above and other related objects, the present application provides a clock configurator based on a dynamic configuration interface for a slave device, the clock configurator comprising: one or more protocol interfaces for interacting with the host to obtain address information of the host representing the read-write request; the path manager is used for identifying the register address in the address information and distributing the path to the corresponding state manager aiming at the legal register address; a state manager, comprising: a configuration register, a status register corresponding to the PLL, and a DRP switch corresponding to the DRP control logic; the state manager is used for detecting the PLL state and DRP control logic state in real time and storing the PLL state and DRP control logic state into the state register; the configuration register is used for receiving and analyzing the write request so as to update the configuration register and the state register, and judging the state of the PLL according to the DRP control logic so as to configure the configuration register.

In an embodiment of the present application, the determining the state of the PLL for configuring the configuration register according to the DRP control logic includes: judging whether the state of the PLL is a configurable state according to the state register; if the state is the non-configurable state, waiting until the state is the configurable state; if the configuration state is the configurable state, the DRP switch is opened to trigger the DRP control logic to analyze the writing request content, and the time sequence of the configuration register is converted into the dynamic configuration port time sequence of the PLL so as to complete the configuration of the configuration register.

In an embodiment of the present application, the configuration register is further configured to receive and parse a read request to read a current PLL state and a DRP control logic state included in a state register of the state manager of the corresponding path.

In one embodiment of the present application, the method for determining the state of a PLL for configuring the configuration register by the host according to DRP control logic includes: the host reads the current PLL state and the DRP control logic state through the state register; and when the state of the PLL is a configurable state, writing a numerical value into a configuration register of a corresponding path to complete the configuration of the configuration register.

In an embodiment of the present application, when the slave device is a single slave device, the path manager is only responsible for path allocation; and/or, when the slave device is a multi-slave device, the path manager further comprises: an arbitration function, and a blocking function for determining allocation of paths based on register addresses of the host and states of the state manager.

In an embodiment of the present application, the path manager includes an arbitration register for implementing an arbitration mechanism by dynamically allocating priorities of protocol interfaces; when a plurality of protocol interfaces access the same path at the same time, the arbitration register of the path manager only allows the access of the protocol interface which is dynamically preset as the first choice, and refuses the access of the rest protocol interfaces.

In one embodiment of the present application, the blocking mechanism includes: if the current path is occupied by a certain protocol interface, marking the current path as an occupied state so as to enable the other protocol interfaces to answer the correct address when accessing the current path, and carrying out data answer representing the error condition in a data stage.

In one embodiment of the present application, the protocol interface includes: any one or a plurality of combinations of I2C, SPI and UART.

To achieve the above and other related objects, the present application provides an FPGA system, comprising: slave devices, and hosts; the slave device includes: a clock configurator based on a dynamically configurable interface as described above.

In summary, the clock configurator and the FPGA system based on the dynamic configuration interface of the present application include: one or more protocol interfaces for interacting with the host to obtain address information of the host representing the read-write request; the path manager is used for identifying the register address in the address information and distributing the path to the corresponding state manager aiming at the legal register address; a state manager, comprising: a configuration register, a status register corresponding to the PLL, and a DRP switch corresponding to the DRP control logic; the state manager is used for detecting the PLL state and DRP control logic state in real time and storing the PLL state and DRP control logic state into the state register; the configuration register is used for receiving and analyzing the write request so as to update the configuration register and the state register, and judging the state of the PLL according to the DRP control logic so as to configure the configuration register.

Has the following beneficial effects:

the clock configurator based on the dynamic interface can adjust various parameters of the PLL in real time, effectively saves bit stream file compiling time consumed by adjusting clock frequency or various parameters of the clock, and is a more efficient FPGA clock management scheme.

Drawings

FIG. 1 is a schematic diagram of a clock configurator based on a dynamic configuration interface according to an embodiment of the present application.

Fig. 2A is a schematic flow chart of the present application applied to a single slave device in an embodiment.

Fig. 2B is a schematic flow chart of the present application applied to a multi-slave device in an embodiment.

Fig. 3 is a schematic structural diagram of an FPGA system according to an embodiment of the application.

Detailed Description

Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.

It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present application by way of illustration, and although only the components related to the present application are shown in the drawings and not drawn according to the number, shape and size of the components in actual implementation, the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.

Throughout the specification, when a portion is said to be "connected" to another portion, this includes not only the case of "direct connection" but also the case of "indirect connection" with other elements interposed therebetween. In addition, when a certain component is said to be "included" in a certain section, unless otherwise stated, other components are not excluded, but it is meant that other components may be included.

The first, second, and third terms are used herein to describe various portions, components, regions, layers and/or sections, but are not limited thereto. These terms are only used to distinguish one portion, component, region, layer or section from another portion, component, region, layer or section. Thus, a first portion, component, region, layer or section discussed below could be termed a second portion, component, region, layer or section without departing from the scope of the present application.

Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" specify the presence of stated features, operations, elements, components, items, categories, and/or groups, but do not preclude the presence, presence or addition of one or more other features, operations, elements, components, items, categories, and/or groups. The terms "or" and/or "as used herein are to be construed as inclusive, or meaning any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: a, A is as follows; b, a step of preparing a composite material; c, performing operation; a and B; a and C; b and C; A. b and C). An exception to this definition will occur only when a combination of elements, functions or operations are in some way inherently mutually exclusive.

As shown in fig. 1, a schematic diagram of a clock configurator based on a dynamic configuration interface in an embodiment of the present application is shown. The clock configurator 100 is used for slave devices, and as shown in the figure, the clock configurator 100 includes: one or more protocol interfaces 110, a path manager 120, and a state manager 130.

One or more protocol interfaces 110 for interacting with the host to obtain address information of the host representing the read/write request;

in the present application, in one aspect, the number of the protocol interfaces 110 may be one or more, and it should be noted that the number of the plurality of protocol interfaces 110 shown in fig. 1 may not be only a plurality but also one; in addition, when the protocol interfaces 110 are different, the path allocation schemes in the path manager 120 are correspondingly different. In another aspect, the protocol interface 110 includes, but is not limited to: any one of I2C, SPI and UART are combined, so that a rich and flexible interface mode is provided.

In brief, the protocol interface 110 is used primarily as a slave device to interact with a host for the host to read from and write to registers of the state manager 130 via register access by the protocol interface 110.

The path manager 120 is configured to identify a register address in the address information, and allocate a path to a corresponding state manager 130 for a legal register address, so that the host performs a read-write operation on a register of the state manager 130.

In the present application, the path manager 120 is configured to allocate a DRP path for a host to access through the protocol interface 110, which identifies a register address received by the protocol interface 110, allocates the path to the corresponding state manager 130, and writes or reads back a register of the corresponding path when the host performs a read/write operation.

Normally, the path manager 120 will only correctly respond to legitimate addresses, and will incorrectly respond to illegitimate addresses.

In an embodiment of the present application, when the slave device is a single slave device, the path manager 120 is only responsible for path allocation; and/or, when the slave device is a multi-slave device, the path manager 120 further includes: an arbitration function, and a blocking function for determining allocation of paths based on register addresses of the hosts and states of the state manager 130.

As shown in fig. 2A, a flow diagram is shown as applied to a single slave device; as shown in fig. 2B, a flow diagram for a multi-slave device is shown. Wherein, the multiple protocol interfaces 110 in fig. 2B may be interfaces using different protocols. In addition, the state management of multiple DRPs by the path manager 120, that is, corresponding to different state managers 130, and the DRP logic in each state manager 130 is also different according to the timing, parameters, etc. of each configuration register 132, but the principle and manner of determining the state of the PLL for configuring the configuration registers 132 are the same.

In short, when the clock configurator 100 includes a protocol interface 110, i.e. is a single slave device, the manager is only responsible for path allocation; when the clock configurator 100 includes a plurality of protocol interfaces 110, i.e., the manager is a multi-slave device, the path manager 120 further includes: an arbitration function, and a blocking function for determining whether a path is allocated based on the address accessed by the host and the state of the state manager 130.

Specifically, the path manager includes an arbitration register for implementing an arbitration mechanism by dynamically assigning priorities to the protocol interfaces 110; when several protocol interfaces 110 access the same path at the same time, the arbitration of the path manager only allows the access of the protocol interfaces 110 dynamically preset as the first choice, and denies the access of the rest of the protocol interfaces 110.

For example, path manager 120 includes an arbitration register that is accessible only to the first protocol port for dynamically assigning protocol port priorities. When several slave interfaces access the same path at the same time, the arbitration register in the path manager arbitrates the accesses, and the other slave interfaces can reject the accesses with the highest priority or the highest priority.

Preferably, the dynamic allocation may be by the host active device, or randomly or sequentially at a preset frequency.

In one embodiment of the present application, the blocking mechanism includes: if the current path is occupied by a certain protocol interface 110, the current path is marked as an occupied state, so that when the rest of protocol interfaces 110 access the current path, a response of a correct address is performed, and a data response representing an error condition is performed in a data stage.

For example, if the current path is occupied by a slave device interface, the current path is marked as occupied, if other slave device interfaces access the current path and perform correct address response, but the data phase performs data response of error condition, the host should recognize the condition to know that the current path is occupied.

The state manager 130 includes: a configuration register 132, a status register 131 corresponding to the PLL, and a DRP switch 133 corresponding to the DRP control logic; the state manager 130 is configured to detect PLL states and DRP control logic states in real time and store the PLL states and DRP control logic states in the state register 131; the DRP switch 133 is used to control the triggering or stopping of the DRP control logic.

When the host performs a read/write operation, address information of the host, which indicates a read/write request, reaches the state manager 130 after being distributed through a path of the path manager 120, specifically, is sent to a configuration register 132 of the state manager 130, where the configuration register 132 is configured to receive and parse the read/write request.

In one aspect, the configuration register 132 is configured to receive and parse a write request to update the configuration register 132 and the status register 131, and determine the status of the PLL according to the DRP control logic for configuring the configuration register 132.

The PLL is a phase-locked loop or phase-locked loop for unifying and integrating clock signals to make the high-frequency device work normally, such as accessing data in a memory. PLLs are used for feedback techniques in oscillators. Many electronic devices are intended to function properly, and typically require that an external input signal be synchronized with an internal oscillating signal. The common crystal oscillator cannot achieve very high frequency due to the reasons of process and cost, and when the high frequency application is needed, the corresponding device VCO is used for achieving conversion into high frequency, but the crystal oscillator is unstable, so that a stable and high-frequency clock signal can be achieved by using a phase-locked loop. The DRP is a dynamic reconfiguration interface for reconfiguring the state or parameters of the PLL.

In an embodiment of the present application, the determining the PLL state for configuring the configuration register 132 according to the DRP control logic includes:

A. whether the state of the PLL is a configurable state is determined according to the state register 131.

The state of the PLL can be simply divided into a configurable state and a non-configurable state. When the PLL is in a non-configurable state, the PLL cannot be configured by the DRP.

B. If the state is the non-configurable state, waiting until the state is the configurable state.

For example, after waiting for the PLL enable port to signal, the PLL may be determined to be in a configurable state.

C. If in the configurable state, opening the DRP switch 133 triggers the DRP control logic to parse the write request content and transfer the timing of the configuration register 132 to the dynamic configuration port timing of the PLL to complete the configuration of the configuration register 132.

Specifically, the configuration register 132 parses the write request, determines whether to trigger the subsequent DRP control logic according to the current PLL status, and parses the register contents by the DRP control logic and configures the configuration via the dynamic configuration port of the PLL.

On the other hand, the configuration register 132 is configured to receive and parse a read request to read the current PLL state and DRP control logic state contained in the state register 131 of the state manager 130 of the corresponding path. Meanwhile, whether the PLL is successfully configured can also be observed according to the status of the status register 131.

In one embodiment of the present application, in addition to the function of determining the PLL state for configuring the configuration register 132 according to the DRP control logic implemented by the state manager 130, the host may also perform the function, and the specific method includes:

A. the host reads the current PLL state and DRP control logic state through the state register 131;

B. when the state of the PLL is a configurable state, a value is written to the configuration register 132 of the corresponding path to complete the configuration of the configuration register 132.

The clock configurator 100 based on the dynamic interface can adjust various parameters of the PLL in real time, effectively saves bit stream file compiling time consumed by adjusting clock frequency or various parameters of the clock, and is a more efficient FPGA clock management scheme.

As shown in fig. 3, a schematic structure of the FPGA system according to an embodiment of the present application is shown. As shown, the system 300 includes: slave device 310, and host 320; the slave device 310 includes: a clock configurator based on a dynamic configuration interface as described in figure 1.

It should be noted that, because the content of information interaction and execution process between the above device systems is based on the same concept as the embodiment of the clock configurator according to the present application, the technical effects brought by the same concept are also the same, and the specific content can be referred to the description in the foregoing embodiment of the present application, which is not repeated here.

In summary, the clock configurator and the FPGA system based on the dynamic configuration interface provided by the present application, the clock configurator includes: one or more protocol interfaces for interacting with the host to obtain address information of the host representing the read-write request; the path manager is used for identifying the register address in the address information and distributing the path to the corresponding state manager aiming at the legal register address; a state manager, comprising: a configuration register, a status register corresponding to the PLL, and a switch corresponding to the DRP control logic; the state manager is used for detecting the PLL state and DRP control logic state in real time and storing the PLL state and DRP control logic state into the state register; the configuration register is used for receiving and analyzing the write request so as to update the configuration register and the state register, and judging the state of the PLL according to the DRP control logic so as to configure the configuration register.

The application effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be included within the scope of the appended claims.

Claims

1. A clock configurator for a slave device based on a dynamically configured interface, the clock configurator comprising:

one or more protocol interfaces for interacting with the host to obtain address information of the host representing the read-write request;

the path manager is used for identifying the register address in the address information and distributing the path to the corresponding state manager aiming at the legal register address;

a state manager, comprising: a configuration register, a status register corresponding to the PLL, and a DRP switch corresponding to the DRP control logic; the state manager is used for detecting the PLL state and DRP control logic state in real time and storing the PLL state and DRP control logic state into the state register;

the configuration register is configured to receive and parse a write request to update the configuration register and the status register, and determine a status of the PLL according to the DRP control logic for configuring the configuration register, and includes: judging whether the state of the PLL is a configurable state according to the state register; if the state is the non-configurable state, waiting until the state is the configurable state; if the configuration state is the configurable state, the DRP switch is opened to trigger the DRP control logic to analyze the writing request content, and the time sequence of the configuration register is converted into the dynamic configuration port time sequence of the PLL so as to complete the configuration of the configuration register.

2. The dynamic configuration interface based clock configurator of claim 1, wherein the configuration register is further configured to receive a read request and parse to read a current PLL state and DRP control logic state contained in a state register of the state manager of a corresponding path.

3. The dynamic configuration interface based clock configurator of claim 2, wherein the method of determining the state of the PLL for configuration of the configuration registers by the host according to the DRP control logic comprises:

the host reads the current PLL state and the DRP control logic state through the state register;

and when the state of the PLL is a configurable state, writing a numerical value into a configuration register of a corresponding path to complete the configuration of the configuration register.

4. The dynamic configuration interface based clock configurator of claim 1, wherein the path manager is responsible for path allocation only when the slave is a single slave; and/or, when the slave device is a multi-slave device, the path manager further comprises: an arbitration function, and a blocking function for determining allocation of paths based on register addresses of the host and states of the state manager.

5. The interface-based clock configurator of claim 4, wherein the path manager includes an arbitration register for implementing an arbitration mechanism by dynamically assigning priorities of protocol interfaces;

when a plurality of protocol interfaces access the same path at the same time, the arbitration register of the path manager only allows the access of the protocol interface which is dynamically preset as the first choice, and refuses the access of the rest protocol interfaces.

6. The dynamic configuration interface based clock configurator of claim 4, wherein the blocking function comprises: if the current path is occupied by a certain protocol interface, marking the current path as an occupied state so as to enable the other protocol interfaces to answer the correct address when accessing the current path, and carrying out data answer representing the error condition in a data stage.

7. The dynamic configuration interface based clock configurator of claim 1, wherein the protocol interface comprises:

any one or a plurality of combinations of I2C, SPI and UART.

8. An FPGA system, the system comprising: slave devices, and hosts; the slave device includes: a dynamically configurable interface based clock configurator as claimed in any one of claims 1 to 7.