CN114442736A - Clock configurator and FPGA system based on dynamic configuration interface - Google Patents
Clock configurator and FPGA system based on dynamic configuration interface Download PDFInfo
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- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
- G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The application provides a clock configurator, FPGA system based on dynamic configuration interface, clock configurator includes: one or more protocol interfaces to obtain address information indicating read and write requests by the host; a path manager for assigning paths to corresponding state managers; a state manager, comprising: a configuration register corresponding to the PLL, a status register, and a DRP switch corresponding to the DRP control logic; the state manager is used for detecting the PLL state and the DRP control logic state in real time and storing the PLL state and the DRP control logic state into the state register; the configuration register is used for receiving the write request and analyzing the write request so as to update the configuration register and the state register, and the state of the PLL is judged according to the DRP control logic so as to configure the configuration register. According to the clock configurator based on the dynamic interface, all parameters of the PLL can be adjusted in real time, the bit stream file compiling time consumed by adjusting the clock frequency or all parameters of the clock is effectively saved, and the clock configurator is a more efficient FPGA clock management scheme.
Description
Technical Field
The invention relates to the technical field of clock dynamic configuration, in particular to a clock configurator and an FPGA system based on a dynamic configuration interface.
Background
At present, the FPGA is widely applied to more industries, the resources of the FPGA are very important for certain products, and the clock resources are the most important part. Most PLLs within FPGAs are left with a dynamic configuration port for changing the PLL's configuration when needed.
But the time consuming generation of bit stream files by large-scale FPGA systems can be very long. Because the clock frequency or various clock parameters cannot be modified normally when the bit stream file is generated, the bit stream file is uploaded again when the clock frequency needs to be adjusted, and more time is consumed.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present application aims to provide a clock configurator and an FPGA system based on a dynamic configuration interface, so as to effectively save the compiling time of a bit stream file consumed by adjusting the clock frequency or various parameters of the clock.
To achieve the above and other related objects, the present application provides a clock configurator based on a dynamic configuration interface, for a slave device, the clock configurator comprising: one or more protocol interfaces for interacting with the host to obtain address information indicating the read-write request by the host; the path manager is used for identifying the register address in the address information and distributing a path to the corresponding state manager aiming at the legal register address; a state manager, comprising: a configuration register corresponding to the PLL, a status register, and a DRP switch corresponding to the DRP control logic; the state manager is used for detecting the PLL state and the DRP control logic state in real time and storing the PLL state and the DRP control logic state into the state register; the configuration register is used for receiving the write request and analyzing the write request so as to update the configuration register and the state register, and the state of the PLL is judged according to the DRP control logic so as to configure the configuration register.
In an embodiment of the present application, the determining the state of the PLL according to the DRP control logic for configuring the configuration register includes: judging whether the state of the PLL is a configurable state or not according to the state register; if the configurable state is not available, waiting until the configurable state is available; if the configuration register is in a configurable state, the DRP switch is opened to trigger the DRP control logic to analyze the content of the write request, and the time sequence of the configuration register is converted into the time sequence of a dynamic configuration port of the PLL, so that the configuration of the configuration register is completed.
In an embodiment of the present application, the configuration register is further configured to receive a read request and analyze the read request to read a current PLL status and a DRP control logic status included in a status register of the status manager corresponding to the path.
In an embodiment of the present application, the method for determining the state of the PLL according to the DRP control logic for configuring the configuration register by the host includes: the host reads the current PLL state and the DRP control logic state through the state register; and when the state of the PLL is a configurable state, writing a numerical value into the configuration register of the corresponding path to complete the configuration of the configuration register.
In an embodiment of the present application, when the slave device is a single slave device, the path manager is only responsible for path allocation; and/or, when the slave device is a multi-slave device, the path manager further comprises: an arbitration function, and a blocking function, for determining the allocation of the paths based on the register address of the host and the state of the state manager.
In an embodiment of the present application, the path allocator includes an arbitration register for dynamically allocating the priority of the protocol interface to implement an arbitration mechanism; when a plurality of protocol interfaces access the same path at the same time, the arbitration of the path distributor only allows the access of the protocol interface which is dynamically preset as the preferred protocol interface, and denies the access of the rest protocol interfaces.
In an embodiment of the present application, the blocking mechanism includes: if the current path is occupied by a certain protocol interface, the current path is marked as an occupied state, so that when other protocol interfaces access the current path, correct address response is carried out, and data response representing error conditions is carried out in a data stage.
In an embodiment of the present application, the protocol interface includes: any one of a plurality of combinations of I2C, SPI, and UART.
To achieve the above and other related objects, the present application provides an FPGA system, comprising: a slave device, and a host; the slave device includes: a clock configurator based on a dynamically configurable interface as described above.
To sum up, the clock configurator and the FPGA system based on the dynamic configuration interface of the present application, the clock configurator includes: one or more protocol interfaces for interacting with the host to obtain address information indicating the read-write request by the host; the path manager is used for identifying the register address in the address information and distributing a path to the corresponding state manager aiming at the legal register address; a state manager, comprising: a configuration register corresponding to the PLL, a status register, and a DRP switch corresponding to the DRP control logic; the state manager is used for detecting the PLL state and the DRP control logic state in real time and storing the PLL state and the DRP control logic state into the state register; the configuration register is used for receiving the write request and analyzing the write request so as to update the configuration register and the state register, and the state of the PLL is judged according to the DRP control logic so as to configure the configuration register.
Has the following beneficial effects:
according to the clock configurator based on the dynamic interface, all parameters of the PLL can be adjusted in real time, the bit stream file compiling time consumed by adjusting the clock frequency or all parameters of the clock is effectively saved, and the clock configurator is a more efficient FPGA clock management scheme.
Drawings
Fig. 1 is a schematic structural diagram of a clock configurator based on a dynamic configuration interface according to an embodiment of the present invention.
Fig. 2A is a flow chart illustrating an application of the present application to a single slave device in an embodiment.
Fig. 2B is a flowchart illustrating an application of the present application to a multi-slave device in an embodiment.
Fig. 3 is a schematic structural diagram of an FPGA system according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application is provided by way of specific examples, and other advantages and effects of the present application will be readily apparent to those skilled in the art from the disclosure herein. The present application is capable of other and different embodiments and its several details are capable of modifications and/or changes in various respects, all without departing from the spirit of the present application. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only schematic and illustrate the basic idea of the present application, and although the drawings only show the components related to the present application and are not drawn according to the number, shape and size of the components in actual implementation, the type, quantity and proportion of the components in actual implementation may be changed at will, and the layout of the components may be more complex.
Throughout the specification, when a part is referred to as being "connected" to another part, this includes not only a case of being "directly connected" but also a case of being "indirectly connected" with another element interposed therebetween. In addition, when a certain part is referred to as "including" a certain component, unless otherwise stated, other components are not excluded, but it means that other components may be included.
The terms first, second, third, etc. are used herein to describe various elements, components, regions, layers and/or sections, but are not limited thereto. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of the present application.
Also, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," and/or "comprising," when used in this specification, specify the presence of stated features, operations, elements, components, items, species, and/or groups, but do not preclude the presence, or addition of one or more other features, operations, elements, components, items, species, and/or groups thereof. The terms "or" and/or "as used herein are to be construed as inclusive or meaning any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: a; b; c; a and B; a and C; b and C; A. b and C ". An exception to this definition will occur only when a combination of elements, functions or operations are inherently mutually exclusive in some way.
Fig. 1 is a schematic structural diagram of a clock configurator based on a dynamic configuration interface according to an embodiment of the present application. The clock configurator 100 is for a slave device, as shown, the clock configurator 100 includes: one or more protocol interfaces 110, a path manager 120, and a state manager 130.
One or more protocol interfaces 110 for interacting with the host to obtain address information indicating the read/write request from the host;
in the present application, on one hand, the protocol interfaces 110 may be one or more, and it should be noted that the plurality of protocol interfaces 110 illustrated in fig. 1 are not only shown in plural, but also shown in one; in addition, the path allocation scheme of the path manager 120 is different for different protocol interfaces 110. On the other hand, the protocol interface 110 includes but is not limited to: any one of a plurality of combinations of I2C, SPI, and UART, thereby providing a rich and flexible interface.
Briefly, the protocol interface 110 is mainly used as a slave device to interact with a host, so that the host can read and write the register of the state manager 130 through the protocol interface 110 by means of register access.
The path manager 120 is configured to identify a register address in the address information, and allocate a path to the corresponding state manager 130 according to a legal register address, so that the host performs a read/write operation on a register of the state manager 130.
In the present application, the path manager 120 is configured to allocate a DRP path for a host to access through the protocol interface 110, identify a register address received by the protocol interface 110, and allocate the path to the corresponding state manager 130, where the host writes or reads back a register of the path when performing a read/write operation.
Typically, the path manager 120 will only respond correctly to legitimate addresses and will respond incorrectly to illegitimate addresses.
In an embodiment of the present application, when the slave device is a single slave device, the path manager 120 is only responsible for path allocation; and/or, when the slave device is a multi-slave device, the path manager 120 further includes: an arbitration function, and a blocking function for determining the allocation of the paths according to the register address of the host and the state of the state manager 130.
As shown in fig. 2A, a flow diagram is shown as applied to a single slave device; as shown in fig. 2B, a flow diagram applied to a multi-slave device is shown. In fig. 2B, the plurality of protocol interfaces 110 may be interfaces using different protocols. In addition, the DRP state management is distributed to a plurality of DRP state managers by the path manager 120, that is, the DRP logic in each state manager 130 is different according to the timing, parameters, and other factors of each configuration register 132, but the principle and manner of determining the state of the PLL for configuring the configuration register 132 are the same.
Briefly, when the clock configurator 100 includes a protocol interface 110, i.e. as a single slave device, this manager is only responsible for path allocation; when the clock configurator 100 includes a plurality of protocol interfaces 110, i.e. when the manager is a multi-slave device, the path manager 120 further includes: an arbitration function, and a blocking function, for determining whether a path is allocated according to the address accessed by the host and the state of the state manager 130.
Specifically, the path allocator includes an arbitration register for dynamically allocating the priority of the protocol interface 110 to implement the arbitration mechanism; when several protocol interfaces 110 access the same path at the same time, the arbitration of the path allocator allows access only to the protocol interface 110 that is dynamically preset as the first choice, and denies access to the remaining protocol interfaces 110.
For example, the path manager 120 includes an arbitration register that is accessible only to the first protocol port for dynamically assigning protocol port priorities. When several slave interfaces access the same path at the same time, an arbitration register in the path distributor arbitrates the accesses, the access with the highest priority or preset as the preferred access can be obtained, and the other accesses can be rejected.
Preferably, the dynamic allocation can be dynamically allocated by the host active device, or randomly or sequentially at a preset frequency.
In an embodiment of the present application, the blocking mechanism includes: if the current path is occupied by a certain protocol interface 110, the current path is marked as an occupied state, so that when the rest protocol interfaces 110 access the current path, correct address response is performed, and data response indicating error conditions is performed in a data phase.
For example, if the current path is occupied by a slave device interface, the current path is marked as occupied, if other slave device interfaces access the current path, a correct address response is performed, but the data phase performs a data response of an error condition, and the host should recognize that the current path is occupied.
A state manager 130, comprising: a configuration register 132 corresponding to the PLL, a status register 131, and a DRP switch 133 corresponding to the DRP control logic; the state manager 130 is configured to detect a PLL state and a DRP control logic state in real time and store the detected states in the state register 131; the DRP switch 133 is used to control the activation or deactivation of the DRP control logic.
When the host performs a read/write operation, address information indicating a read/write request of the host reaches the state manager 130 after being allocated by a path of the path manager 120, and specifically, the address information is sent to the configuration register 132 of the state manager 130, where the configuration register 132 is configured to receive the read/write request and analyze the read/write request.
On one hand, the configuration register 132 is configured to receive a write request and analyze the write request to update the configuration register 132 and the status register 131, and determine a PLL status according to the DRP control logic to configure the configuration register 132.
The PLL is a phase-locked loop or a phase-locked loop, and is used to integrate clock signals uniformly so that high-frequency devices can work normally, such as data access of a memory. PLLs are used for feedback techniques in oscillators. Many electronic devices normally operate by requiring an external input signal to be synchronized with an internal oscillating signal. The general crystal oscillator can not realize very high frequency due to the process and cost, and when high frequency application is needed, the corresponding device VCO realizes conversion into high frequency, but the frequency is unstable, so that a stable and high-frequency clock signal can be realized by utilizing the phase-locked loop. DRP is a dynamic reconfiguration interface for reconfiguring the state or parameters of the PLL.
In an embodiment of the present application, the determining the PLL status according to the DRP control logic for configuring the configuration register 132 includes:
A. and judging whether the state of the PLL is a configurable state or not according to the state register 131.
The state of the PLL can be simply classified into a configurable state and a non-configurable state. When the PLL is in a non-configurable state, the PLL cannot be configured by the DRP.
B. If the configurable state is not available, waiting until the configurable state is available.
For example, after waiting for the PLL enable port to send a signal, the PLL may be determined to be in the configurable state.
C. If the configuration register 132 is configurable, the DRP switch 133 is turned on to trigger the DRP control logic to parse the write request and convert the timing of the configuration register 132 to the dynamic configuration port timing of the PLL, so as to complete the configuration of the configuration register 132.
Specifically, the configuration register 132 will analyze when receiving the write request, and determine whether to trigger the subsequent DRP control logic according to the current PLL status, and the DRP control logic analyzes the register content and configures through the dynamic configuration port of the PLL.
On the other hand, the configuration register 132 is used for receiving and parsing a read request to read the current PLL status and DRP control logic status contained in the status register 131 of the status manager 130 of the corresponding path. Meanwhile, whether the PLL configuration is successful or not can be observed according to the state of the state register 131.
In an embodiment of the present application, in addition to the function of the state manager 130 determining the PLL state according to the DRP control logic for configuring the configuration register 132, the host may also complete the function, and the specific method includes:
A. the host reads the current PLL status and DRP control logic status via the status register 131;
B. when the state of the PLL is a configurable state, a value is written to the configuration register 132 of the corresponding path to complete the configuration of the configuration register 132.
According to the clock configurator 100 based on the dynamic interface, each parameter of the PLL can be adjusted in real time, the bit stream file compiling time consumed by adjusting the clock frequency or each parameter of the clock is effectively saved, and the clock configurator is a more efficient FPGA clock management scheme.
Fig. 3 is a schematic structural diagram of an FPGA system according to an embodiment of the present invention. As shown, the system 300 includes: slave 310, and host 320; the slave device 310 includes: the clock configurator based on the dynamic configuration interface as described in fig. 1.
It should be noted that, because the contents of information interaction, execution process, and the like between the device systems are based on the same concept as the embodiment of the clock configurator described in the present application, the technical effects brought by the contents are also the same, and specific contents may refer to the descriptions in the foregoing embodiments of the present application, and are not described herein again.
To sum up, the clock configurator and the FPGA system based on the dynamic configuration interface provided by the present application, the clock configurator includes: one or more protocol interfaces for interacting with the host to obtain address information indicating the read-write request by the host; the path manager is used for identifying the register address in the address information and distributing a path to the corresponding state manager aiming at the legal register address; a state manager comprising: a configuration register corresponding to the PLL, a status register, and a switch corresponding to the DRP control logic; the state manager is used for detecting the PLL state and the DRP control logic state in real time and storing the PLL state and the DRP control logic state into the state register; the configuration register is used for receiving the write request and analyzing the write request so as to update the configuration register and the state register, and the state of the PLL is judged according to the DRP control logic so as to configure the configuration register.
The application effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles and utilities of the present application and are not intended to limit the invention. Any person skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present application.
Claims (9)
1. A clock configurator based on a dynamic configuration interface, for a slave device, the clock configurator comprising:
one or more protocol interfaces for interacting with the host to obtain address information indicating the read-write request from the host;
the path manager is used for identifying the register address in the address information and distributing a path to the corresponding state manager aiming at the legal register address;
a state manager comprising: a configuration register corresponding to the PLL, a status register, and a DRP switch corresponding to the DRP control logic; the state manager is used for detecting the PLL state and the DRP control logic state in real time and storing the PLL state and the DRP control logic state into the state register;
the configuration register is used for receiving the write request and analyzing the write request so as to update the configuration register and the state register, and the state of the PLL is judged according to the DRP control logic so as to configure the configuration register.
2. The dynamic configuration interface based clock configurator of claim 1, wherein said determining the state of the PLL for configuration of said configuration register according to the DRP control logic comprises:
judging whether the state of the PLL is a configurable state or not according to the state register;
if the configurable state is not available, waiting until the configurable state is available;
if the configuration register is in a configurable state, the DRP switch is opened to trigger the DRP control logic to analyze the content of the write request, and the time sequence of the configuration register is converted into the time sequence of a dynamic configuration port of the PLL, so that the configuration of the configuration register is completed.
3. The dynamic configuration interface based clock configurator of claim 1, wherein said configuration register is further configured to receive a read request and parse it to read the current PLL status and DRP control logic status contained in the status register of said status manager of the corresponding path.
4. The dynamic configuration interface based clock configurator of claim 3, wherein said method of determining the state of the PLL according to the DRP control logic for configuration of said configuration register by said host comprises:
the host reads the current PLL state and the DRP control logic state through the state register;
and when the state of the PLL is a configurable state, writing a numerical value into the configuration register of the corresponding path to complete the configuration of the configuration register.
5. The clock configurator based on dynamic configuration interface according to claim 1, wherein said path manager is only responsible for path allocation when said slave device is a single slave device; and/or, when the slave device is a multi-slave device, the path manager further comprises: an arbitration function, and a blocking function, for determining the allocation of the paths based on the register address of the host and the state of the state manager.
6. The dynamic configuration interface based clock configurator of claim 5, wherein said path allocator comprises an arbitration register for implementing an arbitration mechanism by dynamically allocating the priority of the protocol interface;
when a plurality of protocol interfaces access the same path at the same time, the arbitration of the path distributor only allows the access of the protocol interface which is dynamically preset as the preferred protocol interface, and denies the access of the rest protocol interfaces.
7. The dynamically configurable interface based clock configurator of claim 5, wherein said blocking mechanism comprises: if the current path is occupied by a certain protocol interface, the current path is marked as an occupied state, so that when other protocol interfaces access the current path, correct address response is carried out, and data response representing error conditions is carried out in a data stage.
8. The dynamically configurable interface based clock configurator of claim 1, wherein said protocol interface comprises: any one of a plurality of combinations of I2C, SPI, and UART.
9. An FPGA system, the system comprising: a slave device, and a host; the slave device includes: a dynamically configurable interface based clock configurator according to any of claims 1 to 8.
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Denomination of invention: Clock configurator and FPGA system based on dynamic configuration interface Granted publication date: 20230905 Pledgee: Ningbo Yinsheng Investment Co.,Ltd. Pledgor: XINQIYUAN (SHANGHAI) SEMICONDUCTOR TECHNOLOGY Co.,Ltd. Registration number: Y2024980014581 |