CN114442521A - Cross control circuit between dual-redundancy signal channels - Google Patents
Cross control circuit between dual-redundancy signal channels Download PDFInfo
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- CN114442521A CN114442521A CN202111648875.9A CN202111648875A CN114442521A CN 114442521 A CN114442521 A CN 114442521A CN 202111648875 A CN202111648875 A CN 202111648875A CN 114442521 A CN114442521 A CN 114442521A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0421—Multiprocessor system
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/24—Pc safety
- G05B2219/24182—Redundancy
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Abstract
The invention provides a cross control circuit between dual-redundancy signal channels, which comprises an A channel control circuit and a B channel control circuit, wherein the A channel control circuit and the B channel control circuit have the same structure and respectively comprise a phase inverter, an AND gate, a comparator and an NMOS tube. The input end of the inverter is electrically connected with an opposite channel state signal CHV; the input end of the AND gate is electrically connected with the output end of the phase inverter and the channel state signal CHV, and the output end of the AND gate is electrically connected with the positive input end of the comparator; the reverse input end of the comparator is electrically connected with a fixed voltage REF; the output end of the comparator is electrically connected with the grid electrode of the NMOS tube of the opposite channel, and the drain electrode of the NMOS tube is electrically connected with the control end of the output circuit of the opposite channel. The cross control circuit designed by the invention can meet the requirements of working when one channel fails and entering a safe state when two channels fail, and can improve the robustness and safety of the airborne computer.
Description
Technical Field
The invention belongs to the field of airborne computers, relates to a circuit design technology for dual-redundancy signal control, and particularly relates to a cross control circuit between dual-redundancy signal channels.
Background
In the field of aircraft, in order to realize safety indexes of an electromechanical control system and improve robustness and safety of the system, a strategy of increasing redundancy control is often adopted. For example, for an onboard electromechanical control system, in order to realize control over a critical system, an onboard electromechanical computer often adopts a dual-redundancy design, that is, two physically isolated channels are designed for a single finished product, and for important and critical signals in the system, common control is performed through dual redundancies of the two channels.
However, in some existing control systems with dual redundancy design, for a control interface outputting 28V when a load requires a safe state, when a single channel fails (such as an FPGA failure and a power failure), the failed channel outputs 28V, and the other channel is normal but cannot control the load; the above-mentioned manner of controlling the load may cause the situation that the control interface is permanently in a safe state to be presented outside the control system, and the dual-redundancy control significance is lost.
Disclosure of Invention
In order to solve the problem, in an airborne electromechanical control system, when one channel fails, a control interface is required not to output 28V, so that the other normal channel can control the load, and the load is in a normal working state; when two channels are failed, the control interface outputs 28V to enter a safe state, namely, the aim of 'primary failure work and secondary failure safety' is achieved.
The technical scheme for realizing the purpose of the invention is as follows: a channel A and a channel B are respectively and electrically connected with a load through an output circuit, and the cross control circuit is used for controlling a control signal of the output circuit.
The cross control circuit comprises an A channel control circuit and a B channel control circuit, the A channel control circuit and the B channel control circuit have the same structure and respectively comprise a phase inverter, an AND gate, a comparator and an NMOS tube.
The input end of the inverter is electrically connected with a counter channel state signal CHV, and the inverter is used for inverting the counter channel state signal CHV.
The input end of the AND gate is electrically connected with the output end of the phase inverter and the channel state signal CHV, the output end of the AND gate is electrically connected with the positive input end of the comparator, and the reverse input end of the comparator is electrically connected with the fixed voltage REF.
The output end of the comparator is electrically connected with the grid electrode of the NMOS tube of the opposite channel, the source electrode of the NMOS tube is grounded, and the drain electrode of the NMOS tube is electrically connected with the control end of the output circuit of the opposite channel.
According to the invention, through designing the cross control circuit between the dual-redundancy signal channels, the requirement of the aviation airborne control system that the operation is carried out when one channel fails and the two channels enter the safe state when the two channels fail can be realized, the load product can be prevented from being degraded too fast, and the robustness and the safety of the aviation airborne computer can be greatly improved.
The principle of the cross control circuit design is as follows: and performing AND operation on the opposite channel state signal CHV after inverting and the channel state signal CHV in an AND gate, and comparing the two signals by a comparator to control the conduction or non-conduction of an NMOS tube of the opposite channel so as to control the control signal of an output circuit of the opposite channel.
In one embodiment of the present invention, the channel state signals CHV of the channels a and B are determined by the states of the FPGAs of the respective channels. When the FPGA of the channel is normal, and the channel state signal CHV of the channel is output as a channel effective signal CHV; when the FPGA of the channel is abnormal, and the channel state signal CHV of the channel is output as the channel invalid signal CHV.
In another embodiment of the present invention, the channel state signals CHV of the channel a and the channel B are determined by the CPU and the FPGA states of the respective channels. When the CPU and the FPGA of a channel are normal, the channel is normal, and a channel state signal CHV of the channel is output as a channel effective signal CHV; when any one or 2 of the CPU and the FPGA of the channel are abnormal, the channel is abnormal, and the channel state signal CHV of the channel is output as a channel invalid signal CHV.
Furthermore, the output end of the FPGA is electrically connected with the input end of the bus driver, the output end of the bus driver is electrically connected with the input end of the Darlington tube, and the output end of the Darlington tube is electrically connected with the control end of the output circuit.
Furthermore, when the channel A and the channel B are normal, the output circuits of the channel A and the channel B output an open circuit or 28V to a load under the action of the FPGA, the bus driver and the Darlington tube.
Furthermore, the control circuit further comprises a 28V voltage source, and the 28V voltage source is electrically connected with the control end of the output circuit through a voltage dividing resistor R1.
In a preferred embodiment of the present invention, when both the a channel and the B channel are abnormal, the level of the control terminal of the output circuit is determined by the 28V voltage source, and the output circuit outputs 28V to the load.
Furthermore, when any one of the channel A and the channel B is abnormal, the control end of the output circuit of the abnormal channel is grounded, and the abnormal channel is open-circuit to the load output; the interface of the cross control circuit for outputting to the load is not locked, and the output state of the cross control circuit for the load is controlled by a normal channel.
Compared with the prior art, the invention has the beneficial effects that: according to the invention, through designing the cross control circuit between the dual-redundancy signal channels, the requirement of the aviation airborne control system that the operation is carried out when one channel fails and the two channels enter the safe state when the two channels fail can be realized, the load product can be prevented from being degraded too fast, and the robustness and the safety of the aviation airborne computer can be greatly improved.
Drawings
In order to more clearly illustrate the technical solution of the embodiment of the present invention, the drawings used in the description of the embodiment will be briefly introduced below. It should be apparent that the drawings in the following description are only for illustrating the embodiments of the present invention or technical solutions in the prior art more clearly, and that other drawings can be obtained by those skilled in the art without any inventive work.
FIG. 1 is a circuit diagram of a cross control circuit between dual redundant signal paths in an embodiment.
Detailed Description
The invention will be further described with reference to specific embodiments, and the advantages and features of the invention will become apparent as the description proceeds. These examples are illustrative only and do not limit the scope of the present invention in any way. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention, and that such changes and modifications may be made without departing from the spirit and scope of the invention.
In the description of the present embodiments, it is to be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to a number of indicated technical features. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the invention, the meaning of "a plurality" is two or more unless otherwise specified.
In the airborne electromechanical control system, in order to realize that the control interface does not output 28V when one channel fails, the other normal channel can control the load, and the load is in a normal working state; when both channels fail, the control interface outputs 28V to enter a safe state, i.e., the goal of 'primary failure work, secondary failure safety' is realized.
In the airborne electromechanical control system, the A channel and the B channel are respectively and electrically connected with a load to form a dual-redundancy signal channel for controlling the load. In this embodiment, the crossing strategy and the control principle of the dual-redundancy signal channel of this embodiment are illustrated below in three cases, i.e., a channel failure and a B channel normal, both a channel and B channel normal, and both a channel and B channel failure.
The present embodiment provides a cross control circuit between dual-redundancy signal channels, where the cross control circuit is used to control a control signal of an output circuit of an a channel and/or a B channel, so as to implement cross control on the dual-redundancy signal channels. The cross control circuit comprises an a channel control circuit and a B channel control circuit, the a channel control circuit and the B channel control circuit have the same structure, as shown in fig. 1, the a channel control circuit and the B channel control circuit both comprise an inverter, an and gate, a comparator and an NMOS transistor, and the channel control circuit is described below by taking the B channel as an example.
As shown in fig. 1, the input end of the inverter of the B channel is electrically connected to a counterpart channel state signal CHV (an a channel state signal CHV, i.e., CHV _ a shown in fig. 1, which is input to the B channel and then becomes the OTHRE _ CHV of the B channel), and the inverter is used for inverting the counterpart channel state signal CHV.
Specifically, when the a channel is normal, that is, the output of the a channel state signal CHV (OTHRE _ CHV) is defined as "1", and at this time, after the inverter of the B channel inverts the a channel state signal CHV, the value of the OTHRE _ CHV output by the inverter is "0"; when the A channel is in fault or abnormal, namely the output of the A channel state signal CHV (OTHRE _ CHV) is defined as '0', and after the inverter of the B channel inverts the A channel state signal CHV, the value of the OTHRE _ CHV output by the inverter is '1'.
As shown in FIG. 1, the input terminal of the AND gate in the B channel is electrically connected to the output terminal of the inverter and the present channel state signal CHV (i.e., CHV _ B shown in FIG. 1), the output terminal of the AND gate is electrically connected to the positive input terminal of the comparator in the B channel, and the negative input terminal of the comparator is electrically connected to the constant voltage REF in the B channel.
Specifically, when the a channel fails and the B channel is normal, the value of OTHRE _ CHV at the input end of the and gate of the B channel is "1", CHV _ B is "1", and the output of the and gate is at a high level. When the channel A is normal and the channel B is normal or abnormal, one of the OTHRE _ CHV value and the CHV _ B value at the input end of the AND gate of the channel B is '1' and the other is '0', and the output of the AND gate is low level at the moment.
The high level or the low level output by the AND gate is input to the positive input end of the comparator, the fixed voltage REF is input to the negative input end of the comparator, and the high level or the low level is compared with the fixed voltage REF. When the output of the AND gate to the comparator is high level, the high level output by the AND gate is higher than the fixed voltage REF through comparison with the fixed voltage REF designed in advance by the comparator, so that the comparator outputs high level; when the output of the and gate to the comparator is low, the low level of the output of the and gate is lower than the fixed voltage REF through comparison with the fixed voltage REF designed in advance by the comparator, and thus the comparator outputs the low level.
In the above description, i.e. when the a channel fails and the B channel is normal, the comparator outputs a high level; when the A channel and the B channel are normal or the A channel and the B channel are failed, the comparator outputs low level.
As shown in fig. 1, the output terminal of the comparator in the channel B is electrically connected to the gate of the NMOS transistor in the opposite channel (i.e., the NMOS transistor in the channel a), the source of the NMOS transistor is grounded, and the drain of the NMOS transistor is electrically connected to the control terminal of the output circuit in the opposite channel.
Specifically, when the comparator outputs a high level, the NMOS transistor of the channel a is turned on, the control end of the output circuit is forced to a low level, the output circuit outputs an open circuit to the load, the interface does not enter a safe state (output 28V), the dual-redundancy output interface is not locked, the output state is determined by the channel B, and the requirement that the product is "one channel failure is working" is met. In short, when any one of the channel A and the channel B is abnormal, the control end of the output circuit of the abnormal channel is grounded, and the abnormal channel is open to the load output; the interface of the cross control circuit for outputting to the load is not locked, and the output state of the cross control circuit for the load is controlled by a normal channel. When the comparator outputs low level, the NMOS tube of the channel A is not conducted, and the channel A and the channel B have two states of all normal and all fault, so the output state of the output circuit to the load is different.
In the first example of the cross control circuit between the dual redundancy signal channels, as shown in fig. 1, the channel state signals CHV of the a channel and the B channel are respectively determined by the states of the FPGAs of the respective channels. When the FPGA of the channel is normal, and the channel state signal CHV of the channel is output as a channel effective signal CHV; when the FPGA of the channel is abnormal, and the channel state signal CHV of the channel is output as the channel invalid signal CHV.
In a second example of the cross control circuit between the dual redundancy signal channels, the channel state signals CHV of the channel a and the channel B are respectively determined by the states of the CPU and the FPGA of the respective channels (the figures are shown, the states of the CPU and the FPGA may be respectively determined, or the states of the CPU and the FPGA may be output after being monitored with each other). In this example, the CPU and the FPGA monitor each other, and when the CPU and the FPGA of a channel are both normal, the channel is normal, and the channel state signal CHV of the channel is output as a channel valid signal CHV; when any one or 2 of the CPU and the FPGA of the channel is abnormal, and the channel state signal CHV of the channel is output as a channel invalid signal CHV.
In a modified solution of the 2 examples, as shown in fig. 1, the output terminal of the FPGA is electrically connected to the input terminal of the bus driver, the output terminal of the bus driver is electrically connected to the input terminal of the darlington, and the output terminal of the darlington is electrically connected to the control terminal of the output circuit.
Furthermore, when the channel A and the channel B are both normal, the NMOS tube of the channel A is not conducted, and at the moment, the output circuits of the channel A and the channel B output an open circuit or 28V to the load after the output state of the load is acted by the FPGA, the bus driver and the Darlington tube. Specifically, when the IO output of the FPGA is at a high level, the darlington tube is grounded, the control terminal of the output circuit is at a low level, and an open circuit is output to the load product; when the IP of the FPGA outputs a high level, the output of the Darlington tube is open, the control end of the output circuit is at a high level, and 28V is output to a load product, in short, when 2 channels are normal, the output state of an interface output to the load is controllable and is determined by the control instructions of the respective channels.
Furthermore, when both the channel a and the channel B fail, the NMOS transistors of the channel a and the channel B are not turned on, and the FPGAs of the channel a and the channel B do not work, in order to output 28V to the load and enter a safe state when 2 channels fail, the present embodiment further improves the cross control circuit again, as shown in fig. 1, the control circuit further includes a 28V voltage source, and the 28V voltage source is electrically connected to the control end of the output circuit through a voltage dividing resistor R1. Specifically, when the a channel and the B channel are both abnormal, the level of the control terminal of the output circuit is determined by the 28V voltage source, and the output circuit outputs 28V to the load.
According to the invention, through designing the cross control circuit between the dual-redundancy signal channels, the requirement of the aviation airborne control system that the operation is carried out when one channel fails and the two channels enter the safe state when the two channels fail can be realized, the load product can be prevented from being degraded too fast, and the robustness and the safety of the aviation airborne computer can be greatly improved.
The principle of the cross control circuit design is as follows: and after the state signal CHV of the opposite channel is inverted, the AND gate is compared with the state signal CHV of the channel in an AND gate, and then the conduction or non-conduction of an NMOS tube of the opposite channel is controlled through a comparator, so that the control signal of an output circuit of the opposite channel is controlled.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and should not be taken as limiting the scope of the present invention, which is intended to cover any modifications, equivalents, improvements, etc. within the spirit and scope of the present invention.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (8)
1. The utility model provides a cross control circuit between two redundant signal path, A passageway and B passageway are connected with the load electricity through output circuit respectively, and cross control circuit is used for controlling output circuit's control signal, its characterized in that: the cross control circuit comprises an A channel control circuit and a B channel control circuit, wherein the A channel control circuit and the B channel control circuit have the same structure and respectively comprise a phase inverter, an AND gate, a comparator and an NMOS tube;
the input end of the inverter is electrically connected with a counter channel state signal CHV, and the inverter is used for performing inversion processing on the counter channel state signal CHV;
the input end of the AND gate is electrically connected with the output end of the phase inverter and the channel state signal CHV, the output end of the AND gate is electrically connected with the positive input end of the comparator, and the reverse input end of the comparator is electrically connected with the fixed voltage REF;
the output end of the comparator is electrically connected with the grid electrode of the NMOS tube of the opposite channel, the source electrode of the NMOS tube is grounded, and the drain electrode of the NMOS tube is electrically connected with the control end of the output circuit of the opposite channel.
2. The crossover control circuit of claim 1, wherein: the channel state signals CHV of the channel A and the channel B are respectively determined by the states of the FPGAs of the respective channels;
when the FPGA of the channel is normal, and a channel state signal CHV of the channel is output as a channel effective signal CHV;
when the FPGA of the channel is abnormal, and the channel state signal CHV of the channel is output as a channel invalid signal CHV.
3. The crossover control circuit of claim 1, wherein: the channel state signals CHV of the channel A and the channel B are respectively determined by the state of the CPU and the FPGA of each channel;
when the CPU and the FPGA of a channel are normal, the channel is normal, and a channel state signal CHV of the channel is output as a channel effective signal CHV;
and when any one or 2 of the CPU and the FPGA of the channel is abnormal, and the channel state signal CHV of the channel is output as a channel invalid signal CHV.
4. The crossover control circuit of claim 2 or 3, wherein: the FPGA output end is electrically connected with the input end of the bus driver, the output end of the bus driver is electrically connected with the input end of the Darlington tube, and the output end of the Darlington tube is electrically connected with the control end of the output circuit.
5. The crossover control circuit of claim 4, wherein: when the channel A and the channel B are normal, the output circuits of the channel A and the channel B output an open circuit or 28V to a load under the action of the FPGA, the bus driver and the Darlington tube.
6. The crossover control circuit of claim 4, wherein: the control circuit also comprises a 28V voltage source, and the 28V voltage source is electrically connected with the control end of the output circuit through a voltage dividing resistor R1.
7. The crossover control circuit of claim 6, wherein: when the A channel and the B channel are abnormal, the level of the control end of the output circuit is determined by the 28V voltage source, and the output circuit outputs 28V to a load.
8. The crossover control circuit of claim 2 or 3, wherein: when any one of the channel A and the channel B is abnormal, the control end of the output circuit of the abnormal channel is grounded, and the abnormal channel opens a load output circuit; the interface of the cross control circuit for outputting to the load is not locked, and the output state of the cross control circuit for the load is controlled by a normal channel.
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| CN114442521B (en) | 2024-03-19 |
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