CN114441947A

CN114441947A - Automatic test system signal routing method based on ATML

Info

Publication number: CN114441947A
Application number: CN202111601823.6A
Authority: CN
Inventors: 唐小峰; 邹建; 胡宇
Original assignee: Chengdu Jovian Technology Exploitation Co ltd
Current assignee: Chengdu Jovian Technology Exploitation Co ltd
Priority date: 2021-12-24
Filing date: 2021-12-24
Publication date: 2022-05-06

Abstract

The invention discloses an ATML-based automatic test system signal routing method, which comprises two stages of route map construction and signal routing search. The invention provides a signal routing method solution in signal-oriented test from the system level, thus improving the practicability of the technology; aiming at the structural characteristics of a typical ATS, a signal routing map model and a recursive depth-first search algorithm are designed, so that the problem complexity can be reduced, and the algorithm operation efficiency can be improved; the invention follows ATML international standard, and enhances the wide applicability of the signal routing method in the testing, measuring and controlling industry.

Description

Automatic test system signal routing method based on ATML

Technical Field

The invention belongs to the technical field of automatic test of equipment, and particularly relates to an automatic test system signal routing method based on ATML.

Background

An Automatic Test System (ATS) is an important component of a complex equipment guarantee, is widely applied to life cycle stages of equipment development, production, use, maintenance and the like, and provides an efficient technical approach for technicians to confirm the health state of the tested equipment.

The Automatic Test Markup Language (ATML) series standard is proposed by IEEE standardization organization, and the data structure of the element models in a typical ATS is defined by using an eXtensible Markup Language (XML) through several sub-standards, such as IEEE 1671.1 standard description Test Program (Test Program, TP), IEEE1671.2 standard description Test instrument, IEEE1671.3 standard description Unit Under Test (UUT), and the like.

The ATML-based automatic test is a signal-oriented test, namely, only the signal requirement on a UUT pin needs to be described in the TP, so that the decoupling of the test and the instrument resource is realized, and the transportability of the TP is improved.

One key technology in signal-oriented testing is the signal routing method related to the invention, namely, a signal path between a specified UUT pin and a specified instrument port is searched.

Considering that a general ATS usually includes special switching instruments such as a common switch and a matrix switch, and the complexity of the ATS itself, a higher requirement is placed on efficient implementation of a signal routing method.

There is a scheme in the prior art, which abstracts the matrix switch modules in the ATS and the combination of these modules into an undirected graph, and then uses the classical algorithm in the graph theory to find the optimal path on the matrix switch. These studies do not take into account other relevant factors in the actual system, such as single pole, multiple throw switches and complex patch connections on the system interface, and therefore do not fully guide engineering practice.

Disclosure of Invention

The invention aims to provide a signal routing method of an automatic test system based on ATML (automatic test markup language) to overcome the defects of the prior art.

The purpose of the invention is realized by the following technical scheme: an ATML-based automatic test system signal routing method comprises two stages of route map construction and signal route searching.

Further: the specific steps of the route map construction stage are as follows:

s1-1, analyzing the test station description according to the IEEE1671.6 standard, and constructing a test station routing map according to the interface and connection information contained in the test station description;

s1-2, according to the instrument examples contained in the test station description, analyzing the corresponding instrument description according to the IEEE1671.2 standard, and constructing an instrument routing map aiming at the instrument examples which are not switched;

s1-3, analyzing the UUT description according to the IEEE1671.3 standard, analyzing the test adapter and/or the test cable description according to the IEEE1671.5 standard, analyzing the UUT, the test adapter, the test cable and a connection table among all example interfaces of the test station according to the IEEE1671 standard, and constructing a routing map of the UUT end.

Further: the signal route searching stage comprises the following specific steps:

s2-1, determining the starting point-UUT pin and end point-instrument capability of signal route search, and loading a route map;

s2-2, searching available instrument resources and ports thereof having a mapping relation with the instrument capability according to the instrument routing map, and searching a corresponding instrument external port list according to the resource ports;

s2-3, if the number of each port in the external port list of the instrument and the number of the pins contained in the port list of the instrument are the same as the number of the UUT pins, recursive depth-first search is executed, and path information between the UUT pins and the instrument pins is searched in sequence.

Further: the Interface information is described in an < Interface > tag, which contains definitions of ports, connectors and pins of the test station; the connection information is described in the < NetworkList > tag, which contains two connected nodes, each of which describes a port or pin from the current test station itself or from an interface of an instrument instance therein in XPath syntax.

Further: the test station routing map is a dictionary data structure, the key of the dictionary is represented by a formatted character string of each node appearing in the test station < NetworkList > tag, and the value of the dictionary is a formatted character string list of all nodes connected with the current node obtained after analysis and combination.

Further: the instrument instance is contained in the < Instruments > tag of the test station description, including the instrument's ID, the referenced instrument description model identification, and the instrument's address.

Further: the instrument routing map has a dictionary data structure similar to that of the test station routing map, and the contents of the dictionary data structure are the connection relation between the external port and the resource port of the instrument contained in the instrument description < NetworkList > tag and the mapping relation between the resource port and the capability port contained in the < capability map > tag.

Further: the nodes of ports or pins with connection relations on different model example interfaces in the connection list among the example interfaces are described in a < WirelList > tag, and an XML file in which the tag is located conforms to the WirelLists.xsd document specification given by the IEEE1671 standard.

Further: the UUT end routing map has a dictionary data structure similar to the test station routing map, the content of the UUT end routing map is a one-way connection relation from a UUT port or a pin to a test station port or a pin, the connection relation of a cable/an adapter serving as an intermediate level is ignored, and algorithm execution efficiency is improved.

Further, the method comprises the following steps: the end-instrument capability is based on the IEEE1671.2 and IEEE1641 standards describing the ability of an instrument to generate or measure signals, including signal type and range, uncertainty and resolution of signal properties, to match the signal test requirements on the UUT pin as a search starting point in signal-oriented testing.

Further: the number of the instrument resources is consistent with that of signal generation or measurement channels of the instrument, one-to-many relation exists between the instrument capacity and the instrument resources, and when the instrument channels corresponding to the resources are occupied, the current resources are unavailable.

Further: the recursive depth-first search is started from a UUT pin as a search starting point, the information of secondary pins connected with the pin is inquired in each routing map, and then the search process is recursively executed by taking the secondary pins as new search starting points until a search termination condition is reached.

Further: the search termination condition includes that the experienced path already includes a corresponding pin on an instrument port corresponding to the instrument capability as a search end point, or the target instrument pin still cannot be found after all reachable paths have been traversed.

Further: in the recursive depth-first search process, when an instrument of a common switch type is encountered, the instrument is searched for the inside through an interface of the instrument, and when a switch is encountered, all reachable pins at the other end of the switch are taken as secondary pins to continue recursive search.

Further, the method comprises the following steps: in the recursive depth-first search process, when a matrix switch type instrument is encountered, the instrument is searched inside through an interface of the instrument, and when a matrix switch module is encountered, all other available pins on a row and column of the module are taken as secondary pins to continue recursive search.

Further: in the recursive depth-first search process, historical path information needs to be recorded, and the historical path is avoided when a new path is explored, so that repeated search and endless loop are prevented.

Further: the path information between the UUT pin and the instrument pin is composed of all pins experienced in the signal route search process, and an effective path is only obtained when the instrument pin serving as an end point is included in the pins.

The aforementioned main aspects of the invention and their respective further alternatives can be freely combined to form a plurality of aspects, all of which are aspects that can be adopted and claimed by the present invention. The skilled person in the art can understand that there are many combinations, which are all the technical solutions to be protected by the present invention, according to the prior art and the common general knowledge after understanding the scheme of the present invention, and the technical solutions are not exhaustive herein.

The invention has the beneficial effects that:

1. the invention provides a signal routing method solution in signal-oriented test from the system level, thus improving the practicability of the technology;

2. aiming at the structural characteristics of a typical ATS, a signal routing map model and a recursive depth-first search algorithm are designed, so that the problem complexity can be reduced, and the algorithm operation efficiency can be improved;

3. the invention follows ATML international standard, and enhances the wide applicability of the signal routing method in the testing, measuring and controlling industry.

4. The invention realizes the decoupling of the test program and the instrument, so that the test program running on one test system can be quickly transplanted to another system with similar test capability (including the conditions of upgrading and replacing the instrument in the test system and the like), and the technology provided by the invention can obviously reduce the maintenance and reuse cost of the test program in consideration of high debugging or verification cost of the test program of high-end equipment.

5. The developer of the test program only needs to concentrate on the test requirement of the UUT, and the distribution and control of related instruments and switch resources are automatically completed by the technology provided by the invention, so that the workload and the complexity of the test program development can be reduced, and the efficiency is improved.

Drawings

FIG. 1 is a flow chart of the present invention;

fig. 2 is a schematic view of an embodiment of the present invention.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.

It should be noted that, in order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention are clearly and completely described below, and it is obvious that the described embodiments are some embodiments of the present invention, but not all embodiments.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate orientations and positional relationships that are conventionally used in the products of the present invention, and are used merely for convenience in describing the present invention and for simplicity in description, but do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and therefore, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.

Furthermore, the terms "horizontal", "vertical", "overhang" and the like do not imply that the components are required to be absolutely horizontal or overhang, but may be slightly inclined. For example, "horizontal" merely means that the direction is more horizontal than "vertical" and does not mean that the structure must be perfectly horizontal, but may be slightly inclined.

In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

In addition, it should be noted that, in the present invention, if the specific structures, connection relationships, position relationships, power source relationships, and the like are not written in particular, the structures, connection relationships, position relationships, power source relationships, and the like related to the present invention can be known by those skilled in the art without creative work on the basis of the prior art.

Example 1:

referring to fig. 1, the invention discloses an automatic test system signal routing method based on ATML, which comprises the following specific implementation steps:

stage one: the route map construction method comprises the following steps:

step S1-1: the test station description is parsed according to the IEEE1671.6 standard, and a test station routing map is constructed based on the interface and wiring information contained therein.

The IEEE1671.6 standard is one of the ATML family of standards for describing an automated test station information that integrates several instrumentation.

The Interface information of the test station description is described in an Interface tag, wherein the Interface information comprises the definitions of ports, connectors and pins of the test station; the connection information is described in the < NetworkList > tag, which contains two connected nodes, each of which describes a port or pin from the current test station itself or from an interface of an instrument instance therein in XPath syntax.

The test station routing map is a dictionary data structure, the keys of the dictionary being a formatted string representation of each node appearing in the test station < NetworkList > tag; the value of the dictionary is a formatted character string list of all nodes connected with the current node after analysis and combination.

The instrument instance is included in the < Instruments > tag of the test station description, including the instrument's ID, referenced instrument model information, and the instrument's address, among others.

The algorithm process of the test station route map construction is as follows:

1) loading and parsing a test station description file, which is an XML file conforming to the IEEE1671.6 standard;

2) for each < Network > sub-tag in the < Network list > tag, performing the following steps 3) to 5);

3) acquiring < Path > sub-tags which are paired in < Network > tags, wherein each < Path > contains a Path character string described by XPath grammar;

4) judging whether the Path belongs to the test station or a description file from an instrument example contained in the test station according to the documentId attribute in the < Path > tag, and then acquiring two groups of pin information according to the Path character string;

5) and recording each pin contained in the two groups of pin information in pairs in a test station routing map according to the index sequence of the pin.

Step S1-2: and according to the instrument examples contained in the test station description, analyzing the corresponding instrument descriptions according to the IEEE1671.2 standard, and constructing an instrument routing map for the non-switching instrument examples.

The IEEE1671.2 standard is one of ATML series of standards, and is used to describe the relevant information of an instrument, mainly including the interface, resources, capabilities of the instrument, and the mapping relationship between them.

The Interface of the instrument is described in an < Interface > tag, which includes physical pin and signal port information external to the instrument.

The Resources of the instrument are described in < Resources > tags for the test channels of the corresponding instrument, each resource having one or more resource ports.

Capabilities of the instrument are described in the < Capabilities > tag for representing the type of signal supported by the instrument, the range of signal properties, uncertainty and resolution, etc., each capability having one or more capability ports.

The connection relation between the external port and the resource port of the instrument is described in a < NetworkList > tag, which indicates that a certain external port is a test channel corresponding to a resource.

The mapping relation between the resource port and the capability port is described in the < capability map > tag, which indicates the test function of the test channel corresponding to the resource.

Said instrument routing map having a dictionary data structure similar to said test station routing map, the dictionary keys being a formatted string representation of each node appearing in the test station < NetworkList > and < CapabilityMap > tags; the value of the dictionary is a formatted character string list of all nodes connected with the current node after analysis and combination.

Optionally, for the switch-type instrument, due to the difference in standard content, all the connection relationships are described in < NetworkList >, and the instrument routing map records the connection relationships between the ports of the switch unit and the external interfaces.

The switch unit can be a single-pole multi-throw switch device or a module of a matrix switch.

The algorithm process of the instrument routing map construction is as follows:

1) loading and parsing an instrument description file, which is an XML file conforming to the IEEE1671.2 standard;

2) if the type of the instrument is a common instrument, executing the following steps 3) to 6);

3) executing the following steps 4) to 5) for each < Network > sub-tag in the < Network list > tag;

4) acquiring < Path > sub-tags which are paired in < Network > tags, wherein each < Path > contains a Path character string described by XPath syntax, and acquiring two groups of pin information according to the content of the Path character string;

5) and recording each pin contained in the two groups of pin information in pairs in the instrument routing map according to the index sequence of the pin.

6) Executing the steps 4) to 5) for each < Mapping > sub-tag in each < capability map >;

7) if the instrument type is a common switch or a matrix switch, the steps 3) to 5) are executed.

Step S1-3: and resolving the UUT description according to the IEEE1671.3 standard, resolving the test adapter and/or the test cable description according to the IEEE1671.5 standard, resolving the UUT, the test adapter, the test cable and a connection table among the example interfaces of the test station according to the IEEE1671 standard, and constructing a routing map of the UUT end.

The IEEE1671.3 standard is one of ATML series standards, is used for describing relevant information of a Unit Under Test (UUT), and mainly comprises interfaces, compositions and the like of the UUT.

The IEEE1671.5 standard ATML series standard is used for describing relevant information of a test adapter or a test cable, and mainly comprises an interface, an internal connection line and the like of the adapter or the cable.

The IEEE1671 standard is a main standard of the ATML series of standards, in which a common data structure on which respective sub-standards depend in common is defined.

The nodes of the ports or pins which represent connection relations on the example interfaces of different models in the interconnection list among the example interfaces are described in a < WirelList > tag, and an XML file in which the tag is located conforms to the WirelLists.xsd document specification given by the IEEE1671 standard.

The UUT end routing map has a dictionary data structure similar to the routing map of the test station, the content of the UUT end routing map is a one-way connection relation from a UUT port or a pin to a test station interface port or a pin, cable/adapter connection information serving as an intermediate level is ignored, and the purpose is to improve algorithm execution efficiency.

Alternatively, an automatic test system may not contain a description model of the test adapters and cables, as would be necessary for a UUT and test station.

The algorithm process of the UUT end route map construction is as follows:

1) loading and analyzing a UUT description file, wherein the UUT description file is an XML file conforming to the IEEE1671.3 standard;

2) loading and parsing a test adapter or test cable description file, which is an XML file conforming to IEEE1671.5 standard;

3) loading and analyzing a netlist file between the interfaces, wherein the netlist file is an XML file which accords with the specification of a WirelList.

4) For each pin on the UUT interface, if the pin is contained in the connection table, the pin is taken as a key of a dictionary, the corresponding pin in the connection table is taken as a value (actually, a list) of the dictionary, and an initial UUT end routing map is constructed;

5) if the test cable description exists, each pin in the routing map of the initial UUT end is examined in sequence, and if records exist in a certain < Network > sub-tag and a connection table in a cable description < Network List > tag, the pins at two ends of the cable are all related to the corresponding UUT pins;

6) if the test adapter description exists, each pin in the current UUT end routing map is examined in sequence, and if records exist in a certain < Network > sub-tag and a connection list in the < Network list > tag of the adapter description, the pins at the two ends of the adapter are related to the corresponding UUT pins;

7) and clearing the non-test station interface pins contained in the current UUT end routing map.

And a second stage: signal routing search, comprising the steps of:

step S2-1: the start point (i.e., UUT pin) and end point (i.e., instrument capability) of the signal route search are determined and the route map information is loaded.

The instrument capability as the search endpoint is based on the signal generation or measurement capability described by the IEEE1671.2 and IEEE1641 standards, including the signal type and the range, uncertainty and resolution of the signal properties. In signal-oriented testing, the instrument capability is used to match the signal test requirements on the UUT pin as the search starting point as described in 3.

The test station routing map is realized when a test station description file is loaded; the instrument routing map is completed when the instrument examples are analyzed in the process of loading the description information of the test station; and the routing map of the UUT end is constructed after the loading of the link table description files among the UUT, the test adapter, the test cable and the interface is finished.

Step S2-2: searching available instrument resources and ports thereof which have a mapping relation with the instrument capability according to an instrument routing map, and searching a corresponding instrument external port list according to the resource ports;

the instrument resources are generally consistent with the number of signal generation or measurement channels of the instrument, and the instrument capability and the instrument resources have a one-to-many relationship. When the instrument channel corresponding to the resource is occupied, the current resource is unavailable.

The algorithm process for searching the instrument capability and the corresponding instrument external port list is as follows:

1) inputting the ID of the instrument and the ID of the capability, and executing the step 2) for each key value pair contained in the instrument routing map;

2) if the current key contains the given instrument ID and the given capability ID, then adding the current key to a resource port list for each item in the corresponding value list if the item represents a port under the same instrument and the current port is not occupied;

3) executing step 4) for each resource port in the resource port list;

4) and searching an item connected with the instrument routing map from the instrument routing map, and adding the item to the instrument external port list if the item represents the external port of the current instrument.

Step S2-3: and if the number of each port in the external port list of the instrument and the number of the pins contained in the port list of the instrument are the same as the number of the UUT pins, performing recursive depth-first search, and sequentially searching path information between the UUT pins and the instrument pins.

The recursive depth-first search is started from a UUT pin as a search starting point, the information of secondary pins connected with the pin is inquired in each routing map, and then the search process is recursively executed by taking the secondary pins as new search starting points until a search termination condition is reached.

The search termination condition includes that the experienced path already includes a corresponding pin on an instrument port corresponding to the instrument capability as a search end point, or the target instrument pin still cannot be found after all reachable paths have been traversed.

In the recursive depth-first search process, when an instrument of a common switch type is encountered, the instrument is searched for the inside through an interface of the instrument, and when a switch is encountered, all reachable pins at the other end of the switch are taken as secondary pins to continue recursive search.

In the recursive depth-first search process, when a matrix switch type instrument is encountered, the instrument firstly searches the interior through an interface of the instrument, and when a matrix switch module is encountered, all other available pins on a module row and column are taken as secondary pins to continue recursive search.

In the recursive depth-first search process, historical path information needs to be recorded, and the historical path is avoided when a new path is explored, so that repeated search and endless loop are prevented.

Historical path information between the UUT pins and the instrument pins consists of all pins experienced in the signal route searching process, an effective path is only formed when the pins contain the instrument pins serving as end points, and the historical path information and the effective path information are recorded simultaneously in the searching process.

Alternatively, on the premise of acceptable time complexity, all possible signal paths may be searched, and then an optimal path may be selected as a final path according to a certain principle, such as the minimum number of switches on the path.

This embodiment is a simplified automatic test system, as shown in fig. 2, which includes:

a UUT (UUT1) containing 3 ports and 5 pins;

the test station (ATE1) comprises a power switch (S1), a spectrometer (SA1), a digital multimeter (DM1) and a matrix switch (MT1), wherein an external interface of the test station consists of three ports and a plurality of pins, and internal instruments are switched to realize interconnection through the pins on the external interface;

and a test cable (CAB1) for connecting the interface of the UUT with the interface of the test station.

Before the first phase of route mapping is performed, modeling of each object in the test system needs to be performed based on ATML.

The following XML script example represents the interface of a UUT (similar to the interface description of other objects):

the following example of XML scripts represents the internal wiring of a test cable:

the following XML script example represents an instrument instance in a test station:

the following example of XML scripts represents the connection relationships on the teststation interface:

the following XML script example represents the connection relationship of external interfaces and resource ports and the mapping relationship of resource ports and capability ports in the instrument (SA 1):

the XML scripts are respectively contained in the ATML standard description files, and when the ATML standard description files are analyzed, the routing maps are constructed.

To implement a routing map dictionary, the pins are represented using a formatted string.

The syntax of the external interface for each model object is as follows:

< type > < object ID > < Pin string >

The type represents the type of a model to which the current pin belongs, and can be divided into a Test Station (TS), an Instrument (INS) and a device under test (UUT); the object ID is a unique identifier of the model instance; the pin string format is: < connector ID > - < pin ID >, which indicates a pin of a certain number on the connector.

For the internal pins of the instrument, the syntax is:

INS < Instrument ID > < Pin type > < ID1> < ID2>

Wherein INS represents a pin inside the instrument; the instrument ID is a unique identifier for the instrument; the pin types can be divided into instrument Capabilities (CAP), instrument Resources (RES), matrix Modules (MTB) and common switch units (SWP); the ID1 can respectively represent the unique identification of the capability, resource, matrix model or switch unit according to the different pin types; ID2 represents the port identification of the object represented by ID 1.

For example, for the present embodiment, a test station route map may be obtained as follows:

"TS::ATE1::J1-1":["INS::S1::A1-1"]

"TS::ATE1::J1-2":["INS::SA1::OP1::B1-1"]

"TS::ATE1::J1-3":["INS::S1::A1-3"]

"TS::ATE1::J3-5":["INS::S1::A1-5"]

"TS::ATE1::J2-4":["INS::S1::A1-1","TS::ATE1::J2-8"]

"TS::ATE1::J2-5":["INS::S1::A1-4"]

"TS::ATE1::J2-8":["INS::SA1::OP1::B1-1","INS::SA1::OP2::B1-2","TS::ATE1::J2-4"]

"TS::ATE1::J3-1":["INS::MT1::RP0::X1-1","INS::MT1::RP2::X1-11"]

"TS::ATE1::J3-2":["INS::MT1::RP0::X1-2","INS::MT1::RP2::X1-12"]

"TS::ATE1::J3-3":["INS::MT1::RP1::X1-3","INS::MT1::RP3::X1-13"]

"TS::ATE1::J3-4":["INS::MT1::RP1::X1-4","INS::MT1::RP3::X1-14"]

"TS::ATE1::J3-5":["INS::MT1::CP2::X1-9"]

"TS::ATE1::J3-6":["INS::MT1::CP2::X1-10"]

"TS::ATE1::J3-7":["INS::DM1::C1-1","INS::MT1::CP3::X1-15"]

"TS::ATE1::J3-8":["INS::DM1::C1-2","INS::MT1::CP3::X1-16"]

"INS::S1::A1-1":["TS::ATE1::J1-1"]

"INS::S1::A1-2":["TS::ATE1::J2-4"]

"INS::SA1::OP1::B1-1":["TS::ATE1::J2-2"]

"INS::SA1::OP2::B1-2":["TS::ATE1::J2-8"]

"INS::S1::A1-3":["TS::ATE1::J1-3"]

"INS::S1::A1-5":["TS::ATE1::J3-5"]

"INS::S1::A1-4":["TS::ATE1::J2-5"]

"INS::MT1::RP0::X1-1":["TS::ATE1::J3-1"]

"INS::MT1::RP2::X1-11":["TS::ATE1::J3-1"]

"INS::MT1::RP0::X1-2":["TS::ATE1::J3-2"]

"INS::MT1::RP2::X1-12":["TS::ATE1::J3-2"]

"INS::MT1::RP1::X1-3":["TS::ATE1::J3-3"]

"INS::MT1::RP3::X1-13":["TS::ATE1::J3-3"]

"INS::MT1::RP1::X1-4":["TS::ATE1::J3-4"]

"INS::MT1::RP3::X1-14":["TS::ATE1::J3-4"]

"INS::MT1::CP2::X1-9":["TS::ATE1::J3-5"]

"INS::MT1::CP2::X1-10":["TS::ATE1::J3-6"]

"INS::DM1::C1-1":["TS::ATE1::J3-7"]

"INS::DM1::C1-2":["TS::ATE1::J3-8"]

"INS::MT1::CP3::X1-15":["TS::ATE1::J3-7"]

"INS::MT1::CP3::X1-16":["TS::ATE1::J3-8"]

part of the instrument routing map is as follows:

"INS::S1::A1-1":["INS*::S1::SWP::Swt1::COM"]

"INS::S1::A1-2":["INS*::S1::SWP::Swt1::PO1"]

"INS::S1::A1-3":["INS*::S1::SWP::Swt2::COM"]

"INS*::S1::SWP::Swt1::COM":["INS::S1::A1-1"]

"INS*::S1::SWP::Swt1::PO1":["INS::S1::A1-2"]

"INS*::S1::SWP::Swt2::COM":["INS::S1::A1-3"]

……

"INS*::SA1::CAP::C1::CP1":["INS*::SA1::RES::RES1::RP1"]

"INS*::SA1::CAP::C2::CP2":["INS*::SA1::RES::RES1::RP2"]

"INS*::SA1::RES::RES1::RP1":["INS::SA1::OP1","INS*::SA1::CAP::C1::CP1"]

"INS*::SA1::RES::RES1::RP2":["INS::SA1::OP2","INS*::SA1::CAP::C2::CP2"]

"INS*::DM1::CAP::C1::CP1":["INS*::DM1::RES::RES1::RP1"]

"INS*::DM1::RES::RES1::RP1":["INS::DM1::P1","INS*::DM1::CAP::C1::CP1"]

"INS::MT1::RP0::X1-1":["INS*::MT1::MTB::MtxB0::B0ROW0+"]

"INS::MT1::RP0::X1-2":["INS*::MT1::MTB::MtxB0::B0ROW0-"]

"INS::MT1::RP1::X1-3":["INS*::MT1::MTB::MtxB0::B0ROW1+"]

"INS::MT1::RP1::X1-4":["INS*::MT1::MTB::MtxB0::B0ROW1-"]

"INS::MT1::CP0::X1-5":["INS*::MT1::MTB::MtxB0::B0COL0+"]

"INS::MT1::CP0::X1-6":["INS*::MT1::MTB::MtxB0::B0COL0-"]

"INS*::MT1::MTB::MtxB0::B0ROW0+":["INS::MT1::RP0::X1-1"]

"INS*::MT1::MTB::MtxB0::B0ROW0-":["INS::MT1::RP0::X1-2"]

"INS*::MT1::MTB::MtxB0::B0ROW1+":["INS::MT1::RP1::X1-3"]

"INS*::MT1::MTB::MtxB0::B0ROW1-":["INS::MT1::RP1::X1-4"]

"INS*::MT1::MTB::MtxB0::B0COL0+":["INS::MT1::CP0::X1-5"]

"INS*::MT1::MTB::MtxB0::B0COL0-":["INS::MT1::CP0::X1-6"]

……

the UUT end routing map is as follows:

"UUT::UUT1::X1-1":["TS::ATE1::J1-1"]

"UUT::UUT1::X1-2":["TS::ATE1::J1-2"]

"UUT::UUT1::X1-3":["TS::ATE1::J1-3"]

"UUT::UUT1::X1-8":["TS::ATE1::J1-3"]

"UUT::UUT1::X1-9":["TS::ATE1::J3-6"]

the test station and the instrument routing map are bidirectional, the UUT end routing map is unidirectional, and only the connection information from the UUT interface to the test station interface is recorded.

Assuming that the capability C1 of the digital multimeter (DM1) in the embodiment can be used to measure the dc voltage value between two pins, the description of the capability according to the related ATML standards (IEEE 1671.2 and IEEE 1641) is as follows, indicating that the capability supports the measurement of dc voltages of 0V to 300V.

Assuming that the current test requirement is to measure the direct-current voltage between the UUT pins X1-8 and X1-9, after dynamic resource matching is performed according to the capability, the DM1 is used as a target instrument, and then a signal path from the two UUT pins to the capability C1 of the instrument needs to be searched, that is, the search starting point is the pins X1-8 and X1-9 of the UUT, and the ending point is the capability C1 of the DM 1.

Based on the DM1 related instrument routing map information, port CP1 of available capability C1 is connected to port RP1 of resource RES1, which in turn is connected to external port P1 of DM1, with two pins C1-1 and C1-2 on P1, the problem translates into searching for a signal path from pins X1-8 and X1-9 of the UUT to pins C1-1 and C1-2 of DM1, respectively.

Take X1-8 pin of UUT as an example, and take it as a search starting point to perform recursive depth-first search.

First, if this pin appears in the UUT end routing map, the teststation pin to which it is connected can be obtained as J1-3 of ATE 1.

Then, starting from J1-3, the test station route map is searched for additional pins to connect to, which are A1-3 of power switch S1.

Then, according to the instrument routing map, the COM end of the switch unit Swt2 corresponding to the pin can be obtained, and then, further, through the ATML description model of the switch, it can be known that the switch unit has two ports PO1 and PO2 which can be outlets, and these two ports are sequentially selected as new starting points to perform depth-first search until the C1-1 pin of the DM1 is encountered as an end point.

The processing in the matrix is similar to the power switch described above, and when the new starting point is one pin of the matrix, the other pins can be used as the secondary starting point pins to perform depth-first traversal.

Finally, the historical path information may be obtained as follows:

UUT::UUT1::X1-8

TS::ATE1::J1-3

INS::S1::A1-3

INS*::S1::SWP::Swt2::COM

INS*::S1::SWP::Swt2::PO1

INS*::S1::SWP::Swt3::COM

INS*::S1::SWP::Swt3::PO1

INS::S1::A1-4

TS::ATE1::J2-5

INS*::S1::SWP::Swt2::PO2

INS::S1::A1-5

TS::ATE1::J3-5

INS::MT1::CP2::X1-9

INS::MT1

INS::MT1::RP0::X1-1

TS::ATE1::J3-1

INS::MT1::RP2::X1-11

INS::MT1::RP1::X1-3

TS::ATE1::J3-3

INS::MT1::RP3::X1-13

INS::MT1::CP0::X1-5

INS::MT1::CP1::X1-7

INS::MT1::CP3::X1-15

TS::ATE1::J3-7

INS::DM1::C1-1

the effective path information is:

INS::DM1::C1-1

TS::ATE1::J3-7

INS::MT1::CP3::X1-15

INS::MT1::CP2::X1-9

TS::ATE1::J3-5

INS::S1::A1-5

INS*::S1::SWP::Swt2::PO2

INS*::S1::SWP::Swt2::COM

INS::S1::A1-3

TS::ATE1::J1-3

UUT::UUT1::X1-8

the valid path information is included in the history path information, and since recording is started only after the pin of the instrument as the search target is found, the order of the valid path information is opposite to that of the history path information, but the application is not affected.

Similarly, for the X1-9 pin of UUT and the C1-2 pin of DM1, the historical path information is as follows:

UUT::UUT1::X1-9

TS::ATE1::J3-6

INS::MT1::CP2::X1-10

INS::MT1

INS::MT1::RP0::X1-2

TS::ATE1::J3-2

INS::MT1::RP2::X1-12

INS::MT1::RP1::X1-4

TS::ATE1::J3-4

INS::MT1::RP3::X1-14

INS::MT1::CP0::X1-6

INS::MT1::CP1::X1-8

INS::MT1::CP3::X1-16

TS::ATE1::J3-8

INS::DM1::C1-2

the effective path information is:

INS::DM1::C1-2

TS::ATE1::J3-8

INS::MT1::CP3::X1-16

INS::MT1::CP2::X1-10

TS::ATE1::J3-6

UUT::UUT1::X1-9

considering the ratio of the number of nodes in the effective path information to the number of nodes in the historical path information, the efficiency of the signal routing method is reflected, and it can be seen from the above embodiment that the invention can quickly and effectively complete the signal routing work in the complex test system.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims

1. A signal routing method of an automatic test system based on ATML is characterized by comprising two stages of route map construction and signal route searching.

2. The ATML-based signal routing method for an automatic test system according to claim 1, wherein the route map construction phase comprises the specific steps of:

3. The ATML-based signal routing method for an automatic test system according to claim 1, wherein the signal route search stage comprises the specific steps of:

4. The method of claim 2, wherein the Interface information is described in an < Interface > tag containing definitions of ports, connectors and pins of the test station; the connection information is described in a < NetworkList > tag, wherein the tag comprises two connected nodes, and each node adopts XPath syntax to describe a port or a pin from the current test station or an interface of one instrument instance;

the test station routing map is a dictionary data structure, the keys of the dictionary are represented by a formatted character string of each node appearing in the < NetworkList > tag of the test station, and the values of the dictionary are the formatted character string lists of all nodes connected with the current node obtained after analysis and combination.

5. The ATML-based automatic test system signal routing method of claim 2 wherein the instrument instance is contained in a < Instruments > tag of the test station description including the ID of the instrument, the referenced instrument description model identification and the address of the instrument;

the instrument routing map has a dictionary data structure similar to that of the test station routing map, and the contents of the dictionary data structure are the connection relation between the external port and the resource port of the instrument contained in the instrument description < NetworkList > tag and the mapping relation between the resource port and the capability port contained in the < capability map > tag.

6. The signal routing method for automatic test system based on ATML of claim 2, wherein the nodes in the netlist between the instance interfaces representing the ports or pins with connection relationships on the different model instance interfaces are described in the < WireList > tag where the XML file conforms to the WireList.

The UUT end routing map has a dictionary data structure similar to the test station routing map, the content of the UUT end routing map is a one-way connection relation from a UUT port or a pin to a test station port or a pin, the connection relation of a cable/an adapter serving as an intermediate level is ignored, and algorithm execution efficiency is improved.

7. The ATML-based automatic test system signal routing method of claim 3, wherein the end-to-instrument capability is based on IEEE1671.2 and IEEE1641 standards describing capabilities representing instrument-owned signal generation or measurement, including signal type and range, uncertainty and resolution of signal attributes, and in signal-oriented testing, instrument capability is used to match signal test requirements on UUT pins as a search starting point;

the number of the instrument resources is consistent with that of signal generation or measurement channels of the instrument, one-to-many relation exists between the instrument capacity and the instrument resources, and when the instrument channels corresponding to the resources are occupied, the current resources are unavailable.

8. The signal routing method of ATML-based automatic test system of claim 3 wherein the recursive depth-first search is started from a UUT pin as a search starting point, secondary pin information connected to the pin is queried in each routing map, and then the search process is recursively executed with the secondary pins as new search starting points until a search termination condition is reached;

9. The signal routing method for the ATML-based automatic test system of claim 8, wherein in the recursive depth-first search process, when an instrument of a common switch type is encountered, the instrument is searched for the inside first through an interface of the instrument, and when a switch is encountered, all reachable pins at the other end of the switch are used as secondary pins to continue the recursive search; when a matrix switch type instrument is encountered, searching the interior through an interface of the instrument, and when a matrix switch module is encountered, continuing to perform recursive search by taking all other available pins on a module row and column as secondary pins; history path information is recorded, and history paths are avoided when new paths are searched, so that repeated searching and endless loop are prevented.

10. The method as claimed in claim 3, wherein the path information from the UUT pin to the instrument pin is composed of all pins passing through the signal routing search process, and is a valid path when the instrument pin is included as an end point in the pins.