CN106526460A - Circuit fault locating method and device - Google Patents
Circuit fault locating method and device Download PDFInfo
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- CN106526460A CN106526460A CN201611247451.0A CN201611247451A CN106526460A CN 106526460 A CN106526460 A CN 106526460A CN 201611247451 A CN201611247451 A CN 201611247451A CN 106526460 A CN106526460 A CN 106526460A
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- 238000000034 method Methods 0.000 claims abstract description 109
- 230000005284 excitation Effects 0.000 claims abstract description 81
- 238000003745 diagnosis Methods 0.000 claims abstract description 29
- 238000004458 analytical method Methods 0.000 claims abstract description 11
- 230000000875 corresponding Effects 0.000 claims abstract description 7
- 238000004088 simulation Methods 0.000 claims abstract description 6
- 238000011068 load Methods 0.000 claims description 25
- 230000004807 localization Effects 0.000 claims description 16
- 230000005611 electricity Effects 0.000 claims description 8
- 239000000523 sample Substances 0.000 claims description 8
- 239000000284 extract Substances 0.000 claims description 4
- 230000003068 static Effects 0.000 claims description 4
- 238000000605 extraction Methods 0.000 claims 1
- 230000002452 interceptive Effects 0.000 abstract 1
- 239000000203 mixture Substances 0.000 description 5
- 230000000903 blocking Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005457 optimization Methods 0.000 description 3
- 241000208340 Araliaceae Species 0.000 description 2
- 241000287532 Colaptes Species 0.000 description 2
- 235000003140 Panax quinquefolius Nutrition 0.000 description 2
- 235000005035 ginseng Nutrition 0.000 description 2
- 235000008434 ginseng Nutrition 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
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- 238000002955 isolation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000031068 symbiosis, encompassing mutualism through parasitism Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2836—Fault-finding or characterising
- G01R31/2843—In-circuit-testing
Abstract
The invention provides a circuit fault locating method and device. The circuit fault locating method comprises the steps that the input is analog circuit test interactive format files and test routing files constructed based on simulation data under the normal and fault state of the circuit and a circuit network; the files are analyzed so that test excitation, test nodes, instrument mapping, test routing, test criteria and other information required by circuit testing and fault diagnosis are acquired; and files including the test process are generated according to the information acquired by analysis, and testing and fault locating of a circuit board can be realized by performing the process files. With application of the method and the device, the technical problems that the workload is large, the degree of automation is low, the number and the distribution of the test nodes are insufficiently optimized and the topology logic is low due to the fact that the existing technical scheme mainly depends on artificial inputting the corresponding test node information and determining the test sequence of the nodes can be solved.
Description
Technical field
The present invention relates to circuit test and fault diagnosis field, more particularly to a kind of fault localization method and device.
Background technology
With developing rapidly for electronic technology, circuit test diagnosis is particularly analog circuit fault diagnosing and becomes increasingly complex.
Circuit board needs to measure the data of intermediate node collection in fault location, carries out circuit state according to measurement result
Judge and analyze the Test Strategy for being inferred to next step；At present in board failure positioning, depend on and be manually entered phase
The test node information answered the testing sequence for determining node, so as to cause, workload is big, automaticity is not high, and causes
The quantity of the test node and distribution not enough not strong problem of optimization, topological logic.
The content of the invention
It is an object of the present invention to when being to solve using manual testing's circuit node information, have that workload is big, automation
Degree is not high, and causes the quantity and the distribution not enough not strong problem of optimization, topological logic of test node, there is provided a kind of
Board failure localization method and device.
Described fault localization method, its input be based on circuit normally with malfunction under emulation data and electricity
The analog circuit test exchange format file that road network builds is (referred to as：ATIF) and test routing file；Above-mentioned file is carried out
Parsing, is obtained circuit test and is sentenced with the test and excitation needed for fault diagnosis, test node, instrument mapping, test route and test
According to etc. information；The information according to acquired in parsing, generates test program, and by performing test program, realizes the survey to circuit board
Examination and fault location.
For achieving the above object, a kind of fault localization method that the present invention is provided, the method are comprised the steps of：
Step 1) import analog circuit test exchange format file and test routing file, and parse acquisition circuit test with
The mapping of test and excitation, test node, instrument, test route and test criteria information needed for fault diagnosis, parses the number for finishing
According to being stored in database；Described analog circuit test exchange format file using circuit normally with malfunction under emulation
Data and circuit network are built-up, describe the status information during analog circuit test, and described test routing file is retouched
State the input of tester, the connection relation information between output channel and circuit-under-test test node.
Step 2) configuration to power channel and its parameter is completed according to parsing data, generate comprising test and excitation operation stream
The file of journey, the parameter and input, output channel of configuration testing instrument, generates the file comprising test operation flow process；
Step 3) execution step 2) in generate the file comprising test and excitation operating process, comprising test operation flow process
File, controls tester and realizes test and fault location to circuit-under-test plate.This method has been applied to analog circuit event
In barrier diagnosis, and show superior performance.
As the further improvement of above-mentioned technical proposal, described step 2) include：
Step 201) extract analog circuit test exchange format file in test and excitation and test node information, and survey
The connection relation information between power channel and circuit node in examination routing file, completes to match somebody with somebody power channel and its parameter
Put, generate test and excitation operating process；
Step 202) the test operation flow process of each module in circuit-under-test is generated, described test operation flow process includes circuit
Test operation flow process and fault diagnosis operating process, described circuit testing operation flow process are used to judge each module as normal or event
Barrier state, and fault diagnosis operating process is performed by the module to malfunction, obtained for failure judgement type with gathering
Response data；
Step 203) by step 201) in test and excitation operating process, step 202) in circuit testing operation flow process and
Fault diagnosis operating process is respectively written into the flow file specified.
Used as the further improvement of above-mentioned technical proposal, the generation step of described circuit testing operation flow process is：Foundation
The test route letter extracted in the test and excitation information extracted in analog circuit test exchange format file, test routing file
Breath, the parameter and input channel of configuration testing instrument；According to the response message extracted in analog circuit test exchange format file
With the test routing iinformation extracted in test routing file, the parameter and output channel of configuration testing instrument；Described failure is examined
The generation step of disconnected operating process is：According to the excitation information, test route that extract in analog circuit test exchange format file
The routing iinformation extracted in file, the parameter and input channel of configuration testing instrument；According to analog circuit test exchange format text
The information for needing acquisition node, the parameter and output channel of configuration testing instrument, and the configuration dialog box are extracted in part, test is pointed out
Node and probe pen type, the PCB scintillation parameters of configuration output test node.
As the further improvement of above-mentioned technical proposal, the step 1) in analog circuit test exchange format file bag
Include：Header file, UUT file groups, exciter response file group and fault knowledge file group；
The version number of described header file storage fault dictionary, the generation time of fault dictionary, the number of fault dictionary file
Amount, numbering and grouping information；
Described UUT file groups include：Net meter file, circuit unit file, input node file, output node file,
Can not test pin file, pin node mapped file and node map pins file, the respectively netlist letter of storage emulation circuit
Breath, circuit assembly information, input node information, output node information, can not test pin information, pin correspondence reflecting to node
Penetrate information, the map information of node correspondence to pin；
Described exciter response file group includes：Excitation types file, excitation property file, quiescent point response file
With steady-state response file, quiescent point response letter when excitation types information, excitation attribute information, functional simulation is stored respectively
Breath, steady-state response information；
Described fault knowledge file group includes：Failure numbering file, quiescent point fault set file, steady state fault collection
File, untestable fault collection file, fuzzy set schema file, quiescent point fuzzy set file, stable state fuzzy set file, static state
Operating point fault dictionary file, steady state fault dictionary file and homomorphism failure file, store failure numbering, quiescent point respectively
Failure name information, steady state fault name information, untestable fault information, fuzzy set pattern information, quiescent point fuzzy set
Information, stable state fuzzy set information, quiescent point fault dictionary information, steady state fault dictionary information, homomorphism fault message.
As the further improvement of above-mentioned technical proposal, the step 1) in test routing file include：Input pin
Information, output pin information, excitation mapping and response mapping；
If it is determined that pin is excitation loading pin, then input pin is defined as, if it is decided that pin draws for response loading
Pin, then be defined as output pin；
Described excitation mapping to be represented and load excitation tester input used, output channel according to input pin；Institute
The response mapping stated to be represented and set up tester input, output channel and circuit-under-test connector output pin according to output pin
Connection.
As the further improvement of above-mentioned technical proposal, described step 3) include：
Step 301) load step 201) in the file comprising test and excitation operating process that generates, by power channel and its
The configuration of parameter is delivered in power supply, control power supply output；
Step 302) according to step 203) the middle file comprising circuit testing operation flow process for generating, in circuit-under-test one
The individual module loading test and excitation do not tested, the parameter and input channel of configuration testing instrument realize excitation output；
Step 303) according to step 203) the middle file comprising circuit testing operation flow process for generating, to step 302) in
Module loading test response, the parameter and output channel of configuration testing instrument realize response collection；It is sequentially completed and adopts
After the response of collection, according to the response data criterion that exciter response file group in analog circuit test exchange format file is parsed,
Judge the module for obtaining current test for normal condition or malfunction；
Step 304) if step 303) in the module of test be normal condition, output module normal state information is right
One module do not tested re-executes step 302)；If step 303) in test module be malfunction, according to step
Rapid 203) the middle file comprising fault diagnosis operating process for generating, to module loading test and excitation, the ginseng of configuration testing instrument
Number and input channel, realize excitation output；
Step 305) according to step 203) in generate the file comprising fault diagnosis operating process, to step 304) in plus
The module loading test response after test and excitation is carried, probe pen and the connection of tested node is completed according to prompting, is clicked in dialog box
Continue executing with after, complete the configuration and control of tester, realize response collection；Being sequentially completed all needs the response of collection
Afterwards, execution step is 306)；
Step 306) to step 305) in collection all response messages according in analog circuit test exchange format files
Fuzzy set schema file carry out type matching, after matching obtains fuzzy integrated mode, with the fuzzy set in fuzzy set file
Match somebody with somebody, if judging that all response messages have matched fuzzy set scope, show that malfunction is what matching was obtained
The corresponding failure of fuzzy set.
As the further improvement of above-mentioned technical proposal, including：Document analysis module, testing process generation module, test
Flow executing modules and tester；
Described document analysis module：For importing analog circuit test exchange format file and test routing file, and
Parsing obtains circuit test with the test and excitation needed for fault diagnosis, test node, instrument mapping, test route and test criteria
Information；Described analog circuit test exchange format file using circuit normally with malfunction under emulation data and circuit network
Network is built-up, describes the status information during analog circuit test, and it is defeated that described test routing file describes tester
Enter, the link information between output channel and circuit-under-test test node；
Described testing process generation module：For parsing the information for obtaining according to document analysis module, complete to power supply
The configuration of passage and its parameter, generates the file comprising test and excitation operating process, the parameter of configuration testing instrument and input, defeated
Go out passage, generate the file comprising test operation flow process；
Testing process performing module：For perform generate in testing process generation module comprising test and excitation operating process
File, the file comprising test operation flow process, control tester and realize test and fault location to circuit.
The present invention a kind of fault localization method and device advantage be：
The device and method provided using the present invention, can realize that the fault based on circuit networking and graph search is fixed
, the functions such as test is imported, test is parsed, testing process file is automatically generated and is performed are realized, prior art is solved
The testing sequence for being manually entered corresponding test node information and determining node is depended on, the caused workload of institute is greatly, certainly
Dynamicization degree is not high and causes the quantity of the test node and distribution not enough not strong technical problem of optimization, topological logic.
Description of the drawings
Fig. 1 is a kind of fault localization method flow chart that the present invention is provided.
Fig. 2 is the ATIF files composition frame diagram in the present invention.
Fig. 3 is the test operation automatic process generating schematic diagram in the embodiment of the present invention.
Fig. 4 is that the test operation flow process in the embodiment of the present invention performs schematic diagram.
Specific embodiment
With reference to the accompanying drawings and examples a kind of fault localization method of the present invention and device are carried out in detail
Explanation.
As shown in figure 1, a kind of fault localization method that the present invention is provided, the method includes：
Step 1) import analog circuit test exchange format file and test routing file, and parse acquisition circuit test with
The mapping of test and excitation, test node, instrument, test route and test criteria information needed for fault diagnosis；Described simulation electricity
Drive test examination exchange format file using circuit normally with malfunction under emulation data and circuit network it is built-up, mould is described
Intend circuit testing procedures in status information, described test routing file describe tester input, output channel with it is tested
Link information between circuit test node；
Step 2) according to step 1) information for obtaining is parsed, the configuration to power channel and its parameter is completed, is automatically generated
File comprising test and excitation operating process, the parameter and input, output channel of configuration testing instrument, generates comprising test operation
The file of flow process；
Step 3) execution step 2) in generate the file comprising test and excitation operating process, comprising test operation flow process
File, controls tester and realizes test and fault location to circuit.
As shown in Fig. 2 the step 1) in analog circuit test exchange format file include：Header file, UUT files
Group, exciter response file group, fault knowledge file group composition；
The version number of described header file storage fault dictionary, the number for generating time and fault dictionary file of fault dictionary
Amount, numbering and grouping information；
Described UUT files group by net meter file, circuit unit file, input node file, output node file, can not
Test pin file, pin node mapped file, 7 file compositions of node map pins file, store institute's artificial circuit respectively
Netlist information, circuit assembly information, input and output node information, can not test pin information, pin it is corresponding to node
The map information of map information, node correspondence to pin；
Described exciter response file group is by excitation types file, excitation property file, quiescent point response file, steady
4 file compositions of state response file, store quiescent operation when excitation types information, excitation attribute information and functional simulation respectively
Point response message, steady-state response information；
Described fault knowledge file group is by failure numbering file, quiescent point fault set file, steady state fault collection text
Part, untestable fault collection file, fuzzy set schema file, quiescent point fuzzy set file, stable state fuzzy set file, static work
Make point failure dictionary file, steady state fault dictionary file, 10 files of homomorphism failure file composition, store respectively failure numbering,
Quiescent operation point failure name information, steady state fault name information, untestable fault information, fuzzy set pattern information, static work
Make point fuzziness collection information, stable state fuzzy set information, quiescent point fault dictionary information, steady state fault dictionary information, homomorphism event
Barrier information.
By above-mentioned ATIF document analysis data storage in database, as the number that follow-up test flow file is automatically generated
According to source.The information parsed in the information stored in database and ATIF files is completely the same, respectively with ATIF files in UUT
File group, exciter response file group, fault knowledge file group correspondence.
Test routing file describes the link information of tester and test point.By parsing test routing file,
Obtain being described as follows for parsing information：
Input/output pinout information：If it is determined that pin is excitation loading pin, then input pin is defined as, if sentenced
Determine pin and pin is loaded for response, then be defined as output pin；
Excitation/response mapping：Described excitation mapping is represented to be loaded according to input pin and encourages tester used defeated
Enter, output channel；Described response mapping to be represented and set up tester input, output channel and circuit-under-test according to output pin
Connector output pin connects；
Above-mentioned test routing file parsing information is stored in database, is automatically generated as follow-up test flow file
Data source.
In testing process generating process, it is necessary first to automatically generate excitation；Then blocking information (the test according to circuit
In advance circuit board is constituted according to its function in routing file, circuit board is divided into into the module of several function opposite independents), point
The test operation flow process of each circuit module is not generated.
In the present embodiment, described step 2) in specifically include comprising the file generated process of test operation flow process：
Step 201) in test and excitation operating process generating process, according to the blocking information of circuit, such as circuit board presses work(
Energy Module Division is 5 modules, then the test and excitation operating process symbiosis for generating is into 7 parts；Part I is used to control electricity
The operation of source load-on module；2-6 parts are used for the operation for controlling 5 functional modules；7th part control power-off module
Operation；Test and excitation and test node information in ATIF files are extracted with power supply load-on module, is carried from test routing file
Connection relation information between the power channel for taking and circuit node, completes the configuration to power channel and its parameter, realizes electricity
The loading of source forcing, and power-off is always maintained at, so as to realize automatically generating test and excitation operating process.Terminating test
Afterwards, shutoff operation is arranged to the respective channel of power supply by power-off module, to terminate test operation.By above-mentioned configuration information
Store into test TP files.
Step 202) according to the blocking information of circuit, the testing process of each circuit module is generated respectively；Each circuit mould
The test of block includes circuit testing operation flow process and fault diagnosis operating process two parts.Described circuit testing operation flow process is used
In each module being judged as normal or malfunction, and fault diagnosis operating process is performed by the module to malfunction, to adopt
Collection obtains the response data for failure judgement type.By taking any one in 5 circuit modules as an example, described circuit test
The generation step of operating process is：According to what is extracted in the test and excitation information, test routing file extracted from ATIF files
Test routing iinformation, the parameter and input channel of configuration testing instrument；Secondly according to the response message extracted from ATIF files,
The test routing iinformation extracted in test routing file, the parameter and output channel of configuration testing instrument；By the letter of above-mentioned generation
Breath saves as TP；The generation step of described fault diagnosis operating process is：Collection section is needed according to extracting from ATIF files
The routing iinformation that extracts in the excitation information of point, test routing file, the parameter and input channel of configuration testing instrument, foundation
The information for needing acquisition node, the parameter and output channel of configuration testing instrument, and the configuration dialog box are extracted in ATIF files, is carried
Show test node and probe pen type, configuration exports the PCB scintillation parameters of the node；The information of above-mentioned generation is preserved into into TP literary
Part.
Described fault diagnosis operating process is provided with PCB flickers and dialog box prompting operation, and the position sensing of flicker is current
Measured point or tested components and parts, and the probe pen type that needed by the current test of dialog box prompting and measured point, test when
Wait the position of the test point that prompting needs to perform current test.
Described step 3) in specifically include comprising the file implementation procedure of test operation flow process：
Step 301) load step 201) in generate the file comprising test and excitation operating process, specially：According to electricity
Load-on module corresponding test and excitation flow process in source performs power supply loading operation；Upon execution, by the driving of software transfer power supply
Function, the passage and its configuration parameter of power supply are delivered in power supply, control power supply output；
Step 302) according to step 202) the middle file comprising circuit testing operation flow process for generating, in circuit-under-test one
The individual module loading test and excitation do not tested, and complete the parameter of tester, input channel configuration and control, realize that excitation is defeated
Go out；
Step 303) according to step 202) the middle file comprising circuit testing operation flow process for generating, to step 302) in
Module loading test response, and complete the parameter of tester, output channel configuration and control, realize response collection；It is complete successively
The responses of collection, and the response data criterion parsed according to the exciter response file group from ATIF files are needed into whole,
Judge to obtain the module of current test in circuit for normal condition or malfunction；
Step 304) if step 303) in test functions of modules it is normal, carry out next step functional test, i.e., under
One module do not tested re-executes step 302)；If step 303) in test functions of modules it is abnormal, according to step
Rapid 202) the middle file comprising fault diagnosis operating process for generating is tested again to the module, and module loading test is swashed
Encourage, the parameter and input channel of configuration testing instrument, realize excitation output, until realizing fault location；
Step 305) according to step 202) in generate the file comprising fault diagnosis operating process, to step 304) in plus
The module loading test response after test and excitation is carried, probe pen and the connection of tested node is completed according to prompting, is clicked in dialog box
Continue executing with after, complete the configuration and control of instrument, realize response collection；The information of collection is all stored；Wait to need entirely
After the completion of the information gathering of portion's collection, execution step is 306)；
Step 306) to step 305) in collection each response message according to the fuzzy set schema file in ATIF files
Type matching is carried out, after matching obtains fuzzy integrated mode, is matched with the fuzzy set in fuzzy set file, is judged gathered information
Whether in the range of the fuzzy set for being matched, and after being sequentially completed the judgement of whole response messages, draw judged result：If complete
When portion's response message is in the range of same or certain several matched fuzzy set, then show that current circuit state is the mould
Paste collection or the corresponding failure of certain several fuzzy set.
Described fuzzy set schema file is directed to different waveforms, and the fuzzy set type of the waveform is depicted；With sine wave
As a example by signal, its fuzzy integrated mode is included：Upper amplitude limit, amplitude lower limit, upper frequency limit, lower-frequency limit, the biasing upper limit and biasing
Lower limit.
Described fuzzy set file is directed to the different state of circuit, according to test node signal type in this condition,
According to fuzzy set schema file, the fuzzy set of each test node under every kind of state is described, such as certain test node is sinusoidal letter
Number, then its fuzzy set is expressed as under certain state：0.5 1,1,000 1005,0.25 0.3.
Embodiment one
With reference to shown in Fig. 3, in the present embodiment, testing process is carried out using foregoing circuit Fault Locating Method and automatically generated
Process comprise the steps：
First, test and excitation is generated；According to excitation routing iinformation, complete operate software automatically generate control and encourage from
It is dynamic to generate；
Secondly, according to test output pin, the signal attribute and routing iinformation of the pin is retrieved, circuit testing operation is realized
Flow process is generated, including：Operation software automatically generates control, route closure generation, Self -adaptive and route and disconnects and generating；Wherein,
Self -adaptive refers to the configuration of tester；
Finally, according to tested pin, the signal attribute of the pin is retrieved, realizes that fault diagnosis operating process is generated, bag
Include：Test pin information configuration and PCB flash for prompting are generated；Wherein, test pin information configuration is included：Test prompts information,
Tester is configured.
With reference to shown in Fig. 4, in the present embodiment, the mistake of testing process execution is carried out using foregoing circuit Fault Locating Method
Journey comprises the steps：
First, test and excitation applying is carried out by test and excitation operating process；
Then, the n circuit module to dividing performs test operation；By to the automatic test of circuit module, detecting the electricity
Road module whether there is failure；If fault-free, next circuit module is tested automatically, until whole circuit modules are completed；
If circuit module has failure, into the fault diagnosis operating process of the circuit module, flash and talk with by PCB nodes
Frame information alert, carries out probe pen test, and by the test to all test nodes of the circuit module, realizes Fault Isolation；Such as
The whole test points of fruit are completed, it is impossible to determine failure, then need to regenerate and optimize ATIF files, continue executing with above-mentioned step
Suddenly.
In addition, being based on foregoing circuit Fault Locating Method, the present invention also provides a kind of fault positioner simultaneously,
Including：Document analysis module, testing process generation module, testing process performing module and tester；
Described document analysis module：For importing analog circuit test exchange format file and test routing file, and
Parsing obtains circuit test with the test and excitation needed for fault diagnosis, test node, instrument mapping, test route and test criteria
Information；Described analog circuit test exchange format file using circuit normally with malfunction under emulation data and circuit network
Network is built-up, describe analog circuit test during status information, described routing file describe tester input, it is defeated
The link information gone out between passage and circuit-under-test test node；
Described testing process generation module：For parsing the information for obtaining according to document analysis module, complete to power supply
The configuration of passage and its parameter, automatically generates the file comprising test and excitation operating process, the parameter of configuration testing instrument and defeated
Enter, output channel, generate comprising test operation flow process file；
Testing process performing module：For perform generate in testing process generation module comprising test and excitation operating process
File, the file comprising test operation flow process, control tester and realize test and fault location to circuit.
It should be noted last that, above example is only to illustrate technical scheme and unrestricted.Although ginseng
The present invention is described in detail according to embodiment, it will be understood by those within the art that, the technical side to the present invention
Case is modified or equivalent, and without departure from the spirit and scope of technical solution of the present invention, which all should be covered in the present invention
Right in the middle of.
Claims (7)
1. a kind of fault localization method, it is characterised in that include：
Step 1) analog circuit test exchange format file and test routing file are imported, and parse acquisition circuit test and failure
Test and excitation, test node, instrument mapping, test route and test criteria information needed for diagnosis；Described analog circuit is surveyed
Examination exchange format file using circuit normally with malfunction under emulation data and circuit network it is built-up, description simulation electricity
Status information during drive test examination, described test routing file describe tester input, output channel and circuit-under-test
Link information between test node；
Step 2) according to step 1) information for obtaining is parsed, the configuration to power channel and its parameter is completed, is generated comprising test
The file of excitation operating process, the parameter and input, output channel of configuration testing instrument, generates the text comprising test operation flow process
Part；
Step 3) execution step 2) in generate the file comprising test and excitation operating process, the text comprising test operation flow process
Part, controls tester and realizes test and fault location to circuit.
2. fault localization method according to claim 1, it is characterised in that described step 2) include：
Step 201) extract analog circuit test exchange format file in test and excitation and test node information, and test road
By the connection relation information between the power channel and circuit node in file, the configuration to power channel and its parameter is completed,
Generate test and excitation operating process；
Step 202) the test operation flow process of each module in circuit-under-test is generated, described test operation flow process includes circuit test
Operating process and fault diagnosis operating process, described circuit testing operation flow process are used to judge each module as normal or failure shape
State, and fault diagnosis operating process is performed by the module to malfunction, to gather the sound obtained for failure judgement type
Answer data；
Step 203) by step 201) in test and excitation operating process, step 202) in circuit testing operation flow process and failure
Diagnostic operation flow process is respectively written into the flow file specified.
3. fault localization method according to claim 2, it is characterised in that described circuit testing operation flow process
Generation step is：According to carrying in the test and excitation information, test routing file extracted in analog circuit test exchange format file
The test routing iinformation for taking, the parameter and input channel of configuration testing instrument；According in analog circuit test exchange format file
The test routing iinformation extracted in the response message and test routing file of extraction, the parameter of configuration testing instrument and output are led to
Road；The generation step of described fault diagnosis operating process is：According to swashing for extracting in analog circuit test exchange format file
The routing iinformation extracted in encouraging information, test routing file, the parameter and input channel of configuration testing instrument；According to analog circuit
The information for needing acquisition node, the parameter and output channel of configuration testing instrument are extracted in test exchange format file, and is configured
Dialog box, points out test node and probe pen type, the PCB scintillation parameters of configuration output test node.
4. fault localization method according to claim 3, it is characterised in that the step 1) in analog circuit survey
Examination exchange format file includes：Header file, UUT file groups, exciter response file group and fault knowledge file group；
The version number of described header file storage fault dictionary, the generation time of fault dictionary, the quantity of fault dictionary file, volume
Number and grouping information；
Described UUT file groups include：Net meter file, circuit unit file, input node file, output node file, can not
Test pin file, pin node mapped file and node map pins file, the netlist information of difference storage emulation circuit, electricity
Road module information, input node information, output node information, can not test pin information, pin correspondence to node mapping believe
The map information of breath, node correspondence to pin；
Described exciter response file group includes：Excitation types file, excitation property file, quiescent point response file and steady
State response file, respectively store excitation types information, excitation attribute information, functional simulation when quiescent point response message,
Steady-state response information；
Described fault knowledge file group includes：Failure numbering file, quiescent point fault set file, steady state fault collection text
Part, untestable fault collection file, fuzzy set schema file, quiescent point fuzzy set file, stable state fuzzy set file, static work
Make point failure dictionary file, steady state fault dictionary file and homomorphism failure file, store failure numbering, quiescent point event respectively
Barrier name information, steady state fault name information, untestable fault information, fuzzy set pattern information, quiescent point fuzzy set letter
Breath, stable state fuzzy set information, quiescent point fault dictionary information, steady state fault dictionary information, homomorphism fault message.
5. fault localization method according to claim 3, it is characterised in that the step 1) in test route text
Part includes：Input pin information, output pin information, excitation mapping and response mapping；
If it is determined that pin is excitation loading pin, then input pin is defined as, if it is decided that pin is response loading pin, then
It is defined as output pin；
Described excitation mapping to be represented and load excitation tester input used, output channel according to input pin；Described
Response mapping represents that setting up tester input, output channel and circuit-under-test connector output pin according to output pin connects
Connect.
6. fault localization method according to claim 4, it is characterised in that described step 3) include：
Step 301) load step 201) in generate the file comprising test and excitation operating process, by power channel and its parameter
Configuration be delivered in power supply, control power supply output；
Step 302) according to step 203) the middle file comprising circuit testing operation flow process for generating, to one in circuit-under-test not
The module loading test and excitation of test, the parameter and input channel of configuration testing instrument realize excitation output；
Step 303) according to step 203) in generate the file comprising circuit testing operation flow process, to step 302) in module
Loading test response, the parameter and output channel of configuration testing instrument realize response collection；It is sequentially completed
After response, according to the response data criterion that exciter response file group in analog circuit test exchange format file is parsed, judge
The module for obtaining current test is normal condition or malfunction；
Step 304) if step 303) in test module be normal condition, output module normal state information, to
The module do not tested re-executes step 302)；If step 303) in test module be malfunction, according to step
203) file comprising fault diagnosis operating process generated in, to module loading test and excitation, the parameter of configuration testing instrument
And input channel, realize excitation output；
Step 305) according to step 203) the middle file comprising fault diagnosis operating process for generating, to step 304) middle loading survey
Module loading test response after examination excitation, completes probe pen and the connection of tested node according to prompting, click in dialog box after
After continuous execution, the configuration and control of tester are completed, realize response collection；After being sequentially completed the response for all needing to gather,
Execution step is 306)；
Step 306) to step 305) in collection all response messages according to the mould in analog circuit test exchange format files
Paste integrated mode file carries out type matching, after matching obtains fuzzy integrated mode, matches with the fuzzy set in fuzzy set file, sentences
If all response messages of breaking have matched fuzzy set scope, show that malfunction is the fuzzy set that matching is obtained
Corresponding failure.
7. the fault positioner based on the fault localization method described in one of claim 1-6, it is characterised in that
Including：Document analysis module, testing process generation module, testing process performing module and tester；
Described document analysis module：For importing analog circuit test exchange format file and test routing file, and parse
Circuit test is obtained with the test and excitation needed for fault diagnosis, test node, instrument mapping, test route and test criteria letter
Breath；Described analog circuit test exchange format file using circuit normally with malfunction under emulation data and circuit network
It is built-up, describe analog circuit test during status information, described test routing file describe tester input,
Link information between output channel and circuit-under-test test node；
Described testing process generation module：For parsing the information for obtaining according to document analysis module, complete to power channel
And its configuration of parameter, the file comprising test and excitation operating process is generated, the parameter of configuration testing instrument is logical with input, output
Road, generates the file comprising test operation flow process；
Testing process performing module：For performing the text comprising test and excitation operating process generated in testing process generation module
Part, the file comprising test operation flow process, control tester and realize test and fault location to circuit.
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