CN114441927A - Multi-environment batch chip testing method - Google Patents
Multi-environment batch chip testing method Download PDFInfo
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- CN114441927A CN114441927A CN202011205199.3A CN202011205199A CN114441927A CN 114441927 A CN114441927 A CN 114441927A CN 202011205199 A CN202011205199 A CN 202011205199A CN 114441927 A CN114441927 A CN 114441927A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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- G01R31/2894—Aspects of quality control [QC]
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Abstract
The present disclosure relates to a multi-environment batch chip testing method. The method comprises the steps of 1, carrying out primary test on batch chips based on a first test environment, and acquiring grading information of the batch chips according to a primary test result; step 2, grading the batch chips according to the grading information, and grading the batch chips into first-grade chips to Nth-grade chips; and 3, selecting any one of the N chips, carrying out secondary test on the chip based on a second test environment, and obtaining the trimming target of the chip according to a secondary test result until the trimming target of each chip in the batch of chips is obtained. Based on the method disclosed by the disclosure, the trimming targets of different gears can be provided for the chips, and the batch production of high-precision chips can be realized.
Description
Technical Field
The invention relates to a chip testing method, in particular to a multi-environment batch chip testing method.
Background
At present, in the process of developing an integrated circuit chip, in order to ensure the yield of high-precision chip manufacturing, the chip needs to be tested for many times based on different environments before the chip is manufactured and shipped from a factory, and the test results of the chip in the different environments are calculated to obtain a final test result, so as to check whether the performance of the chip meets the high-precision requirement.
For example, in the production process of a temperature sensor chip, it is necessary that the detection chip outputs different voltages or currents corresponding to ambient temperatures at different ambient temperatures. In order to ensure that the measurement accuracy of the manufactured temperature sensor chip meets the requirement, it is necessary to realizeLinear relationship of output voltage to ambient temperature: v ═ kT + V0. Wherein V is the chip output voltage, T is the ambient temperature, V0To test the output voltage of a chip at a temperature of 0 ℃, k is the slope of the linear relationship between the output voltage and the ambient temperature, usually a constant coefficient. In chip testing, if the precision of k is to be realized, the test is required to be carried out in two different temperature environments. At a first temperature T1When the test result is V1. Then testing the chip in a second test temperature environment T2Test with a test result of V2. The final test value of k is k ═ V2-V1)/(T2-T1)。
However, with this test method, each chip is first subjected to a first temperature test, then to a second temperature test, and then the process is repeated for each next chip. Therefore, the test machine is required to be heated and cooled continuously during testing, the method not only puts high requirements on the test machine, but also requires long time for continuous heating and cooling, and the test method has long test time, low efficiency and large error during mass production testing.
Therefore, a testing method capable of performing multi-environment testing on a lot of chips in mass production testing is needed.
Disclosure of Invention
In order to solve the defects in the prior art, the invention aims to provide a multi-environment batch chip testing method, which can be used for grading batch chips in a primary test and providing different trimming references for the chips according to grading information in a secondary test.
The invention adopts the following technical scheme. A multi-environment batch chip testing method comprises the following steps: step 1, testing the batch chips for one time based on a first testing environment, and acquiring grading information of the batch chips according to a testing result for one time; step 2, grading the batch chips according to the grading information, and grading the batch chips into first-grade chips to Nth-grade chips; and 3, selecting any one of the N grades of chips, carrying out secondary test on the grade of chip based on a second test environment, and obtaining the trimming target of the grade of chip according to a secondary test result until the trimming target of each chip in the batch of chips is obtained.
Preferably, step 1 further comprises: step 1.1, predetermining the grading range of the batch chips according to one or more standard gear values; step 1.2, comparing the primary test result with one or more standard gear values; and step 1.3, determining the grading information of each chip in the batch of chips according to the comparison result.
Preferably, step 1 further comprises: the grading information of each chip is the average value of the maximum standard gear value and the minimum standard gear value of the gear where the chip is located.
Preferably, step 3 further comprises: step 3.1, obtaining a trimming target of each chip according to the grading information and the expected attribute value of each chip in the grading chip; and 3.2, comparing the secondary test result with the trimming target to obtain the trimming value of each chip in the grade of chip.
Preferably, the first test environment is a first test temperature T1The first test result is the first test temperature T1Output voltage V of lower chip1(ii) a The grading information of the batch of chips is according to the first test temperature T1Output voltage V of lower chip1The average value of the maximum standard gear value and the minimum standard gear value of the gear where the chip is located is obtained; the second test environment is a second test temperature T2The secondary test result is the second test temperature T2Output voltage V of lower chip2。
Preferably, the trimming target of each chip is k (T)2-T1)+(an+an+1) 2; wherein n is the gear of the chip, k is the expected attribute value corresponding to the gear of the chip, and anIs the minimum standard gear value of the gear of the chip, an+1The maximum standard gear value of the gear of the chip.
Preferably, the gear value a is based on a standard1、a2、a3、a4、a5Determining the output voltage range of the 4-gear qualified chip; wherein, the output voltage of the first-gear chip is in the range of (a)1,a2]The output voltage of the second-level chip is in the range of (a)2,a3]The output voltage of the third-gear chip is in the range of (a)3,a4]The output voltage of the fourth-gear chip is in the range of (a)4,a5](ii) a Wherein, the grading information of the first grade chip is (a)1+
a2) The grading information of the second grade chip is (a)2+a3) The grading information of the third grade chip is (a)3+a4) The grading information of the fourth grade chip is (a)4+a5)/2。
Compared with the prior art, the multi-environment batch chip testing method has the advantages that the batch chips are graded during primary testing, and different trimming references are provided for the chips according to grading information during secondary testing. And the chips are trimmed according to the trimming target, so that high-precision factory chips are provided in batches.
1. According to the invention, the batch of chips can be graded according to the primary test result, so that when the trimming target is generated by the secondary test, the trimming target can be changed according to different gears, and the yield is improved.
2. The invention can determine the trimming target generated in the secondary test based on the initial test performance of the chip in the test process, thereby ensuring the effectiveness of the two tests aiming at the same chip and realizing the test and trimming of chips in batches.
Drawings
FIG. 1 is a flow chart of a method of multi-environment batch chip testing according to the present invention;
FIG. 2 is a flowchart of the method of step 1 of the multi-environment batch chip testing method of the present invention;
FIG. 3 is a flowchart of step 3 of the method for testing multi-environment batch chips according to the present invention.
Detailed Description
The present application is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present application is not limited thereby.
FIG. 1 is a flowchart of a method for multi-environment batch chip testing according to the present invention. As shown in fig. 1, a multi-environment batch chip testing method includes steps 1 to 3.
Step 1, testing the batch chips for one time based on a first testing environment, and acquiring grading information of the batch chips according to a testing result for one time.
The method can be used for simultaneously testing a plurality of chips produced in batch on the same testing machine, can modulate the temperature of the testing machine to a first testing temperature, and can start to test the chips in batch when the temperature is determined to be constant.
Preferably, step 1 further comprises steps 11 to 13. FIG. 2 is a flowchart of step 1 of a multi-environment batch chip testing method according to the present invention. As shown in FIG. 2, a gear range for a batch of chips is predetermined based on one or more standard gear values, step 11. And step 12, comparing the test result with one or more standard gear values. And step 13, determining the grading information of each chip in the batch of chips according to the comparison result.
Preferably, the step information of each chip is an average value of a maximum standard gear value and a minimum standard gear value of the gear in which the chip is located.
In an embodiment of the disclosure, the chip for batch testing is a temperature sensor chip, and the first testing environment and the second testing environment are respectively a first testing temperature T1And a second test temperature T2. And the primary test result and the secondary test result are respectively the first test temperature T1And a second test temperature T2Output voltage V of lower chip1And an output voltage V2。
Preferably, the grading information of the batch of chips may be according to the first test temperature T1Output voltage V of lower chip1And obtaining the average value of the maximum standard gear value and the minimum standard gear value of the gear where the chip is located.
In one embodiment, a 4-stage pass chip may be provided, whenThe chip is at a first ambient temperature T1In the middle, the output voltage is less than a1Or greater than a5Will be identified as failing. When the output voltage of the chip is at a1And a5In between, the chips are considered to be qualified chips.
Preferably, the gear value a can be based on the standard gear value1、a2、a3、a4、a5And determining the output voltage range of the 4-gear qualified chip. The specific grading of the qualified chips is as follows: the output voltage of the first-gear chip is in the range of (a)1,a2]The output voltage of the second-level chip is in the range of (a)2,a3]The output voltage of the third-gear chip is in the range of (a)3,a4]The output voltage of the fourth-gear chip is in the range of (a)4,a5]. Wherein, the grading information of the first grade chip is (a)1+a2) The grading information of the second grade chip is (a)2+a3) The grading information of the third grade chip is (a)3+a4) The grading information of the fourth grade chip is (a)4+a5)/2。
And 2, grading the batch chips according to the grading information, and grading the batch chips into a first grade chip to an Nth grade chip.
According to the grading information in the step 1, the chip can be actually graded. For example, a manipulator on a testing machine is used to control the chip moving positions divided into different gears, and a second test is performed. Of course, other implementations are possible in the art.
And 3, selecting any one of the N grades of chips, carrying out secondary test on the grade of chip based on a second test environment, and obtaining the trimming target of the grade of chip according to a secondary test result until the trimming target of each chip in the batch of chips is obtained.
Preferably, step 3 further comprises steps 31 to 32. FIG. 3 is a flowchart of step 3 of the method for testing multi-environment batch chips according to the present invention. As shown in fig. 3, step 31, a trimming target of each chip is obtained according to the grading information and the expected attribute value of each chip in the grading chip. And step 32, comparing the secondary test result with the trimming target, and obtaining the trimming value of each chip in the grade of chip.
According to each grading information, the gear where the current chip is located can be obtained. And calculating to obtain the trimming target of the chip according to the grading information of the chip and the expected attribute value k.
Preferably, the trimming target of each chip is k (T)2-T1)+(an+an+1) 2; wherein n is the gear of the chip, k is the expected attribute value corresponding to the gear of the chip, and anIs the minimum standard gear value of the gear of the chip, an+1The maximum standard gear value of the gear of the chip. Therefore, the chips which are divided into the same gear have the same trimming target.
After the trimming target of the chip is determined, the trimming value can be obtained according to the difference between the second test result and the trimming target, and the chip can be trimmed. Generally, a chip for trimming has a programming function in an integrated circuit. After the secondary test is finished, the corresponding module in the chip can be programmed according to the trimming value for the current chip, so that the packaged chip is trimmed.
In the invention, a chip with a secondary programming function can be selected, namely, the acquired grading information of the chip is programmed in the trimming position of the chip in the form of the trimming value during the primary test. Therefore, when the secondary test is carried out, the grading information recorded in the trimming position can be called to calculate the trimming target, so that the batch trimming of the packaged chips can be realized without carrying out chip tracking outside the batch chips.
Compared with the prior art, the multi-environment batch chip testing method has the advantages that the batch chips are graded during primary testing, and different trimming references are provided for the chips according to grading information during secondary testing. And the chips are trimmed according to the trimming target, so that high-precision factory chips are provided in batches.
1. According to the invention, the batch of chips can be graded according to the primary test result, so that when the trimming target is generated by the secondary test, the trimming target can be changed according to different chip gears, and the yield is improved.
2. The invention can determine the trimming target generated in the secondary test based on the initial test performance of the chip in the test process, thereby ensuring the effectiveness of the two tests aiming at the same chip and realizing the test and trimming of chips in batches.
The present applicant has described and illustrated embodiments of the present invention in detail with reference to the accompanying drawings, but it should be understood by those skilled in the art that the above embodiments are merely preferred embodiments of the present invention, and the detailed description is only for the purpose of helping the reader to better understand the spirit of the present invention, and not for limiting the scope of the present invention, and on the contrary, any improvement or modification made based on the spirit of the present invention should fall within the scope of the present invention.
Claims (7)
1. A multi-environment batch chip testing method is characterized by comprising the following steps:
step 1, testing the batch chips for one time based on a first testing environment, and acquiring grading information of the batch chips according to a testing result for one time;
step 2, grading the batch chips according to the grading information, and grading the batch chips into first-grade chips to Nth-grade chips;
and 3, selecting any one of the N chips, carrying out secondary test on the chip based on a second test environment, and obtaining the trimming target of the chip according to a secondary test result until the trimming target of each chip in the batch of chips is obtained.
2. The method of claim 1, wherein the step 1 further comprises:
step 1.1, predetermining the grading range of the batch chips according to one or more standard gear values;
step 1.2, comparing the one-time test result with the one or more standard gear values;
and step 1.3, determining the grading information of each chip in the batch of chips according to the comparison result.
3. The method of claim 2, wherein the step 1 further comprises:
the grading information of each chip is the average value of the maximum standard gear value and the minimum standard gear value of the gear where the chip is located.
4. The method of claim 1, wherein the step 3 further comprises:
step 3.1, obtaining a trimming target of each chip according to the grading information and the expected attribute value of each chip in the grading chip;
and 3.2, comparing the secondary test result with the trimming target to obtain the trimming value of each chip in the grade of chip.
5. The method of claim 4, wherein the method further comprises:
the first test environment is a first test temperature T1The primary test result is a first test temperature T1Output voltage V of lower chip1；
The grading information of the batch of chips is according to a first test temperature T1Output voltage V of lower chip1Obtaining the average value of the maximum standard gear value and the minimum standard gear value of the gear where the chip is located;
the second test environment is a second test temperature T2The secondary test result is a second test temperature T2Output voltage V of lower chip2。
6. The method of claim 5, wherein the method further comprises:
the trimming target of each chip is k (T)2-T1)+(an+an+1)/2；
Wherein n is the gear of the chip, k is the expected attribute value corresponding to the gear of the chip, and anIs the minimum standard gear value of the gear of the chip, an+1The maximum standard gear value of the gear of the chip.
7. The method of claim 6, wherein the method further comprises:
according to the standard gear value a1、a2、a3、a4、a5Determining the output voltage range of the 4-gear qualified chip;
wherein, the output voltage of the first-gear chip is in the range of (a)1,a2]The output voltage of the second-level chip is in the range of (a)2,a3]The output voltage of the third-gear chip is in the range of (a)3,a4]The output voltage of the fourth-gear chip is in the range of (a)4,a5]；
Wherein, the grading information of the first grade chip is (a)1+a2) The grading information of the second grade chip is (a)2+a3) The grading information of the third grade chip is (a)3+a4) The grading information of the fourth grade chip is (a)4+a5)/2。
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| CN116990660A (en) * | 2023-06-25 | 2023-11-03 | 珠海妙存科技有限公司 | eMMC aging test method, eMMC aging test device, electronic equipment and computer readable storage medium |
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| CN116990660A (en) * | 2023-06-25 | 2023-11-03 | 珠海妙存科技有限公司 | eMMC aging test method, eMMC aging test device, electronic equipment and computer readable storage medium |
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