CN114430359B - FPGA-based phase-shift control radio frequency pulse width modulation method and system - Google Patents

FPGA-based phase-shift control radio frequency pulse width modulation method and system Download PDF

Info

Publication number
CN114430359B
CN114430359B CN202210097192.7A CN202210097192A CN114430359B CN 114430359 B CN114430359 B CN 114430359B CN 202210097192 A CN202210097192 A CN 202210097192A CN 114430359 B CN114430359 B CN 114430359B
Authority
CN
China
Prior art keywords
phase
pulse
sampling clock
shift control
sampling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202210097192.7A
Other languages
Chinese (zh)
Other versions
CN114430359A (en
Inventor
陈章
周强
魏志虎
朱蕾
张建亚
傅浩洋
何勰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National University of Defense Technology
Original Assignee
National University of Defense Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National University of Defense Technology filed Critical National University of Defense Technology
Priority to CN202210097192.7A priority Critical patent/CN114430359B/en
Publication of CN114430359A publication Critical patent/CN114430359A/en
Application granted granted Critical
Publication of CN114430359B publication Critical patent/CN114430359B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/20—Modulator circuits; Transmitter circuits
    • H04L27/2032—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner
    • H04L27/2035—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using a single or unspecified number of carriers
    • H04L27/2042—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using a single or unspecified number of carriers with more than two phase states
    • H04L27/205—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using a single or unspecified number of carriers with more than two phase states in which the data are represented by the change in phase of the carrier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/20—Modulator circuits; Transmitter circuits
    • H04L27/2032—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner
    • H04L27/2053—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases
    • H04L27/206—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases using a pair of orthogonal carriers, e.g. quadrature carriers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

The invention relates to a phase-shift control radio frequency pulse width modulation method and a phase-shift control radio frequency pulse width modulation system based on an FPGA, which relate to the field of wireless communication, and comprise the following steps: acquiring a baseband signal; determining phase shift control information of output pulses by using a radio frequency pulse width modulation algorithm for the baseband signals; carrying out phase quantization decomposition on the phase shift control information to obtain a sampling clock sequence number and a pulse generation control word; obtaining a pulse sampling clock according to the sampling clock sequence number, the pulse generator bit number information, the carrier frequency information and the sampling clock phase precision; and generating pulse waveforms according to the pulse generation control word and the pulse sampling clock to obtain the output of the phase-shift control pulse width modulator. The invention can simplify the constitution of the radio frequency pulse width modulator and the transmitter and reduce the complexity and the cost of the system.

Description

FPGA-based phase-shift control radio frequency pulse width modulation method and system
Technical Field
The invention relates to the field of wireless communication, in particular to a phase-shift control radio frequency pulse width modulation method and system based on an FPGA.
Background
In recent years, all-digital transmitters based on digital signal processing technology have become an important hallmark of implementing ultimate software radio architecture, drawing a great deal of attention in the field of communications, and their high efficiency, high linearity, and flexible reconfigurable and programmable performance have become the most attractive features of Software Defined Radio (SDR). The direct digital radio frequency modulation (Direct Digital Radio Frequency Modulation, DDRFM) technology is an important key technology for implementing an all-digital transmitter, and has the main functions of implementing digital up-conversion, and modulating a digital signal into a pulse signal suitable for being amplified by a switch mode power amplifier, thereby directly affecting the performance level of the all-digital transmitter.
Currently, radio frequency pulse width modulation (RF-PWM) is a popular technical means for implementing direct digital radio frequency modulation, wherein the main idea of the radio frequency pulse width modulation (outlining RF-PWM) based on phase shift control is to generate 2 paths of phase modulation signals with specific phase differences according to the amplitude and phase information of a baseband signal, and generate the required radio frequency pulse width modulation signals through the processing procedures of phase shift control, zero crossing comparison and the like. The existing methods for phase-shifting control of the radio frequency pulse width modulator based on the technology mainly comprise two methods: a phase-shift control radio frequency pulse width modulator based on digital delay line circuit is shown in figure 1, which mainly comprises a phase-shift control unit and a delay line unit, wherein the phase-shift control unit is used for extracting phase-shift control information of baseband signals, and the delay line unit is used for carrying out accurate delay processing on carriers of signals according to the phase-shift control information, so that digital up-conversion and pulse signal generation functions are realized simultaneously. The signal processing in the scheme is realized in the digital domain, and has stronger flexibility and reconfigurability. However, the design and development of a dedicated delay line device and an auxiliary circuit are required, and there are problems of high cost and poor versatility.
Another prior art scheme is a phase-shift control rf pulse width modulator implemented based on an analog comparator, and its structural schematic diagram is shown in fig. 2, which mainly comprises a phase-shift control unit, a phase control unit and a zero-crossing comparison unit. The phase shift control unit is responsible for extracting phase shift control information of baseband signals and is usually implemented in digital signal processing circuits with operation functions such as FPGA (field programmable gate array), DSP (digital signal processor) and the like; the phase control unit is generally composed of an analog up-conversion circuit, obtains 2 paths of phase modulation signals containing phase shift control information, and finally adopts an analog comparator circuit to carry out zero-crossing comparison on the 2 paths of phase modulation signals to obtain the required radio frequency pulse width signals. The circuit in the scheme can be generally realized by adopting a universal device, special custom development is not needed, and the technical maturity is high. However, the up-conversion process and the comparison process of the signals are realized in an analog circuit, the required circuit is complex, the reconfigurability and the programmability are poor, and the characteristics and the requirements of SDR are not met.
Disclosure of Invention
The invention aims to provide a phase-shift control radio frequency pulse width modulation method and a phase-shift control radio frequency pulse width modulation system based on an FPGA (field programmable gate array) so as to simplify the constitution of a radio frequency pulse width modulator and a transmitter and reduce the complexity and the cost of the system.
In order to achieve the above object, the present invention provides the following solutions:
a phase-shift control radio frequency pulse width modulation method based on FPGA comprises the following steps:
acquiring a baseband signal;
determining phase shift control information of output pulses by using a radio frequency pulse width modulation algorithm for the baseband signals;
carrying out phase quantization decomposition on the phase shift control information to obtain a sampling clock sequence number and a pulse generation control word;
obtaining a pulse sampling clock according to the sampling clock sequence number, the pulse generator bit number information, the carrier frequency information and the sampling clock phase precision;
and generating pulse waveforms according to the pulse generation control word and the pulse sampling clock to obtain the output of the phase-shift control pulse width modulator.
Optionally, the expression of the phase shift control information is:
ψ 1 (t)＝φ(t)+θ(t)
ψ 2 (t)＝φ(t)-θ(t)
wherein, psi is 1 (t) and ψ 2 And (t) represents the phase shift values of the two paths of phase modulation signals, phi (t) represents the phase values of the output baseband I signal and the baseband Q signal, and theta (t) represents the phase shift value components corresponding to the envelope values.
Optionally, the performing phase quantization decomposition on the phase shift control information to obtain a sampling clock sequence number and a pulse generation control word specifically includes:
determining a pulse generation control word according to the phase shift control information and the pulse generator bit number information;
and determining a sampling clock sequence number according to the phase shift control information, the pulse generator bit number information and the sampling clock phase precision.
Optionally, the pulse generation control word expression is:
β 1 (t)＝INT(ψ 1 (t)×2 M-1 /π)
β 2 (t)＝INT(ψ 2 (t)×2 M-1 /π)
wherein beta is 1 (t) and beta 2 (t) generating control words for pulses corresponding to the two paths of phase-shift control signals respectively, wherein M is pulse generator bit number information, and INT () represents rounding operation;
the expression of the sampling clock sequence number is:
wherein l 1 (t) and l 2 (t) sampling clock numbers corresponding to the two phase shift control signals respectively, REM () represents a remainder operation, ROUND () represents a rounding operation including rounding, ψ 1 (t) and ψ 2 And (t) respectively representing phase shift values of two paths of phase modulation signals, M is pulse generator bit number information, and delta theta is sampling clock phase precision.
Optionally, the obtaining the pulse sampling clock according to the sampling clock sequence number, the pulse generator bit number information, the carrier frequency information and the sampling clock phase precision specifically includes:
determining a sampling frequency according to the carrier frequency information and the pulse generator bit number information;
determining the number of multiple sampling clocks according to the pulse generator bit number information and the sampling clock phase precision;
generating multiple sampling clocks according to the sampling frequency, the multiple sampling clock quantity and a reference clock;
and determining a pulse sampling clock according to the sampling clock sequence number and the multiple sampling clocks.
Optionally, the expression of the sampling frequency is:
F s ＝2 M ·F c
wherein F is s For sampling frequency of multiple sampling clocks, F c The carrier frequency information is M, and the pulse generator bit number information is M;
the number of the multiple sampling clocks is
Wherein INT () represents a rounding operation, L is the number of multiple sampling clocks, Δθ is the sampling clock phase accuracy, Δθ min A minimum phase interval achievable between adjacent ones of the multiple sampling clocks;
the output of the multiple sampling clock is:
wherein Clk (l 1 ) And Clk (l) 2 ) Pulse sampling clock corresponding to two paths of phase-shifting control signals, l 1 Sampling clock sequence number corresponding to baseband I signal, l 2 And the sampling clock sequence number corresponding to the baseband Q signal is set, and t is the signal sampling time value.
Optionally, the generating a pulse waveform according to the pulse generating control word and the pulse sampling clock to obtain an output of the phase-shift control pulse width modulator specifically includes:
generating a pulse generation table index value by using a phase shift register according to the pulse generation control word;
determining a pulse generation table entry value according to the pulse generation table index value and the sampling clock;
and determining the output of the phase-shifting control pulse width modulator according to the pulse generation table entry value.
Optionally, the pulse generation table index value has the expression:
wherein K is 1 Generating a table index value, K, for the first pulse 2 For the second pulse generation table index value, M is pulse generator bit number information, alpha 1 And alpha 1 Output values of phase registers in the two-path pulse waveform generation module, beta 1 And beta 2 Control words are generated for pulses corresponding to the two phase shift control signals, respectively, and REM () represents a remainder operation.
The phase-shift control radio frequency pulse width modulation system based on the FPGA is arranged on the FPGA, and comprises:
the acquisition module is used for acquiring the baseband signal;
the modulation module is used for determining phase shift control information of output pulses by using a radio frequency pulse width modulation algorithm for the baseband signals;
the phase quantization and decomposition module is used for carrying out phase quantization and decomposition on the phase shift control information to obtain a sampling clock sequence number and a pulse generation control word;
the pulse sampling clock determining module is used for obtaining a pulse sampling clock according to the sampling clock sequence number, the pulse generator bit number information, the carrier frequency information and the sampling clock phase precision;
and the pulse waveform generation module is used for generating pulse waveforms according to the pulse generation control word and the pulse sampling clock to obtain the output of the phase-shift control pulse width modulator.
Optionally, the expression of the phase shift control information is:
ψ 1 (t)＝φ(t)+θ(t)
ψ 2 (t)＝φ(t)-θ(t)
wherein, psi is 1 (t) and ψ 2 (t) represents the phase shift values of the two phase modulation signals, respectively, and φ (t) represents the output baseband I signal and baseband Q signalAnd θ (t) represents a phase shift value component corresponding to the envelope value.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention provides a phase-shift control radio frequency pulse width modulation method and a phase-shift control radio frequency pulse width modulation system based on an FPGA, which acquire baseband signals; determining phase shift control information of output pulses by using a radio frequency pulse width modulation algorithm for the baseband signals; carrying out phase quantization decomposition on the phase shift control information to obtain a sampling clock sequence number and a pulse generation control word; obtaining a pulse sampling clock according to the sampling clock sequence number, the pulse generator bit number information, the carrier frequency information and the sampling clock phase precision; and generating pulse waveforms according to the pulse generation control word and the pulse sampling clock to obtain the output of the phase-shift control pulse width modulator. All processing procedures are realized in a digital domain through an FPGA device, so that the frequency conversion and zero crossing processing procedures in an analog domain are avoided, and special components are not required to be designed, thereby simplifying the constitution of a modulator and a transmitter and reducing the complexity and the cost of the system.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a prior art phase-shifting control RF pulse width modulator based on digital delay line circuit implementation;
FIG. 2 is a schematic diagram of a prior art phase-shift control RF pulse width modulator based on an analog comparator implementation;
FIG. 3 is a flowchart of a phase shift control RF pulse width modulation method based on FPGA provided by the invention;
fig. 4 is a schematic structural diagram of a phase-shift control rf pulse width modulator based on FPGA according to the present invention;
FIG. 5 is a schematic diagram of a pulse generating module according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a multi-sampling clock generating module according to an embodiment of the invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention aims to provide a phase-shift control radio frequency pulse width modulation method and a phase-shift control radio frequency pulse width modulation system based on an FPGA (field programmable gate array) so as to simplify the constitution of a radio frequency pulse width modulator and a transmitter and reduce the complexity and the cost of the system.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
As shown in fig. 3, the phase shift control radio frequency pulse width modulation method based on FPGA provided by the present invention includes:
step 101: a baseband signal is acquired.
Step 102: and determining phase shift control information of output pulses by using a radio frequency pulse width modulation algorithm for the baseband signals.
Step 103: and carrying out phase quantization decomposition on the phase shift control information to obtain a sampling clock sequence number and a pulse generation control word. Step 103, specifically includes: determining a pulse generation control word according to the phase shift control information and the pulse generator bit number information; and determining a sampling clock sequence number according to the phase shift control information, the pulse generator bit number information and the sampling clock phase precision.
The pulse generation control word expression is:
β 1 (t)＝INT(ψ 1 (t)×2 M-1 /π)
β 2 (t)＝INT(ψ 2 (t)×2 M-1 /π)
wherein beta is 1 (t) and beta 2 (t) generating control words for pulses corresponding to the two paths of phase-shift control signals respectively, wherein M is pulse generator bit number information, and INT () represents rounding operation;
the expression of the sampling clock sequence number is:
wherein l 1 (t) and l 2 (t) sampling clock numbers corresponding to the two phase shift control signals respectively, REM () represents a remainder operation, ROUND () represents a rounding operation including rounding, ψ 1 (t) and ψ 2 And (t) respectively representing phase shift values of two paths of phase modulation signals, M is pulse generator bit number information, and delta theta is sampling clock phase precision.
Step 104: and obtaining the pulse sampling clock according to the sampling clock sequence number, the pulse generator bit number information, the carrier frequency information and the sampling clock phase precision. Step 104 specifically includes: determining a sampling frequency according to the carrier frequency information and the pulse generator bit number information; determining the number of multiple sampling clocks according to the pulse generator bit number information and the sampling clock phase precision; generating multiple sampling clocks according to the sampling frequency, the multiple sampling clock quantity and a reference clock; and determining a pulse sampling clock according to the sampling clock sequence number and the multiple sampling clocks.
The expression of the sampling frequency is:
F s ＝2 M ·F c
wherein F is s For sampling frequency of multiple sampling clocks, F c The carrier frequency information is M, and the pulse generator bit number information is M;
the number of the multiple sampling clocks is
Wherein INT () represents a rounding operation, L is the number of multiple sampling clocks, Δθ is the sampling clock phase accuracy, Δθ min A minimum phase interval achievable between adjacent ones of the multiple sampling clocks;
the output of the multiple sampling clock is:
wherein Clk (l 1 ) And Clk (l) 2 ) For the output of the pulse sampling clock corresponding to the two paths of phase-shifting control signals, i.e. the multiple sampling clock, l 1 Sampling clock sequence number corresponding to baseband I signal, l 2 And the sampling clock sequence number corresponding to the baseband Q signal is set, and t is the signal sampling time value.
Step 105: and generating pulse waveforms according to the pulse generation control word and the pulse sampling clock to obtain the output of the phase-shift control pulse width modulator. Step 105 specifically includes: generating a pulse generation table index value by using a phase shift register according to the pulse generation control word; determining a pulse generation table entry value according to the pulse generation table index value and the sampling clock; and determining the output of the phase-shifting control pulse width modulator according to the pulse generation table entry value.
The pulse generation table index value has the expression:
wherein K is 1 Generating a table index value, K, for the first pulse 2 For the second pulse generation table index value, M is pulse generator bit number information, alpha 1 And alpha 1 Output values of phase registers in the two-path pulse waveform generation module, beta 1 And beta 2 Control words are generated for pulses corresponding to the two phase shift control signals, respectively, and REM () represents a remainder operation.
In practical application, the expression of the phase shift control information is:
ψ 1 (t)＝φ(t)+θ(t)
ψ 2 (t)＝φ(t)-θ(t)
wherein, psi is 1 (t) and ψ 2 And (t) represents the phase shift value of the 2-path phase modulation signal, phi (t) represents the phase values of the output baseband I signal and the baseband Q signal, and theta (t) represents the phase shift value component corresponding to the envelope value.
As shown in fig. 4 to 6, the present invention further provides a phase-shift control rf pulse width modulation system based on an FPGA, where the phase-shift control rf pulse width modulation system based on the FPGA is disposed on the FPGA, and the phase-shift control rf pulse width modulation system based on the FPGA includes:
and the acquisition module is used for acquiring the baseband signal.
And the modulation module is used for determining phase shift control information of output pulses by using a radio frequency pulse width modulation algorithm for the baseband signals.
And the phase quantization and decomposition module is used for carrying out phase quantization and decomposition on the phase shift control information to obtain a sampling clock sequence number and a pulse generation control word.
And the pulse sampling clock determining module is used for obtaining a pulse sampling clock according to the sampling clock sequence number, the pulse generator bit number information, the carrier frequency information and the sampling clock phase precision.
And the pulse waveform generation module is used for generating pulse waveforms according to the pulse generation control word and the pulse sampling clock to obtain the output of the phase-shift control pulse width modulator.
In practical application, the expression of the phase shift control information is:
ψ 1 (t)＝φ(t)+θ(t)
ψ 2 (t)＝φ(t)-θ(t)
wherein, psi is 1 (t) and ψ 2 (t) each represents a phase shift value of the 2-way phase modulation signal, phi (t) represents an output baseband I signal,The phase value of the baseband Q signal, θ (t), represents the phase-shift value component corresponding to the envelope value.
The pulse generation module with the dynamic multiple sampling clock type frequency direct synthesizer (Direct Digital Synthesis, DDS) structure is designed in the FPGA, so that the phase-shift control radio frequency pulse width modulation algorithm processing process is realized in the digital domain, the high-speed pulse width modulation method has good reconfigurability and programmability in the architecture, the requirements of components and modules such as a digital delay line, an analog comparator, an analog up-conversion circuit and the like are eliminated in the hardware realization, the constitution of a radio frequency pulse width modulator and a transmitter is simplified, the complexity and the cost of the system are reduced, and the universality and the adaptability of the phase-shift control radio frequency pulse width modulation technology are improved.
The phase-shifting control radio frequency pulse width modulator which is realized by utilizing a special digital delay line circuit or a zero-crossing comparator in the prior art is completely realized in a general FPGA device, a clock manager unit in the FPGA is utilized to design a multi-sampling clock, a pulse waveform generation module similar to the DDS is constructed, parameter data such as phase-shifting control information, carrier frequency information, phase precision of a sampling clock, pulse generator bit number and the like of a baseband signal are synthesized in a phase quantization decomposition module, an optimal sampling clock sequence number and a pulse generation control word are calculated, and the optimal sampling clock sequence number and the pulse generation control word are respectively sent to the multi-sampling clock generation module and the pulse waveform generation module to finish the phase-shifting control information loading processing of a pulse waveform, so that the function of the phase-shifting control radio frequency pulse width modulator is realized. The phase-shifting control radio frequency pulse width modulator consists of 1 phase quantization and decomposition module, 1 multiple sampling clock generation module and 2 pulse waveform generation modules.
Wherein the input data parameters of the phase quantization and decomposition module comprise phase shift control information (psi) of the input baseband signal 1 ，ψ 2 ) The phase accuracy Δθ of the sampling clock and the pulse generator bit number information M, and the output result is the sampling clock number (l 1 ，l 2 ) And pulse generation control word (beta) 1 ，β 2 ) And respectively transmitting the clock signals to the multi-sampling clock generation module and the pulse waveform generation module.
In which multiple sample clocks are generated as shown in figure 5The modular implementation is based on clock management units in the FPGA, relative to the input reference clock Clk ref It is possible to simultaneously generate L sampling clocks { Clk (1), clk (2),. The phase-increasing at intervals of Δθ, clk (L) }, and select the sampling clock Clk to be output according to the input sampling clock sequence number instruction L s Clk (l). The maximum number of clocks that a single clock management unit can output at the same time is determined by the hardware performance of the FPGA and the IP core type therein, and therefore, the multiple sampling clock generation module may be composed of 1 or more clock management units according to the size of L. The multiple sampling clock generation module outputs carrier frequency information F of output signals with clock frequency c And the number of bits M of the pulse generation table. Minimum achievable phase separation delta theta between adjacent sampling clocks of multiple sampling clock generation modules min Is determined by the hardware performance and physical characteristics of the FPGA.
The pulse waveform generating module shown in fig. 6 has a structural characteristic similar to DDS, and includes 1M-bit phase register, 2 modulo M-phase accumulator and 1M-bit pulse generating table, and input signal parameters include phase shift control information β and sampling clock Clk (l). Wherein, the output value alpha of the phase shift register is accumulated to generate an index value K of the pulse generation table, and the corresponding table item value S (K) is output according to the sampling clock Clk (l), namely the output value S of the phase shift control radio frequency pulse width modulator PWM 。
In one embodiment of the invention, the method comprises the steps of:
step 1: the highest working frequency F can be supported by the carrier frequency information Fc of the output signals and the FPGA device max The number of bits M of the pulse generation module must be designed so that the condition of expression (1) is satisfied. The entry value S (K) of the pulse generation table is designed according to the formula (2).
The index value K of the pulse generation table is an integer, and K is 0,2 M -1]The entry value S (K) of the pulse generation table is obtained by the formula (2)
Step 2: the carrier frequency information F of the output signal is synthesized according to the formulas (3) and (4) c The number M of bits of the pulse generating module, the sampling clock phase precision delta theta and other parameter data, and the sampling frequency F of the multiple sampling clock generating module is designed s And the number of output clocks L, and configure L resampling clocks according to equation (5).
According to carrier frequency information F of the output signal c The bit number M of the pulse generation module and the sampling clock phase precision delta theta determine the sampling frequency F of the multiple sampling clock generation module s And the number of output clocks L, as in the formulas (3) and (4)
F s ＝2 M ·F c (3)
Where INT () represents a rounding operation.
F calculated according to the formulas (3) and (4) s And L configuring the FPGA clock manager unit to obtain an L resampling clock as shown in formula (5)
{Clk(l)＝cos(2πF s t-l·Δθ)，l∈[0，L]}， (5)
Step 3: for input baseband I, Q signals i (t) and q (t), calculating phase shift value (psi) corresponding to output pulse signal according to phase shift RF-PWM algorithm 1 (t)，ψ 2 (t)) and sent to a phase quantization decomposition module, wherein the calculation process is shown in the formulas (6) to (10):
φ(t)＝tan -1 (q(t)/i(t)) (6)
θ(t)＝cos -1 (A(t)/max(A)) (8)
ψ 1 (t)＝φ(t)+θ(t) (9)
ψ 2 (t)＝φ(t)-θ(t) (10)
where φ (t) represents the phase value of the input baseband I, Q signal, A (t) represents the envelope value of the input baseband I, Q signal, θ (t) represents the phase-shifted value component corresponding to the envelope value, t is the signal sampling time value, and max (A) represents the maximum value of the input signal envelope.
Step 4: the phase precision delta theta of the sampling clock and the bit number information M of the pulse generator are combined, the calculation results according to the formulas (11) to (14) are input into a phase quantization and decomposition module, the sampling clock sequence number and the pulse generation control word are calculated, and the calculation results are respectively sent to a multi-sampling clock generation module and a pulse waveform generation module.
Inputting the calculation results according to the formulas (9) and (10) to a phase quantization and decomposition module, and calculating a sampling clock sequence number and a pulse generation control word by combining the phase precision delta theta of the sampling clock and the pulse generator bit number information M, wherein the calculation process is shown in the formulas (11) to (14):
β 1 (t)＝INT(ψ 1 (t)×2 M-1 /π) (11)
β 2 (t)＝INT(ψ 2 (t)×2 M-1 /π) (12)
where REM () represents a remainder operation and ROUND () represents a rounding operation including rounding. Beta 1 (t) generating control word for pulse corresponding to baseband I signal, beta 2 (t) generating a control word for a pulse corresponding to the baseband Q signal, l 1 (t) is the sampling clock sequence number corresponding to the baseband I signal, l 2 And (t) is the sampling clock sequence number corresponding to the baseband Q signal.
Step 5: transmitting the sampling clock output by the multiple sampling clock generation module obtained according to the formula (15) to the pulse waveform generation module, and sampling and outputting the pulse generation table entry value according to the pulse generation table index value determined by the formula (16)
The calculation results obtained by the formulas (11) to (14) are sent to the multi-sampling clock generation module and the pulse waveform generation module respectively, and there are
The output of the multiple sampling clock generation module is as follows:
the pulse generation table index value of the pulse waveform generation module is as follows:
wherein alpha is 1 And alpha 1 Respectively output values of phase registers in two pulse waveform generating modules, wherein the pulse waveform generating modules respectively adopt Clk (l 1 ) And Clk (l) 2 ) Output index value K as sampling clock 1 And K 2 Corresponding pulse generation table entry value S (K 1 ) S (K) 2 ) I.e. phase-shifted RF-PWM pulse waveform S PWM1 And S is PWM2 。
Compared with the radio frequency pulse width modulator in the prior art, the invention has the following technical advantages:
1. compared with the phase-shifting radio frequency pulse width modulator realized based on the digital delay line circuit in the prior art, the phase-shifting radio frequency pulse width modulator is realized by adopting a general FPGA device, a special digital delay line device and related configuration circuits are not required to be designed and realized, the modulator structure is simplified, the design cost and the engineering realization difficulty are reduced, and the universality and the realizability of the phase-shifting radio frequency pulse width modulation technology are improved.
2. Compared with the phase-shifting radio frequency pulse width modulator realized based on the analog comparator in the prior art, the phase-shifting radio frequency pulse width modulator realized based on the analog comparator has the advantages that the processing is realized in the digital domain completely by adopting the universal FPGA device, the processing procedures of up-conversion, zero-crossing comparison and the like in the analog domain are avoided in the phase-shifting radio frequency pulse width modulator realized based on the analog comparator, a series of related complex circuits and devices are omitted, the modulator structure is simplified, and the universality and the reconfigurability of the phase-shifting radio frequency pulse width modulation technology are improved.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present invention and the core ideas thereof; also, it is within the scope of the present invention to be modified by those of ordinary skill in the art in light of the present teachings. In view of the foregoing, this description should not be construed as limiting the invention.

Claims (2)

1. The phase-shift control radio frequency pulse width modulation method based on the FPGA is characterized by comprising the following steps of:
acquiring a baseband signal;
determining phase shift control information of output pulses by using a radio frequency pulse width modulation algorithm for the baseband signals;
the expression of the phase shift control information is as follows:
ψ 1 (t)＝φ(t)+θ(t)
ψ 2 (t)＝φ(t)-θ(t)
wherein, psi is 1 (t) and ψ 2 (t) represents the phase shift values of the two paths of phase modulation signals respectively, phi (t) represents the phase values of the output baseband I signal and the baseband Q signal, and theta (t) represents the phase shift value component corresponding to the envelope value;
carrying out phase quantization decomposition on the phase shift control information to obtain a sampling clock sequence number and a pulse generation control word; the phase-shift control information is subjected to phase quantization and decomposition to obtain a sampling clock sequence number and a pulse generation control word, and the method specifically comprises the following steps:
determining a pulse generation control word according to the phase shift control information and the pulse generator bit number information;
determining a sampling clock sequence number according to the phase shift control information, the pulse generator bit number information and the sampling clock phase precision;
the pulse generation control word expression is:
β 1 (t)＝INT(ψ 1 (t)×2 M-1 /π)
β 2 (t)＝INT(ψ 2 (t)×2 M-1 /π)
wherein beta is 1 (t) and beta 2 (t) generating control words for pulses corresponding to the two paths of phase-shift control signals respectively, wherein M is pulse generator bit number information, and INT () represents rounding operation;
the expression of the sampling clock sequence number is:
wherein l 1 (t) and l 2 (t) sampling clock numbers corresponding to the two phase shift control signals respectively, REM () represents a remainder operation, ROUND () represents a rounding operation including rounding, ψ 1 (t) and ψ 2 (t) respectively representing phase shift values of two paths of phase modulation signals, M is pulse generator bit number information, and delta theta is sampling clock phase precision;
obtaining a pulse sampling clock according to the sampling clock sequence number, the pulse generator bit number information, the carrier frequency information and the sampling clock phase precision; the method for obtaining the pulse sampling clock according to the sampling clock sequence number, the pulse generator bit number information, the carrier frequency information and the sampling clock phase precision specifically comprises the following steps:
determining a sampling frequency according to the carrier frequency information and the pulse generator bit number information;
determining the number of multiple sampling clocks according to the pulse generator bit number information and the sampling clock phase precision;
generating multiple sampling clocks according to the sampling frequency, the multiple sampling clock quantity and a reference clock;
determining a pulse sampling clock according to the sampling clock sequence number and the multiple sampling clocks;
the expression of the sampling frequency is:
F s ＝2 M ·F c
wherein F is s For sampling frequency of multiple sampling clocks, F c The carrier frequency information is M, and the pulse generator bit number information is M;
the number of the multiple sampling clocks is
Wherein INT () represents a rounding operation, L is the number of multiple sampling clocks, Δθ is the sampling clock phase accuracy, Δθ min A minimum phase interval achievable between adjacent ones of the multiple sampling clocks;
the output of the multiple sampling clock is:
wherein Clk (l 1 ) And Clk (l) 2 ) Pulse sampling clock corresponding to two paths of phase-shifting control signals, l 1 Sampling clock sequence number corresponding to baseband I signal, l 2 The sampling clock sequence number corresponding to the baseband Q signal is given, and t is the signal sampling time value;
generating pulse waveforms according to the pulse generation control word and the pulse sampling clock to obtain the output of the phase-shifting control pulse width modulator; the step of generating pulse waveforms according to the pulse generation control word and the pulse sampling clock to obtain the output of the phase-shift control pulse width modulator specifically comprises the following steps:
generating a pulse generation table index value by using a phase shift register according to the pulse generation control word;
determining a pulse generation table entry value according to the pulse generation table index value and the sampling clock;
determining the output of a phase-shift control pulse width modulator according to the pulse generation table entry value;
the pulse generation table index value has the expression:
wherein K is 1 Generating a table index value, K, for the first pulse 2 For the second pulse generation table index value, M is pulse generator bit number information, alpha 1 And alpha 1 Output values of phase registers in the two-path pulse waveform generation module, beta 1 And beta 2 Control words are generated for pulses corresponding to the two phase shift control signals, respectively, and REM () represents a remainder operation.
2. The phase-shift control radio frequency pulse width modulation system based on the FPGA is characterized in that the phase-shift control radio frequency pulse width modulation system based on the FPGA is arranged on the FPGA, and the phase-shift control radio frequency pulse width modulation system based on the FPGA comprises:
the acquisition module is used for acquiring the baseband signal;
the modulation module is used for determining phase shift control information of output pulses by using a radio frequency pulse width modulation algorithm for the baseband signals;
the expression of the phase shift control information is as follows:
ψ 1 (t)＝φ(t)+θ(t)
ψ 2 (t)＝φ(t)-θ(t)
wherein, psi is 1 (t) and ψ 2 (t) represents the phase shift values of the two phase modulation signals, phi (t) represents the phase values of the output baseband I signal and the baseband Q signal, and theta (t) representsA phase shift value component corresponding to the envelope value;
the phase quantization and decomposition module is used for carrying out phase quantization and decomposition on the phase shift control information to obtain a sampling clock sequence number and a pulse generation control word; the phase-shift control information is subjected to phase quantization and decomposition to obtain a sampling clock sequence number and a pulse generation control word, and the method specifically comprises the following steps:
determining a pulse generation control word according to the phase shift control information and the pulse generator bit number information;
determining a sampling clock sequence number according to the phase shift control information, the pulse generator bit number information and the sampling clock phase precision;
the pulse generation control word expression is:
β 1 (t)＝INT(ψ 1 (t)×2 M-1 /π)
β 2 (t)＝INT(ψ 2 (t)×2 M-1 /π)
wherein beta is 1 (t) and beta 2 (t) generating control words for pulses corresponding to the two paths of phase-shift control signals respectively, wherein M is pulse generator bit number information, and INT () represents rounding operation;
the expression of the sampling clock sequence number is:
wherein l 1 (t) and l 2 (t) sampling clock numbers corresponding to the two phase shift control signals respectively, REM () represents a remainder operation, ROUND () represents a rounding operation including rounding, ψ 1 (t) and ψ 2 (t) respectively representing phase shift values of two paths of phase modulation signals, M is pulse generator bit number information, and delta theta is sampling clock phase precision;
the pulse sampling clock determining module is used for obtaining a pulse sampling clock according to the sampling clock sequence number, the pulse generator bit number information, the carrier frequency information and the sampling clock phase precision; the method for obtaining the pulse sampling clock according to the sampling clock sequence number, the pulse generator bit number information, the carrier frequency information and the sampling clock phase precision specifically comprises the following steps:
determining a sampling frequency according to the carrier frequency information and the pulse generator bit number information;
determining the number of multiple sampling clocks according to the pulse generator bit number information and the sampling clock phase precision;
generating multiple sampling clocks according to the sampling frequency, the multiple sampling clock quantity and a reference clock;
determining a pulse sampling clock according to the sampling clock sequence number and the multiple sampling clocks;
the expression of the sampling frequency is:
F s ＝2 M ·F c
wherein F is s For sampling frequency of multiple sampling clocks, F c The carrier frequency information is M, and the pulse generator bit number information is M;
the number of the multiple sampling clocks is
Wherein INT () represents a rounding operation, L is the number of multiple sampling clocks, Δθ is the sampling clock phase accuracy, Δθ min A minimum phase interval achievable between adjacent ones of the multiple sampling clocks;
the output of the multiple sampling clock is:
wherein Clk (l 1 ) And Clk (l) 2 ) Pulse sampling clock corresponding to two paths of phase-shifting control signals, l 1 Sampling clock sequence number corresponding to baseband I signal, l 2 For baseband Q signal pairsThe corresponding sampling clock sequence number, t is the signal sampling time value;
the pulse waveform generation module is used for generating a pulse waveform according to the pulse generation control word and the pulse sampling clock to obtain the output of the phase-shift control pulse width modulator; the step of generating pulse waveforms according to the pulse generation control word and the pulse sampling clock to obtain the output of the phase-shift control pulse width modulator specifically comprises the following steps:
generating a pulse generation table index value by using a phase shift register according to the pulse generation control word;
determining a pulse generation table entry value according to the pulse generation table index value and the sampling clock;
determining the output of a phase-shift control pulse width modulator according to the pulse generation table entry value;
the pulse generation table index value has the expression:
wherein K is 1 Generating a table index value, K, for the first pulse 2 For the second pulse generation table index value, M is pulse generator bit number information, alpha 1 And alpha 1 Output values of phase registers in the two-path pulse waveform generation module, beta 1 And beta 2 Control words are generated for pulses corresponding to the two phase shift control signals, respectively, and REM () represents a remainder operation.
CN202210097192.7A 2022-01-27 2022-01-27 FPGA-based phase-shift control radio frequency pulse width modulation method and system Active CN114430359B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210097192.7A CN114430359B (en) 2022-01-27 2022-01-27 FPGA-based phase-shift control radio frequency pulse width modulation method and system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210097192.7A CN114430359B (en) 2022-01-27 2022-01-27 FPGA-based phase-shift control radio frequency pulse width modulation method and system

Publications (2)

Publication Number Publication Date
CN114430359A CN114430359A (en) 2022-05-03
CN114430359B true CN114430359B (en) 2023-10-20

Family

ID=81313758

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210097192.7A Active CN114430359B (en) 2022-01-27 2022-01-27 FPGA-based phase-shift control radio frequency pulse width modulation method and system

Country Status (1)

Country Link
CN (1) CN114430359B (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6434194B1 (en) * 1997-11-05 2002-08-13 Wherenet Corp Combined OOK-FSK/PPM modulation and communication protocol scheme providing low cost, low power consumption short range radio link
CN101641931A (en) * 2006-12-18 2010-02-03 艾利森电话股份有限公司 Pulse width modulator

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6434194B1 (en) * 1997-11-05 2002-08-13 Wherenet Corp Combined OOK-FSK/PPM modulation and communication protocol scheme providing low cost, low power consumption short range radio link
CN101641931A (en) * 2006-12-18 2010-02-03 艾利森电话股份有限公司 Pulse width modulator

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
周三文等.数字可变符号率调制器设计.遥测遥控.2013,第34卷(第3期),全文. *
数字可变符号率调制器设计;周三文等;遥测遥控;第34卷(第3期);全文 *

Also Published As

Publication number Publication date
CN114430359A (en) 2022-05-03

Similar Documents

Publication Publication Date Title
US5534827A (en) Modulator
CN108107389A (en) Magnetic nuclear resonance radio frequency impulse generator and control method based on digital modulation technique
US7728691B2 (en) Modulator for radio-frequency signals
CN114430359B (en) FPGA-based phase-shift control radio frequency pulse width modulation method and system
US6940920B2 (en) Multiplier arrangement, signal modulator and transmitter
CN102467152A (en) Method, device and system for realizing amplitude modulation and amplitude keying functions in signal source
CN115826674A (en) Implementation method and system of clock signal generator with stepped frequency in millihertz level
JP4068415B2 (en) Phase shift keying modulator
CN102355257B (en) Digital signal generator
KR100457175B1 (en) Quadrature modulation transmitter
CN117214836A (en) Digital array radio frequency transceiver platform construction method based on RFSoC
Fang et al. Design and simulation of DDS based on Quartus II
JP2008259201A (en) System and method for digital modulation
CN206349986U (en) A kind of digital arrays module based on AD9957
CN112311398B (en) Method and system for doubling generation rate of DDS (direct digital synthesizer) digital signal
Liu Design of typical waveform generator based on DDS/SOPC
CN109889197B (en) Multi-path coherent frequency synthesis circuit based on linear frequency modulation continuous waveform
JPH11289224A (en) Frequency synthesizer
Sun et al. An improved DRFM system based on digital channelized receiver
CN102412839A (en) Circuit used for analog-digital conversion
Nilsson et al. A Low Complexity DDS IC for FM-UWB Applications
US10044383B2 (en) Sinewave generation from multi-phase signals
CN110933006A (en) Parallel digital synthesis method and circuit of FM modulation signal
KR100233828B1 (en) Direct digital frequency synthesizer
JPS63185105A (en) Generating circuit for high frequency optional signal

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant