CN114430359A - Phase-shift control radio frequency pulse width modulation method and system based on FPGA - Google Patents

Phase-shift control radio frequency pulse width modulation method and system based on FPGA Download PDF

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CN114430359A
CN114430359A CN202210097192.7A CN202210097192A CN114430359A CN 114430359 A CN114430359 A CN 114430359A CN 202210097192 A CN202210097192 A CN 202210097192A CN 114430359 A CN114430359 A CN 114430359A
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phase
pulse
sampling clock
shift control
information
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CN114430359B (en
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陈章
周强
魏志虎
朱蕾
张建亚
傅浩洋
何勰
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National University of Defense Technology
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/20—Modulator circuits; Transmitter circuits
    • H04L27/2032—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner
    • H04L27/2035—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using a single or unspecified number of carriers
    • H04L27/2042—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using a single or unspecified number of carriers with more than two phase states
    • H04L27/205—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using a single or unspecified number of carriers with more than two phase states in which the data are represented by the change in phase of the carrier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/20—Modulator circuits; Transmitter circuits
    • H04L27/2032—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner
    • H04L27/2053—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases
    • H04L27/206—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases using a pair of orthogonal carriers, e.g. quadrature carriers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

The invention relates to a phase-shift control radio frequency pulse width modulation method and system based on FPGA, relating to the field of wireless communication, wherein the method comprises the following steps: obtaining a baseband signal; determining phase shift control information of output pulses for the baseband signals by using a radio frequency pulse width modulation algorithm; carrying out phase quantization decomposition on the phase shift control information to obtain a sampling clock sequence number and a pulse generation control word; obtaining a pulse sampling clock according to the sampling clock serial number, the pulse generator bit number information, the carrier frequency information and the sampling clock phase precision; and generating a pulse waveform according to the pulse generation control word and the pulse sampling clock to obtain the output of the phase-shift control pulse width modulator. The invention can simplify the constitution of the radio frequency pulse width modulator and the transmitter, and reduce the complexity and the cost of the system.

Description

Phase-shift control radio frequency pulse width modulation method and system based on FPGA
Technical Field
The invention relates to the field of wireless communication, in particular to a phase-shift control radio frequency pulse width modulation method and system based on an FPGA (field programmable gate array).
Background
In recent years, all-digital transmitters based on digital signal processing technology have become an important mark for realizing ultimate software radio architectures, and have attracted extensive attention in the field of communications, and their high efficiency, high linearity, and flexible reconfigurable and programmable performance have become the most attractive features of Software Defined Radio (SDR). The Direct Digital Radio Frequency Modulation (DDRFM) technology is an important key technology for realizing an all-Digital transmitter, and has the main functions of realizing Digital up-conversion and modulating a Digital signal into a pulse signal suitable for being amplified by a switch mode power amplifier, so that the performance level of the all-Digital transmitter is directly influenced.
Currently, a radio frequency pulse width modulation (RF-PWM) technology is a popular technical means for implementing direct digital radio frequency modulation, wherein the main idea of the radio frequency pulse width modulation (out-phasing RF-PWM) technology based on phase shift control is to generate 2 paths of phase modulation signals with specific phase difference according to amplitude and phase information of baseband signals, and generate required radio frequency pulse width modulation signals through processing processes such as phase shift control and zero-crossing comparison. The existing methods for realizing the phase shift control radio frequency pulse width modulator based on the technology mainly comprise two methods: a phase-shift control radio frequency pulse width modulator realized based on a digital delay line circuit is shown in a schematic structural diagram in figure 1 and mainly comprises a phase-shift control unit and a delay line unit, wherein the phase-shift control unit is responsible for extracting phase-shift control information of a baseband signal, and the delay line unit is responsible for carrying out precise delay processing on a carrier wave of the signal according to the phase-shift control information, so that the functions of digital up-conversion and pulse signal generation are realized simultaneously. The signal processing in the scheme is realized in a digital domain, and has stronger flexibility and reconfigurability. However, it is necessary to design and develop a dedicated delay line device and an auxiliary circuit, which causes problems of high cost and poor versatility.
Another prior art scheme is a phase-shift control rf pulse width modulator implemented based on an analog comparator, and a schematic structural diagram of the phase-shift control rf pulse width modulator is shown in fig. 2, and the phase-shift control rf pulse width modulator mainly includes a phase-shift control unit, a phase control unit, and a zero-crossing comparison unit. The phase shift control unit is responsible for extracting phase shift control information of the baseband signal and is usually realized in a digital signal processing circuit with an operation function, such as an FPGA (field programmable gate array) and a DSP (digital signal processor); the phase control unit is usually composed of an analog up-conversion circuit, obtains 2 paths of phase modulation signals containing phase-shift control information, and finally adopts an analog comparator circuit to perform zero-crossing comparison on the 2 paths of phase modulation signals to obtain the required radio frequency pulse width signal. The circuit in the scheme can be realized by adopting a general device without special customization and development, and the technical maturity is high. However, the up-conversion process and the comparison process of the signal are both realized in an analog circuit, and the required circuit is complex, has poor reconfigurability and programmability, and does not meet the characteristics and requirements of SDR.
Disclosure of Invention
The invention aims to provide a phase-shift control radio frequency pulse width modulation method and system based on an FPGA (field programmable gate array), so as to simplify the structure of a radio frequency pulse width modulator and a transmitter and reduce the complexity and cost of the system.
In order to achieve the purpose, the invention provides the following scheme:
a phase shift control radio frequency pulse width modulation method based on FPGA comprises the following steps:
obtaining a baseband signal;
determining phase shift control information of output pulses for the baseband signals by using a radio frequency pulse width modulation algorithm;
carrying out phase quantization decomposition on the phase shift control information to obtain a sampling clock sequence number and a pulse generation control word;
obtaining a pulse sampling clock according to the sampling clock serial number, the pulse generator bit number information, the carrier frequency information and the sampling clock phase precision;
and generating a pulse waveform according to the pulse generation control word and the pulse sampling clock to obtain the output of the phase-shift control pulse width modulator.
Optionally, the expression of the phase shift control information is:
ψ1(t)＝φ(t)+θ(t)
ψ2(t)＝φ(t)-θ(t)
wherein psi1(t) and ψ2And (t) respectively represents the phase shift values of the two paths of phase modulation signals, phi (t) represents the phase values of the output baseband I signal and the baseband Q signal, and theta (t) represents the phase shift value component corresponding to the envelope value.
Optionally, the performing phase quantization decomposition on the phase shift control information to obtain a sampling clock sequence number and a pulse generation control word specifically includes:
determining a pulse generation control word according to the phase shift control information and the pulse generator digit information;
and determining the sampling clock serial number according to the phase shift control information, the pulse generator bit number information and the sampling clock phase precision.
Optionally, the pulse generation control word expression is:
β1(t)＝INT(ψ1(t)×2M-1/π)
β2(t)＝INT(ψ2(t)×2M-1/π)
wherein, beta1(t) and beta2(t) generating control words for the pulses corresponding to the two paths of phase-shift control signals respectively, wherein M is the bit information of the pulse generator, and INT () represents rounding operation;
the expression of the sampling clock sequence number is as follows:
Figure BDA0003491318510000031
Figure BDA0003491318510000032
wherein l1(t) and l2(t) the sampling clock sequence numbers corresponding to the two phase-shift control signals, REM () represents remainder operation, ROUND () represents rounding operation including rounding, psi1(t) and ψ2And (t) respectively representing the phase shift values of the two paths of phase modulation signals, wherein M is the bit information of the pulse generator, and Delta theta is the phase precision of the sampling clock.
Optionally, the obtaining a pulse sampling clock according to the sampling clock sequence number, the pulse generator bit number information, the carrier frequency information, and the sampling clock phase precision specifically includes:
determining a sampling frequency according to the carrier frequency information and the pulse generator bit number information;
determining the number of multiple sampling clocks according to the bit information of the pulse generator and the phase precision of the sampling clocks;
generating a multiple sampling clock according to the sampling frequency, the multiple sampling clock number and a reference clock;
and determining a pulse sampling clock according to the sampling clock sequence number and the multiple sampling clock.
Optionally, the expression of the sampling frequency is:
Fs＝2M·Fc
wherein, FsFor multiple sampling frequencies of the sampling clock, FcThe carrier frequency information is M, and the pulse generator bit number information is M;
the number of the multiple sampling clocks is
Figure BDA0003491318510000041
Wherein INT () represents a rounding operation, L is the number of multiple sampling clocks, Δ θ is the sampling clock phase accuracyminThe minimum phase interval which can be realized between adjacent sampling clocks in the multiple sampling clocks;
the output of the multisampling clock is:
Figure BDA0003491318510000042
wherein, Clk (l)1) And Clk (l)2) For two-way phase-shifting control signal pairCorresponding pulse sampling clock,/1For the sampling clock number, l, corresponding to the baseband I signal2The sampling clock sequence number corresponding to the baseband Q signal, and t is the signal sampling time value.
Optionally, the generating a pulse waveform according to the pulse generation control word and the pulse sampling clock to obtain an output of the phase-shift control pulse width modulator specifically includes:
generating a pulse generation table index value by using a phase shift register according to the pulse generation control word;
determining a pulse generation table entry value according to the pulse generation table index value and the sampling clock;
and determining the output of the phase-shift control pulse width modulator according to the table entry value of the pulse generation table.
Optionally, the expression of the pulse generation table index value is:
Figure BDA0003491318510000043
wherein, K1Generating a table index value, K, for the first pulse2Generating a table index value for the second pulse, M being the pulse generator bit number information, α1And alpha1Respectively the output value, beta, of the phase register in the two pulse waveform generation modules1And beta2And respectively generating control words for the pulses corresponding to the two paths of phase-shifting control signals, wherein REM () represents remainder calculation.
The phase shift control radio frequency pulse width modulation system based on the FPGA comprises:
the acquisition module is used for acquiring a baseband signal;
the modulation module is used for determining phase shift control information of output pulses for the baseband signals by utilizing a radio frequency pulse width modulation algorithm;
the phase quantization decomposition module is used for performing phase quantization decomposition on the phase shift control information to obtain a sampling clock sequence number and a pulse generation control word;
the pulse sampling clock determining module is used for obtaining a pulse sampling clock according to the sampling clock serial number, the pulse generator digit information, the carrier frequency information and the sampling clock phase precision;
and the pulse waveform generating module is used for generating a pulse waveform according to the pulse generation control word and the pulse sampling clock to obtain the output of the phase-shift control pulse width modulator.
Optionally, the expression of the phase shift control information is:
ψ1(t)＝φ(t)+θ(t)
ψ2(t)＝φ(t)-θ(t)
wherein psi1(t) and ψ2And (t) respectively represents the phase shift values of the two paths of phase modulation signals, phi (t) represents the phase values of the output baseband I signal and the baseband Q signal, and theta (t) represents the phase shift value component corresponding to the envelope value.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention provides a phase-shift control radio frequency pulse width modulation method and system based on FPGA, which obtains baseband signals; determining phase shift control information of output pulses for the baseband signals by using a radio frequency pulse width modulation algorithm; carrying out phase quantization decomposition on the phase shift control information to obtain a sampling clock sequence number and a pulse generation control word; obtaining a pulse sampling clock according to the sampling clock serial number, the pulse generator bit number information, the carrier frequency information and the sampling clock phase precision; and generating a pulse waveform according to the pulse generation control word and the pulse sampling clock to obtain the output of the phase-shift control pulse width modulator. All processing procedures are realized in a digital domain through the FPGA device, the frequency conversion and zero-crossing processing procedures in an analog domain are avoided, and special components are not required to be designed, so that the structure of a modulator and a transmitter is simplified, and the complexity and the cost of a system are reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a schematic diagram of a phase-shift control RF pulse width modulator implemented based on a digital delay line circuit in the prior art;
FIG. 2 is a schematic diagram of a phase-shift controlled RF pulse width modulator implemented based on an analog comparator in the prior art;
FIG. 3 is a flow chart of the phase shift control RF pulse width modulation method based on FPGA according to the present invention;
FIG. 4 is a schematic structural diagram of a phase-shift control RF pulse width modulator based on FPGA according to the present invention;
fig. 5 is a schematic structural diagram of a pulse generation module according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a multiple sampling clock generation module according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a phase-shift control radio frequency pulse width modulation method and system based on an FPGA (field programmable gate array), so as to simplify the structures of a radio frequency pulse width modulator and a transmitter and reduce the complexity and cost of the system.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
As shown in fig. 3, the phase shift control rf pulse width modulation method based on FPGA provided in the present invention includes:
step 101: a baseband signal is acquired.
Step 102: and determining the phase shift control information of the output pulse by using a radio frequency pulse width modulation algorithm for the baseband signal.
Step 103: and carrying out phase quantization decomposition on the phase shift control information to obtain a sampling clock sequence number and a pulse generation control word. Step 103, specifically comprising: determining a pulse generation control word according to the phase shift control information and the pulse generator digit information; and determining the sampling clock serial number according to the phase shift control information, the pulse generator bit number information and the sampling clock phase precision.
The pulse generation control word expression is as follows:
β1(t)＝INT(ψ1(t)×2M-1/π)
β2(t)＝INT(ψ2(t)×2M-1/π)
wherein, beta1(t) and beta2(t) generating control words for the pulses corresponding to the two paths of phase-shift control signals respectively, wherein M is the bit information of the pulse generator, and INT () represents rounding operation;
the expression of the sampling clock sequence number is as follows:
Figure BDA0003491318510000071
Figure BDA0003491318510000072
wherein l1(t) and l2(t) the sampling clock sequence numbers corresponding to the two phase-shift control signals, REM () represents remainder operation, ROUND () represents rounding operation including rounding, psi1(t) and ψ2And (t) respectively representing the phase shift values of the two paths of phase modulation signals, wherein M is the bit information of the pulse generator, and Delta theta is the phase precision of the sampling clock.
Step 104: and obtaining a pulse sampling clock according to the sampling clock serial number, the pulse generator bit number information, the carrier frequency information and the sampling clock phase precision. Step 104, specifically comprising: determining a sampling frequency according to the carrier frequency information and the pulse generator bit number information; determining the number of multiple sampling clocks according to the bit information of the pulse generator and the phase precision of the sampling clocks; generating a multiple sampling clock according to the sampling frequency, the multiple sampling clock number and a reference clock; and determining a pulse sampling clock according to the sampling clock sequence number and the multiple sampling clock.
The expression of the sampling frequency is:
Fs＝2M·Fc
wherein, FsFor multiple sampling frequencies of the sampling clock, FcThe carrier frequency information is M, and the pulse generator bit number information is M;
the number of the multiple sampling clocks is
Figure BDA0003491318510000073
Wherein INT () represents a rounding operation, L is the number of multiple sampling clocks, Δ θ is the sampling clock phase accuracyminThe minimum phase interval which can be realized between adjacent sampling clocks in the multiple sampling clocks;
the output of the multisampling clock is:
Figure BDA0003491318510000081
wherein, Clk (l)1) And Clk (l)2) For the output of a pulse sampling clock, i.e. a multiple sampling clock, corresponding to the two phase-shifted control signals1For the sampling clock number, l, corresponding to the baseband I signal2The sampling clock sequence number corresponding to the baseband Q signal, and t is the signal sampling time value.
Step 105: and generating a pulse waveform according to the pulse generation control word and the pulse sampling clock to obtain the output of the phase-shift control pulse width modulator. Step 105, specifically comprising: generating a pulse generation table index value by using a phase shift register according to the pulse generation control word; determining a pulse generation table entry value according to the pulse generation table index value and the sampling clock; and determining the output of the phase-shift control pulse width modulator according to the table entry value of the pulse generation table.
The expression of the pulse generation table index value is as follows:
Figure BDA0003491318510000082
wherein, K1Generating a table index value, K, for the first pulse2Generating a table index value for the second pulse, M being the pulse generator bit number information, α1And alpha1Respectively the output value beta of the phase register in the two pulse waveform generating modules1And beta2And respectively generating control words for the pulses corresponding to the two paths of phase-shifting control signals, wherein REM () represents remainder calculation.
In practical application, the expression of the phase shift control information is as follows:
ψ1(t)＝φ(t)+θ(t)
ψ2(t)＝φ(t)-θ(t)
wherein psi1(t) and ψ2And (t) respectively represents the phase shift value of the 2 paths of phase modulation signals, phi (t) represents the phase value of the output baseband I signal and the baseband Q signal, and theta (t) represents the phase shift value component corresponding to the envelope value.
As shown in fig. 4 to fig. 6, the present invention further provides an FPGA-based phase shift control rf pulse width modulation system, where the FPGA-based phase shift control rf pulse width modulation system is disposed in an FPGA, and the FPGA-based phase shift control rf pulse width modulation system includes:
and the acquisition module is used for acquiring the baseband signal.
And the modulation module is used for determining the phase shift control information of the output pulse for the baseband signal by using a radio frequency pulse width modulation algorithm.
And the phase quantization decomposition module is used for performing phase quantization decomposition on the phase shift control information to obtain a sampling clock sequence number and a pulse generation control word.
And the pulse sampling clock determining module is used for obtaining a pulse sampling clock according to the sampling clock serial number, the pulse generator digit information, the carrier frequency information and the sampling clock phase precision.
And the pulse waveform generating module is used for generating a pulse waveform according to the pulse generation control word and the pulse sampling clock to obtain the output of the phase-shift control pulse width modulator.
In practical application, the expression of the phase shift control information is as follows:
ψ1(t)＝φ(t)+θ(t)
ψ2(t)＝φ(t)-θ(t)
wherein psi1(t) and ψ2And (t) respectively represents the phase shift value of the 2 paths of phase modulation signals, phi (t) represents the phase value of the output baseband I signal and the baseband Q signal, and theta (t) represents the phase shift value component corresponding to the envelope value.
The invention designs the pulse generating module with a Direct Digital Synthesis (DDS) structure of a class frequency of a dynamic multi-sampling clock in the FPGA, completely realizes the processing process of the phase-shift control radio frequency pulse width modulation algorithm in a Digital domain, has good reconfigurability and programmability on the framework, gets rid of the requirements on components and modules such as a Digital delay line, an analog comparator, an analog up-conversion circuit and the like on the hardware realization, simplifies the composition of the radio frequency pulse width modulator and a transmitter, reduces the complexity and the cost of a system, and promotes the universality and the adaptability of the phase-shift control radio frequency pulse width modulation technology.
The phase-shift control radio-frequency pulse width modulator which needs to be realized by a special digital delay line circuit or a zero-crossing comparator in the prior art is completely realized in a general FPGA device, a clock manager unit in the FPGA is used for designing a multi-sampling clock, a pulse waveform generation module similar to a DDS is constructed, parameter data such as phase-shift control information, carrier frequency information, phase precision of the sampling clock, pulse generator bit number and the like of a baseband signal are synthesized in a phase quantization decomposition module, the optimal sampling clock serial number and pulse generation control word are calculated and respectively sent to the multi-sampling clock generation module and the pulse waveform generation module, the phase-shift control information loading processing of the pulse waveform is completed, and the function of the phase-shift control radio-frequency pulse width modulator is realized. The phase-shift control radio frequency pulse width modulator consists of 1 phase-shift quantization decomposition module, 1 multiple sampling clock generation module and 2 pulse waveform generation modules.
Wherein the input data parameters of the phase quantization decomposition module comprise phase shift control information (psi) of the input baseband signal1，ψ2) Phase precision Delta theta of sampling clock and pulse generator bit number information M, and the output result is sampling clock number1，l2) And a pulse generation control word (beta)1，β2) And respectively sent to the multiple sampling clock generation module and the pulse waveform generation module.
Wherein the multiple sampling clock generation module shown in fig. 5 is implemented based on a clock management unit in the FPGA with respect to the input reference clock ClkrefL sampling clocks { Clk (1), Clk (2),. and Clk (L) } with increasing phase at intervals of delta theta can be generated simultaneously, and the output sampling clock Clk is selected according to an input sampling clock sequence number instruction LsClk (l). The maximum number of clocks which can be simultaneously output by a single clock management unit is determined by the hardware performance of the FPGA and the type of an IP core in the FPGA, so that the multi-sampling clock generation module can be composed of 1 or more clock management units according to different sizes of L. The multiple sampling clock generation module outputs carrier frequency information F of the output signal by adopting clock frequencycAnd the number of bits M of the pulse generation table. Minimum achievable phase spacing delta theta between adjacent sampling clocks of a multisampling clock generation moduleminDetermined by the hardware performance and physical characteristics of the FPGA.
The pulse waveform generation module shown in fig. 6 has the structural characteristics of a DDS-like structure, and includes 1M-bit phase register, 2 modulo M plus phase accumulators, and 1M-bit pulse generation table, and input signal parameters include phase shift control information β and a sampling clock clk (l). Wherein, after accumulating beta and the output value alpha of the phase shift register, the index value K of the pulse generation table is generated, and the corresponding table entry value S (K) is output according to the sampling clock Clk (l),i.e. the output value S of the phase-shift control radio frequency pulse width modulatorPWM。
In one embodiment of the invention, the method comprises the following steps:
step 1: the carrier frequency information Fc according to the output signal and the FPGA device can support the highest working frequency FmaxThe number of bits M of the pulse generating module is designed to satisfy the condition of equation (1). The table entry value s (k) of the pulse generation table is designed according to equation (2).
Figure BDA0003491318510000101
The index value K of the pulse generation table is an integer, and K belongs to [0, 2 ]M-1]The table entry value S (K) of the pulse generation table is obtained from the formula (2)
Figure BDA0003491318510000111
Step 2: synthesizing carrier frequency information F of the output signal according to equations (3) and (4)cThe number M of bits of the pulse generation module and the sampling clock phase precision delta theta and other parameter data, and designing the sampling frequency F of the multiple sampling clock generation modulesAnd the number of output clocks, L, and the L resampling clocks are configured according to equation (5).
From carrier frequency information F of the output signalcDetermining the sampling frequency F of the multiple sampling clock generation module according to the bit number M of the pulse generation module and the sampling clock phase precision delta thetasAnd the number of output clocks L, as shown in equations (3) and (4)
Fs＝2M·Fc (3)
Figure BDA0003491318510000112
Wherein INT () represents a rounding operation.
F calculated from the formulas (3) and (4)sAnd L configuring an FPGA clock manager unit to obtain an L resampling clock as shown in the formula(5)
{Clk(l)＝cos(2πFst-l·Δθ)，l∈[0，L]}， (5)
And step 3: for input baseband I, Q signals i (t) and q (t), calculating a phase shift value (psi) corresponding to the output pulse signal according to a phase shift RF-PWM algorithm1(t)，ψ2(t)), and sending the data to a phase quantization decomposition module, wherein the calculation process is shown in equations (6) to (10):
φ(t)＝tan-1(q(t)/i(t)) (6)
Figure BDA0003491318510000113
θ(t)＝cos-1(A(t)/max(A)) (8)
ψ1(t)＝φ(t)+θ(t) (9)
ψ2(t)＝φ(t)-θ(t) (10)
where φ (t) represents the phase value of the input baseband I, Q signal, A (t) represents the envelope value of the input baseband I, Q signal, θ (t) represents the component of the phase-shifted value corresponding to the envelope value, t is the signal sampling time value, and max (A) represents the maximum value of the input signal envelope.
And 4, step 4: combining the phase precision delta theta of the sampling clock and the pulse generator bit number information M, inputting the calculation results into the phase quantization decomposition module according to the expressions (11) to (14), calculating the sampling clock serial number and the pulse generation control word, and respectively sending the calculation results to the multiple sampling clock generation module and the pulse waveform generation module.
Inputting the calculation results according to the equations (9) and (10) to a phase quantization decomposition module, calculating a sampling clock sequence number and a pulse generation control word by combining the phase precision delta theta of the sampling clock and the pulse generator bit number information M, wherein the calculation processes are shown as equations (11) to (14):
β1(t)＝INT(ψ1(t)×2M-1/π) (11)
β2(t)＝INT(ψ2(t)×2M-1/π) (12)
Figure BDA0003491318510000121
Figure BDA0003491318510000122
where REM () represents a remainder operation and ROUND () represents a rounding operation that involves rounding. Beta is a1(t) generating control words, beta, for the pulses corresponding to the baseband I signal2(t) generating control words for the pulses corresponding to the baseband Q signal, l1(t) is the sampling clock number corresponding to the baseband I signal, l2And (t) is the sampling clock sequence number corresponding to the baseband Q signal.
And 5: sending the sampling clock output by the multiple sampling clock generating module obtained according to the formula (15) to the pulse waveform generating module, and sampling and outputting the table entry value of the pulse generating table according to the pulse generating table index value determined by the formula (16)
If the calculation results obtained from equations (11) to (14) are sent to the multi-sampling clock generation module and the pulse waveform generation module, respectively, there are
The output of the multiple sampling clock generation module is:
Figure BDA0003491318510000123
the index value of the pulse generation table of the pulse waveform generation module is as follows:
Figure BDA0003491318510000131
wherein alpha is1And alpha1Respectively output values of phase registers in two pulse waveform generating modules, wherein the pulse waveform generating modules respectively adopt Clk (l)1) And Clk (l)2) Outputting an index value K as a sampling clock1And K2Corresponding pulse generation table entry value S (K)1) Is/are as followsS(K2) I.e. phase-shifted RF-PWM pulse shape SPWM1And SPWM2。
Compared with the radio frequency pulse width modulator in the prior art, the radio frequency pulse width modulator has the following technical advantages:
1. compared with the phase-shifting radio-frequency pulse width modulator based on the digital delay line circuit in the prior art, the phase-shifting radio-frequency pulse width modulator is realized by adopting a general FPGA device, a special digital delay line device and a related configuration circuit are not required to be designed and realized, the modulator structure is simplified, the design cost and the engineering realization difficulty are reduced, and the universality and the realizability of the phase-shifting radio-frequency pulse width modulation technology are improved.
2. Compared with the phase-shifting radio-frequency pulse width modulator based on the analog comparator in the prior art, the phase-shifting radio-frequency pulse width modulator based on the analog comparator completely realizes processing in a digital domain by adopting the universal FPGA device, avoids the processing processes of up-conversion, zero-crossing comparison and the like in the analog domain, saves a series of related complex circuits and devices, simplifies the structure of the modulator, and improves the universality and the reconfigurability of the phase-shifting radio-frequency pulse width modulation technology.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.

Claims (10)

1. A phase shift control radio frequency pulse width modulation method based on FPGA is characterized by comprising the following steps:
obtaining a baseband signal;
determining phase shift control information of output pulses for the baseband signals by using a radio frequency pulse width modulation algorithm;
carrying out phase quantization decomposition on the phase shift control information to obtain a sampling clock sequence number and a pulse generation control word;
obtaining a pulse sampling clock according to the sampling clock serial number, the pulse generator bit number information, the carrier frequency information and the sampling clock phase precision;
and generating a pulse waveform according to the pulse generation control word and the pulse sampling clock to obtain the output of the phase-shift control pulse width modulator.
2. The FPGA-based phase shift control radio frequency pulse width modulation method of claim 1, wherein the phase shift control information has an expression:
ψ1(t)＝φ(t)+θ(t)
ψ2(t)＝φ(t)-θ(t)
wherein psi1(t) and ψ2And (t) respectively represents the phase shift values of the two paths of phase modulation signals, phi (t) represents the phase values of the output baseband I signal and the baseband Q signal, and theta (t) represents the phase shift value component corresponding to the envelope value.
3. The phase shift control radio frequency pulse width modulation method based on the FPGA of claim 1, wherein the phase quantization decomposition is performed on the phase shift control information to obtain a sampling clock sequence number and a pulse generation control word, and specifically comprises:
determining a pulse generation control word according to the phase shift control information and the pulse generator digit information;
and determining the sampling clock serial number according to the phase shift control information, the pulse generator bit number information and the sampling clock phase precision.
4. The FPGA-based phase shift control radio frequency pulse width modulation method of claim 3, wherein the pulse generation control word expression is as follows:
β1(t)＝INT(ψ1(t)×2M-1/π)
β2(t)＝INT(ψ2(t)×2M-1/π)
wherein, beta1(t) and beta2(t) generating control words for the pulses corresponding to the two paths of phase-shift control signals respectively, wherein M is the bit information of the pulse generator, and INT () represents rounding operation;
the expression of the sampling clock sequence number is as follows:
Figure FDA0003491318500000021
Figure FDA0003491318500000022
wherein l1(t) and l2(t) the sampling clock sequence numbers corresponding to the two phase-shift control signals, REM () represents remainder operation, ROUND () represents rounding operation including rounding, psi1(t) and ψ2And (t) respectively representing the phase shift values of the two paths of phase modulation signals, wherein M is the bit information of the pulse generator, and Delta theta is the phase precision of the sampling clock.
5. The phase shift control radio frequency pulse width modulation method based on the FPGA of claim 1, wherein the obtaining of the pulse sampling clock according to the sampling clock sequence number, the pulse generator bit number information, the carrier frequency information, and the sampling clock phase precision specifically comprises:
determining a sampling frequency according to the carrier frequency information and the pulse generator bit number information;
determining the number of multiple sampling clocks according to the bit information of the pulse generator and the phase precision of the sampling clocks;
generating a multiple sampling clock according to the sampling frequency, the multiple sampling clock number and a reference clock;
and determining a pulse sampling clock according to the sampling clock sequence number and the multiple sampling clock.
6. The FPGA-based phase shift control radio frequency pulse width modulation method of claim 5, wherein the sampling frequency has an expression:
Fs＝2M·Fc
wherein, FsFor multiple sampling frequencies of the sampling clock, FcThe carrier frequency information is M, and the pulse generator bit number information is M;
the number of the multiple sampling clocks is
Figure FDA0003491318500000023
Wherein INT () represents a rounding operation, L is the number of multiple sampling clocks, Δ θ is the sampling clock phase accuracyminThe minimum phase interval which can be realized between adjacent sampling clocks in the multiple sampling clocks;
the output of the multisampling clock is:
Figure FDA0003491318500000031
wherein, Clk (l)1) And Clk (l)2) Pulse sampling clocks corresponding to two phase-shift control signals,/1For the sampling clock number, l, corresponding to the baseband I signal2The sampling clock sequence number corresponding to the baseband Q signal, and t is the signal sampling time value.
7. The phase-shift control radio frequency pulse width modulation method based on the FPGA of claim 1, wherein the generating of the pulse waveform according to the pulse generation control word and the pulse sampling clock to obtain the output of the phase-shift control pulse width modulator specifically comprises:
generating a pulse generation table index value by using a phase shift register according to the pulse generation control word;
determining a pulse generation table entry value according to the pulse generation table index value and the sampling clock;
and determining the output of the phase-shift control pulse width modulator according to the table entry value of the pulse generation table.
8. The FPGA-based phase shift control radio frequency pulse width modulation method of claim 7, wherein the expression of the pulse generation table index value is as follows:
Figure FDA0003491318500000032
wherein, K1Generating a table index value, K, for the first pulse2Generating a table index value for the second pulse, M being the pulse generator bit number information, α1And alpha1Respectively the output value beta of the phase register in the two pulse waveform generating modules1And beta2And respectively generating control words for the pulses corresponding to the two paths of phase-shifting control signals, wherein REM () represents remainder calculation.
9. The phase shift control radio frequency pulse width modulation system based on the FPGA is characterized in that the phase shift control radio frequency pulse width modulation system based on the FPGA is arranged on the FPGA, and comprises:
the acquisition module is used for acquiring a baseband signal;
the modulation module is used for determining phase shift control information of output pulses for the baseband signals by utilizing a radio frequency pulse width modulation algorithm;
the phase quantization decomposition module is used for performing phase quantization decomposition on the phase shift control information to obtain a sampling clock sequence number and a pulse generation control word;
the pulse sampling clock determining module is used for obtaining a pulse sampling clock according to the sampling clock serial number, the pulse generator digit information, the carrier frequency information and the sampling clock phase precision;
and the pulse waveform generating module is used for generating a pulse waveform according to the pulse generation control word and the pulse sampling clock to obtain the output of the phase-shift control pulse width modulator.
10. The FPGA-based phase shift controlled rf pulse width modulation system of claim 9, wherein the phase shift control information is expressed as:
ψ1(t)＝φ(t)+θ(t)
ψ2(t)＝φ(t)-θ(t)
wherein psi1(t) and ψ2And (t) respectively represents the phase shift values of the two paths of phase modulation signals, phi (t) represents the phase values of the output baseband I signal and the baseband Q signal, and theta (t) represents the phase shift value component corresponding to the envelope value.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6434194B1 (en) * 1997-11-05 2002-08-13 Wherenet Corp Combined OOK-FSK/PPM modulation and communication protocol scheme providing low cost, low power consumption short range radio link
CN101641931A (en) * 2006-12-18 2010-02-03 艾利森电话股份有限公司 Pulse width modulator

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6434194B1 (en) * 1997-11-05 2002-08-13 Wherenet Corp Combined OOK-FSK/PPM modulation and communication protocol scheme providing low cost, low power consumption short range radio link
CN101641931A (en) * 2006-12-18 2010-02-03 艾利森电话股份有限公司 Pulse width modulator

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
周三文等: "数字可变符号率调制器设计", 遥测遥控, vol. 34, no. 3 *

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