CN114430240A

CN114430240A - Power conversion device and power conversion system

Info

Publication number: CN114430240A
Application number: CN202011176201.9A
Authority: CN
Inventors: 胡茂; 裴轶; 朱永生
Original assignee: Gpower Semiconductor Inc
Current assignee: Gpower Semiconductor Inc
Priority date: 2020-10-28
Filing date: 2020-10-28
Publication date: 2022-05-03

Abstract

The invention discloses a power supply conversion device and a power supply conversion system. The power supply conversion device comprises a direct-current power supply, a first filter network, a first anti-reflux module, a second anti-reflux module, a first switch network, a first bus capacitor, a second switch network, a first electromagnetic isolation module, a second electromagnetic isolation module and a second filter network; the first switch network comprises a first main switch, a second auxiliary switch and a first auxiliary switch which are sequentially connected in series between the positive bus and the negative bus; the second switch network comprises a third main switch, a fourth auxiliary switch and a third auxiliary switch which are sequentially connected in series between the positive bus and the negative bus; the first end of the first bus capacitor is electrically connected with the positive bus, the second end of the first bus capacitor is electrically connected with the first end of the second bus capacitor, and the second end of the second bus capacitor is electrically connected with the negative bus. The invention realizes a three-level power supply conversion device with high reliability and stability by using a simple circuit.

Description

Power conversion device and power conversion system

Technical Field

The embodiment of the invention relates to a power conversion technology, in particular to a power conversion device and a power conversion system.

Background

In new energy power generation and other occasions, such as photovoltaic power generation, wind power generation and the like, a power conversion device (also called an inverter) is a key device for effectively realizing electric energy conversion. In order to realize a wide output voltage range, a conventional power converter generally employs a two-stage or multi-stage power converter.

However, when a three-level output power conversion device is required, the circuit structure becomes more complicated by using a two-stage or multi-stage device, and the reliability, stability, and the like of the power conversion device are poor, which limits the application of the three-level power conversion device.

Disclosure of Invention

The invention provides a power conversion device and a power conversion system, which can realize a three-level power conversion device with high reliability and stability by using a simpler circuit.

In a first aspect, an embodiment of the present invention provides a power conversion apparatus, including:

the system comprises a direct-current power supply, a first filter network, a first anti-reflux module, a second anti-reflux module, a first switch network, a first bus capacitor, a second switch network, a first electromagnetic isolation module, a second electromagnetic isolation module and a second filter network;

the input end of the first filter network is electrically connected with the direct-current power supply, the first output end of the first filter network is electrically connected with the input end of the first anti-backflow module, and the second output end of the first filter network is electrically connected with the output end of the second anti-backflow module;

the first switch network comprises a first main switch, a second auxiliary switch and a first auxiliary switch which are sequentially connected in series between the positive bus and the negative bus; the second switch network comprises a third main switch, a fourth auxiliary switch and a third auxiliary switch which are sequentially connected in series between the positive bus and the negative bus; the first end of the first bus capacitor is electrically connected with the positive bus, and the first bus capacitor and the second bus capacitor are sequentially connected in series between the positive bus and the negative bus;

a first output end of the first anti-backflow module is connected between the first main switch and the second main switch, and a second output end of the first anti-backflow module is connected between the third main switch and the fourth main switch;

a first input end of the second backflow prevention module is connected between the first auxiliary switch and the second auxiliary switch, and a second input end of the second backflow prevention module is connected between the third auxiliary switch and the fourth auxiliary switch;

a first input end of the first electromagnetic isolation module is connected between the first main switch and the second main switch, a second input end of the first electromagnetic isolation module is connected between the first auxiliary switch and the second auxiliary switch, a first output end of the first electromagnetic isolation module is electrically connected with a first input end of the second filtering module, and a second output end of the first electromagnetic isolation module is electrically connected with a second output end of the second electromagnetic isolation module;

a first input end of the second electromagnetic isolation module is connected between the third main switch and the fourth main switch, a second input end of the second electromagnetic isolation module is connected between the third auxiliary switch and the fourth auxiliary switch, and a first output end of the second electromagnetic isolation module is electrically connected with a second input end of the second filter network;

and a first output end and a second output end of the second filter network are used as output ends of the power supply conversion device.

Optionally, the first filter network comprises a first capacitor and a first inductor;

a first end of the first capacitor is used as a first input end of the first filter network, a second end of the first capacitor is used as a second input end and a second output end of the first filter network, the first end of the first capacitor is electrically connected with a first end of the first inductor, and the second end of the first inductor is used as a first output end of the first filter network; and/or the presence of a gas in the gas,

the second filter network comprises a second inductor and a second capacitor; a first end of the second inductor is used as a first input end of the second filter network, a second end of the second inductor is electrically connected with a first end of the second capacitor, a second end of the second inductor is used as a first output end of the second filter network, and a second end of the second capacitor is used as a second output end of the second filter network.

Optionally, the first anti-backflow module includes a first diode and a second diode, an anode of the first diode and an anode of the second diode are electrically connected to serve as an input end of the first anti-backflow module, a cathode of the first diode serves as a first output end of the first anti-backflow module, and a cathode of the second diode serves as a second output end of the first anti-backflow module; and/or the presence of a gas in the gas,

the second anti-reflux module comprises a third diode and a fourth diode, wherein the cathode of the third diode is electrically connected with the cathode of the fourth diode and then is used as the output end of the second anti-reflux module, the anode of the third diode is used as the first input end of the second anti-reflux module, and the anode of the fourth diode is used as the second input end of the second anti-reflux module.

Optionally, the first electromagnetic isolation module is a first transformer; and/or the presence of a gas in the gas,

the second electromagnetic isolation module is a second transformer.

Optionally, a voltage transfer ratio of the first electromagnetic isolation module is greater than or equal to 1, and a voltage transfer ratio of the second electromagnetic isolation module is greater than or equal to 1.

Optionally, at least one of the first main switch, the second main switch, the third main switch, the fourth main switch, the first auxiliary switch, the second auxiliary switch, the third auxiliary switch, and the fourth auxiliary switch is a III-N transistor.

In a second aspect, an embodiment of the present invention further provides a power conversion system, where the power conversion system includes the power conversion device and the switch control module in the first aspect;

the switch control module is used for controlling the first main switch, the second main switch, the third main switch, the fourth main switch, the first auxiliary switch, the second auxiliary switch, the third auxiliary switch and the fourth auxiliary switch to be switched on or switched off.

Optionally, the switch control module includes a first comparator, a second comparator, a third comparator, a fourth comparator, a fifth comparator, a first combinational logic unit, and a second combinational logic unit;

a non-inverting input end of the first comparator inputs a first modulated wave signal, an inverting input end of the first comparator inputs a first carrier signal, and an output end of the first comparator is electrically connected with a third input end of the first combinational logic unit; the first modulation wave signal is a sine signal, and the first carrier wave signal is a sawtooth wave signal;

a non-inverting input end of the second comparator inputs a second modulated wave signal, an inverting input end of the second comparator inputs a first carrier signal, and an output end of the second comparator is electrically connected with a second input end of the first combinational logic unit; the second modulation wave signal is a direct current signal;

a non-inverting input end of the third comparator inputs a first modulated wave signal, an inverting input end of the third comparator inputs a second carrier signal, and an output end of the third comparator is electrically connected with a third input end of the second combinational logic unit; the second carrier signal is a sawtooth wave signal;

a non-inverting input end of the fourth comparator inputs a second modulated wave signal, an inverting input end of the fourth comparator inputs a second carrier signal, and an output end of the fourth comparator is electrically connected with a second input end of the second combinational logic unit;

a first modulation wave signal is input to a non-inverting input end of the fifth comparator, a reference ground signal of the switch control module is input to an inverting input end of the fifth comparator, and an output end of the fifth comparator is electrically connected with first input ends of the first combination logic unit and the second combination logic unit;

the first output end, the second output end, the third output end and the fourth output end of the first combination logic unit are respectively and electrically connected with the control end of the second main switch, the control end of the first main switch, the control end of the fourth main switch and the control end of the third main switch, and the logic function of the first combination logic unit is as follows:

Vgs2＝(Vzero'·Vspwm1)'·Vpwm1；Vgs1＝Vgs2'；

Vgs4＝(Vzero·Vspwm1)'·Vpwm1；Vgs3＝Vgs4'；

vgs2, Vgs1, Vgs4 and Vgs3 are signals output from the first output terminal, the second output terminal, the third output terminal and the fourth output terminal of the first combinational logic unit, respectively, and Vzero, Vpwm1 and Vspwm1 are signals input from the first input terminal, the second input terminal and the third input terminal of the first combinational logic unit, respectively;

the first output end, the second output end, the third output end and the fourth output end of the second combinational logic unit are respectively and electrically connected with the control end of the second auxiliary switch, the control end of the first auxiliary switch, the control end of the fourth auxiliary switch and the control end of the third auxiliary switch, and the logic function of the second combinational logic unit is as follows:

Vgsub2＝(Vzero'·Vspwm2)'·Vpwm2；Vgsub1＝Vgsub2'；

Vgsub4＝(Vzero·Vspwm2)'·Vpwm2；Vgsub3＝Vgsub4'；

wherein Vgsub2, Vgsub1, Vgsub4 and Vgsub3 are signals output by the first output terminal, the second output terminal, the third output terminal and the fourth output terminal of the second combinational logic unit, respectively, and Vzero, Vpwm2 and Vspwm2 are signals input by the first input terminal, the second input terminal and the third input terminal of the second combinational logic unit, respectively.

Optionally, the first combinational logic unit includes a first nand gate, a second nand gate, a third nand gate, a fourth nand gate, a first and gate, and a second and gate;

the first input end of the first NAND gate and the first input end of the second NAND gate are electrically connected with the first input end of the first combinational logic unit, wherein the first input end of the first NAND gate is an inverting input end, the second input ends of the first NAND gate and the second NAND gate are electrically connected with the third input end of the first combinational logic unit, the output end of the first NAND gate is electrically connected with the first input end of the third NAND gate and the first input end of the first AND gate, the output end of the second NAND gate is electrically connected with the first input end of the fourth NAND gate and the first input end of the second AND gate, the second input end of the first combinational logic unit is electrically connected with the second input end of the first AND gate, the second input end of the third NAND gate, the second input end of the second AND gate and the second input end of the fourth NAND gate; the output end of the first AND gate is electrically connected with the control end of the second main switch, the output end of the third NAND gate is electrically connected with the control end of the first main switch, the output end of the second AND gate is electrically connected with the control end of the fourth main switch, and the output end of the fourth NAND gate is electrically connected with the control end of the third main switch; and/or the presence of a gas in the gas,

the second combined logic unit comprises a fifth NAND gate, a sixth NAND gate, a seventh NAND gate, an eighth NAND gate, a third AND gate and a fourth AND gate;

the first input end of the fifth NAND gate and the first input end of the sixth NAND gate are electrically connected with the first input end of the second combinational logic unit, wherein the first input end of the fifth NAND gate is an inverting input end, the second input end of the fifth NAND gate and the second input end of the sixth NAND gate are electrically connected with the third input end of the second combinational logic unit, the output end of the fifth NAND gate is electrically connected with the first input end of the seventh NAND gate and the first input end of the third AND gate, the output end of the sixth NAND gate is electrically connected with the first input end of the eighth NAND gate and the first input end of the fourth AND gate, a second input end of the second combinational logic unit is electrically connected with a second input end of the third and gate, a second input end of the seventh nand gate, a second input end of the fourth and gate and a second input end of the eighth nand gate; the output end of the third and gate is electrically connected with the control end of the second auxiliary switch, the output end of the seventh nand gate is electrically connected with the control end of the first auxiliary switch, the output end of the fourth and gate is electrically connected with the control end of the fourth auxiliary switch, and the output end of the eighth nand gate is electrically connected with the control end of the third auxiliary switch.

Optionally, the phase difference between the first carrier signal and the second carrier signal is 180 degrees.

According to the technical scheme of the embodiment of the invention, the adopted power conversion device controls the power conversion device to switch among three output levels by controlling the conduction state of each switch, namely three-level output can be realized, and only one-level power conversion control is needed because diodes clamped by midpoint voltages of a front level and a rear level are not needed, so that the control structure is simple, the design cost of the power conversion device is reduced, and the cost performance and the integration level of the power conversion device are improved.

Drawings

Fig. 1 is a schematic circuit diagram of a power conversion device according to an embodiment of the present invention;

fig. 2 is a modulation waveform diagram of a power conversion apparatus according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a first node potential difference and a second node potential difference;

fig. 4-9 are schematic views of the working modes of the power conversion device;

fig. 10 is a modulation waveform diagram of another power conversion apparatus according to an embodiment of the present invention;

fig. 11-16 are operation mode diagrams of the power conversion device;

fig. 17-19 are schematic structural diagrams of switches provided by embodiments of the present invention;

FIGS. 20-21 are schematic structural views of electrical connections for III N diodes provided by embodiments of the present invention;

fig. 22-23 are plan sectional views of III N diode package structures provided by embodiments of the present invention;

fig. 24 to 26 are graphs showing experimental results of the power conversion apparatus according to the embodiment of the present invention;

fig. 27 is a schematic circuit diagram of a power conversion system according to an embodiment of the present invention;

fig. 28 is a flowchart of a control method of a power conversion system according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Fig. 1 is a schematic circuit structure diagram of a power conversion device according to an embodiment of the present invention, and referring to fig. 1, the power conversion device includes: the system comprises a direct current power supply Uin, a first filter network 101, a first anti-reflux module D1, a second anti-reflux module D2, a first switch network 102, a first bus capacitor Cbus1, a second bus capacitor Cbus2, a second switch network 103, a first electromagnetic isolation module T1, a second electromagnetic isolation module T2 and a second filter network 104;

a first input end of the first filter network 101 is electrically connected with a positive electrode of the direct-current power supply Uin, a second input end of the first filter network 101 is electrically connected with a negative electrode of the direct-current power supply Uin, a first output end of the first filter network 101 is electrically connected with an input end of the first anti-backflow module D1, and a second output end of the first filter network 101 is electrically connected with an output end of the second anti-backflow module D2;

the first switching network 102 comprises a first main switch S1, a second main switch S2, a second auxiliary switch Ssub2 and a first auxiliary switch Ssub1 connected in series in sequence between a positive bus V + and a negative bus V-; the second switching network 103 comprises a third main switch S3, a fourth main switch S4, a fourth auxiliary switch Ssub4 and a third auxiliary switch Ssub3 connected in series in sequence between the positive bus V + and the negative bus V-; a first end of the first bus capacitor Cbus1 is electrically connected with a positive bus V +, a second end of the first bus capacitor Cbus1 is electrically connected with a first end of the second bus capacitor Cbus2, and a second end of the second bus capacitor Cbus2 is electrically connected with a negative bus V-;

a first output end of the first anti-backflow module D1 is connected between the first main switch S1 and the second main switch S2, a second output end of the first anti-backflow module D1 is connected between the third main switch S3 and the fourth main switch S4, and the first anti-backflow module D1 is configured to prevent current from flowing from the output end to the input end;

a first input terminal of the second reverse flow prevention module D2 is connected between the first auxiliary switch Ssub1 and the second auxiliary switch Ssub2, a second input terminal of the second reverse flow prevention module D2 is connected between the third auxiliary switch Ssub3 and the fourth auxiliary switch Ssub4, and the second reverse flow prevention module is configured to prevent current from flowing from its output terminal to its input terminal;

a first input end of the first electromagnetic isolation module T1 is connected between the first main switch S1 and the second main switch S2, a second input end of the first electromagnetic isolation module T1 is connected between the first auxiliary switch Ssub1 and the second auxiliary switch Ssub2, a first output end of the first electromagnetic isolation module T1 is electrically connected with a first input end of the second filtering module 104, and a second output end of the first electromagnetic isolation module T1 is electrically connected with a second output end of the second electromagnetic isolation module T2;

a first input terminal of the second electromagnetic isolation module T2 is connected between the third main switch S3 and the fourth main switch S4, a second input terminal of the second electromagnetic isolation module T2 is connected between the third auxiliary switch Ssub3 and the fourth auxiliary switch Ssub4, and a first output terminal of the second electromagnetic isolation module T2 is electrically connected to a second input terminal of the second filter network 104;

the first output terminal and the second output terminal of the second filter network 104 are used as the output terminals of the power transforming apparatus.

Specifically, the first filtering module 101 may be configured to filter a signal generated by the dc power source Uin, and the first backflow prevention module D1 may prevent a current between the first main switch S1 and the second main switch S2 from flowing between the third main switch S3 and the fourth main switch S4; the second reverse flow prevention module D2 may prevent current between the first and second auxiliary switches Ssub1 and Ssub2 from flowing between the third and fourth auxiliary switches Ssub3 and Ssub 4; the first main switch S1, the second main switch S2, the third main switch S3, the fourth main switch S4, the first auxiliary switch Ssub1, the second auxiliary switch Ssub2, the third auxiliary switch Ssub3, and the fourth auxiliary switch Ssub4 can be turned on or off under the action of control signals input by respective control terminals, in this embodiment, the states of the switches can be controlled, so that the voltage between two input terminals of the second filter network 104 (the voltage between the first node N and the second node L) includes three levels, and then harmonics are filtered by the filtering action of the second filter network 104, so that a relatively pure ac signal is obtained on the external load R. Illustratively, when the second main switch S2, the third main switch S3, the second auxiliary switch Ssub2 and the third auxiliary switch Ssub3 are turned on and the other switches are turned off, the first bus capacitor Cbus1 and the second bus capacitor Cbus2 can provide energy to the output side through the third main switch S3, the third auxiliary switch Ssub3 and the second electromagnetic isolation module T2, and the potential difference VNL between the first node N and the second node L is the bus voltage-Vbus ═ Vcbus1+ Vcbus 2; the first bus capacitor Csub1 and the second bus capacitor Csub2 are both large enough and have negligible voltage ripples, and there are Vcubs1 ═ Vcbus2 ═ 1/2) Vbus, where Vcubs1 is the voltage across the first bus capacitor Cbus1 and Vcbus2 is the voltage across the second bus capacitor Cbus 2; when the second main switch S2, the third main switch S3, the second auxiliary switch Ssub2 and the fourth auxiliary switch Ssub4 are controlled to be turned on and the other switches are turned off, VNL equal to-Vcubs 1 can be obtained; when the second main switch S2, the fourth main switch S4, the second auxiliary switch Ssub2, and the fourth auxiliary switch Ssub4 are turned on and the other switches are turned off, the VNL potential difference is clamped to zero; that is, the voltage between the first node N and the second node L has three states of-Vbus, - (1/2) Vbus and 0, i.e., the circuit implements the output voltage three-level function. Compared with a three-level power supply conversion device such as a diode clamp, the three-level power supply conversion device has a simple circuit structure, the traditional two-stage structure needs to simultaneously realize neutral point voltage clamping and other control of a front stage and a rear stage, and the control structure is complex; the power conversion device of the embodiment only needs to realize the control of one-level power conversion, and has a simple control structure, thereby reducing the design cost of the power conversion device and improving the cost performance and the integration level of the power conversion device.

According to the technical scheme of the embodiment, the adopted power conversion device controls the power conversion device to switch among three output levels by controlling the conduction state of each switch, namely three-level output can be realized, and only one-level power conversion control is needed due to the fact that diodes of front-stage and rear-stage midpoint voltage clamps are not needed, the control structure is simple, the design cost of the power conversion device is reduced, and the cost performance and the integration level of the power conversion device are improved.

Exemplarily, the first filter network 101 includes a first capacitor Cin and a first inductor Lin, a first end of the first capacitor Cin is used as a first input end of the first filter network 101, a second end of the first capacitor Cin is used as a second input end and a second output end of the first filter network 101, the first end of the first capacitor Cin is electrically connected to the first end of the first inductor Lin, and the second end of the first inductor Lin is used as a first output end of the first filter network 101; and/or the second filter network 104 includes a second inductor Lo and a second capacitor Lo, a first end of the second inductor Lo is used as a first input end of the second filter network 104, a second end of the second inductor Lo is electrically connected to a first end of the second capacitor Co, a second end of the second inductor Lo is used as a first output end of the second filter network 104, and a second end of the second capacitor Co is used as a second output end of the second filter network 104.

Specifically, in this embodiment, the first filter network 101 and the second filter network 104 may both adopt LC filter circuits, and the LC filter circuits have the advantages of high stability, good filtering effect, low dc loss, and the like, and are more favorable for stable operation of the power conversion device.

Optionally, the first anti-backflow module D1 includes a first diode D11 and a second diode D12, an anode of the first diode D11 is electrically connected to an anode of the second diode D12 and then serves as an input end of the first anti-backflow module D1, a cathode of the first diode D11 serves as a first output end of the first anti-backflow module D1, and a cathode of the second diode D12 serves as a second output end of the first anti-backflow module D1; and/or the second anti-backflow module D2 includes a third diode D21 and a fourth diode D22, a cathode of the third diode D21 is electrically connected to a cathode of the fourth diode D22 and then serves as an output end of the second anti-backflow module D2, an anode of the third diode D21 serves as a first input end of the second anti-backflow module D2, and an anode of the fourth diode D22 serves as a second input end of the second anti-backflow module D2. The first electromagnetic isolation module T1 is a first transformer and/or the second electromagnetic isolation module T2 is a second transformer.

Specifically, the diode has the effect of unidirectional conduction, has the advantages of low cost, good stability and the like, and can be used as the anti-reflux module, so that the stability of the power supply conversion device can be further improved, and the overall cost of the power supply conversion device is reduced.

The following describes the operation of the power converter in detail; as shown in fig. 2, fig. 2 is a modulation waveform diagram of a power converter according to an embodiment of the present invention, which may correspond to a first time period in a positive half cycle of a sine, in this embodiment, the positive half cycle of the sine is divided into three time periods for introduction, as shown in fig. 3, and fig. 3 is a schematic diagram of a potential difference between a first node and a second node; wherein, positionA corresponds to a first time period, and PositionB and PositionC correspond to a second time period and a third time period, and when the modulation wave changes, the time ratio of the first time period, the second time period and the third time period may change.

In the present embodiment, in conjunction with fig. 2 and 3, the first modulation wave signal Vsine, the first carrier signal Vtri1, the second modulation wave signal Vdc and a reference ground signal (not shown) may be first supplied, and then the above signals are passed through a logic circuit such as a comparator to generate the first sinusoidal pulse width signal Vspwm1, the first fixed pulse width signal Vpwm1, the zero-crossing point detection signal Vzero (not shown), and the output drive signals Vgs1 to Vgs4 of the first to fourth main switches are generated through combinational logic (to be described in detail later). Similarly, the second sinusoidal pulse width signal Vspwm2, the second fixed pulse width signal Vpwm2 and the zero-crossing point detection signal Vzero may be generated by a logic circuit such as a comparator through the first modulated wave signal Vsine, the second carrier signal Vtri2, the second modulated wave signal Vdc and the ground reference signal of the switching control module, and the driving signals Vgsub1 to Vgsub4 of the first to fourth auxiliary switches are generated by combinational logic. Here, the high-level conduction of each switch will be described as an example. The first modulation wave signal Vsine is a sine wave, and the frequency of the first modulation wave signal Vsine can be adjusted according to the frequency required by the output load, and if the power conversion device is finally connected to the mains supply, the frequency of the first modulation wave signal Vsine can be set to be 50 Hz; the second modulated wave signal Vdc is a direct current signal, and the first carrier signal Vtri1 and the second carrier signal Vtri2 are both sawtooth waves having frequencies much higher than the frequency of the first modulated wave signal Vsine, and illustratively, the frequencies of the first carrier signal Vtri1 and the second carrier signal Vtri2 are both higher than 100 kHz.

Fig. 4-9 are schematic diagrams of operation modes of the power conversion apparatus, which may sequentially correspond to the mode 1, i.e., [ t0-t1] time period, the mode 2, i.e., [ t1-t2] time period, the mode 3, i.e., [ t2-t3] time period, the mode 4, i.e., [ t3-t4] time period, the mode 5, i.e., [ t4-t5] time period, and the mode 6, i.e., [ t5-t5] time period in fig. 2; referring to fig. 4, during the time period, the second main switch S2, the third main switch S3, the second auxiliary tube Ssub2 and the third auxiliary switch Ssub3 are turned on, on one hand, the dc power source Uin charges the first inductor Lin through the second switch S2 and the second auxiliary switch Ssub2, the first inductor Lin stores energy, and the inductor current gradually rises; on the other hand, the first bus capacitor Cbus1 and the second bus capacitor Cbus2 supply energy to the output side through the third main switch S3, the third auxiliary switch Ssub3 and the second electromagnetic isolation module T2. The potential difference VNL between the output nodes N and L is equal to the bus voltage-Vbus ═ - (Vcbus1+ Vcbus2), the voltage of the first main switch S1 is equal to Vcbus1, the voltage of the first auxiliary switch Ssub1 is equal to Vcbus2, the voltage of the fourth main switch S4 is equal to Vcbus1, and the voltage of the fourth auxiliary switch Ssub4 is equal to Vcbus 2.

Referring to fig. 5, in this time period, i.e. mode 2, the second main switch S2, the third main switch S3, the second auxiliary switch Ssub2 and the fourth auxiliary switch Ssub4 are turned on, on the one hand, the dc power source Uin charges the first inductor Lin from the first path through the second main switch S2 and the second auxiliary switch Ssub2, and charges the first inductor Lin from the second path through the second main switch S2 and the fourth auxiliary switch Ssub4, the first inductor Lin stores energy, and the inductor current continues to gradually rise; on the other hand, the first bus capacitor Cbus1 supplies energy to the output side via the third main switch S3, the fourth main switch Ssub4 and the second electromagnetic isolation module T2. The potential difference VNL between the output nodes N and L is equal to the first bus capacitor voltage-Vcbus 1, the voltage of the first main switch S1 is equal to Vcbus1, the voltage of the first auxiliary switch Ssub1 is equal to Vcbus2, the voltage of the fourth main switch S4 is equal to Vcbus1, and the voltage of the third auxiliary switch Ssub3 is equal to Vcbus 2.

Referring to fig. 6, during the time period, i.e. mode 3, the second main switch S2, the third main switch S3, the first auxiliary switch Ssub1 and the third auxiliary switch Ssub3 are turned on, on one hand, the first inductor Lin is subjected to a reverse voltage drop (Vcbus2-Uin), energy begins to be released, the inductor current gradually drops, and the first bus capacitor Cbus1 and the second bus capacitor Cbus2 are charging, so that the bus voltage is kept balanced; on the other hand, the first bus capacitor Cbus1 and the second bus capacitor Cbus2 supply energy to the output side through the third main switch S3, the third auxiliary switch Ssub3 and the second electromagnetic isolation module T2. The potential difference VNL between the output nodes N and L is equal to the first bus capacitor voltage-Vcbus 1, the voltage of the first main switch S1 is equal to Vcbus1, the voltage of the second auxiliary switch Ssub2 is equal to Vcbus2, the voltage of the fourth main switch S4 is equal to Vcbus1, and the voltage of the fourth auxiliary switch Ssub4 is equal to Vcbus 2.

Referring to fig. 7, during this time period, i.e., mode 4, the switching state of each switch substantially coincides with mode 1. The potential difference VNL between the output nodes N and L is equal to the bus voltage-Vbus ═ - (Vcbus1+ Vcbus2), the voltage of the first main switch S1 is equal to Vcbus1, the voltage of the second auxiliary switch Ssub2 is equal to Vcbus2, the voltage of the fourth main switch S4 is equal to Vcbus1, and the voltage of the fourth auxiliary switch Ssub4 is equal to Vcbus 2.

Referring to fig. 8, in this phase, i.e. mode 5, the second main switch S2, the fourth main switch S4, the second auxiliary switch Ssub2 and the third auxiliary switch Ssub3 are turned on, on one hand, the dc power source Uin charges the first inductor Lin through the second main switch S2 and the second auxiliary switch Ssub2, the first inductor Lin stores energy, and the inductor current gradually rises; on the other hand, the second bus capacitor Cbus2 supplies energy to the output side via the fourth main switch S4, the third auxiliary switch Ssub3 and the second electromagnetic isolation module T2. The potential difference VNL between the output nodes N and L is equal to the second bus capacitor voltage-Vcbus 2, the voltage of the first main switch S1 is equal to Vcbus1, the voltage of the first auxiliary switch Ssub1 is equal to Vcbus2, the voltage of the third main switch S3 is equal to Vcbus1, and the voltage of the fourth auxiliary switch Ssub4 is equal to Vcbus 2.

Referring to fig. 9, in this phase, mode 6, the first main switch S1, the third main switch S3, the second auxiliary switch Ssub2 and the third auxiliary switch Ssub3 are turned on, on one hand, the first inductor Lin is subjected to a reverse voltage drop (Vcbus1-Uin), energy begins to be released, the inductor current gradually decreases, and the first bus capacitor Cbus1 and the second bus capacitor Cbus2 are charging, so that the bus voltage is kept balanced; on the other hand, the first bus capacitor Cbus1 and the second bus capacitor Cbus2 supply energy to the output side through the third main switch S3, the third auxiliary switch Ssub3 and the second electromagnetic isolation module T2. The potential difference VNL between the output nodes N and L is equal to the second bus capacitor voltage-Vcbus 2, the voltage of the second main switch S2 is equal to Vcbus1, the voltage of the first auxiliary switch Ssub1 is equal to Vcbus2, the voltage of the fourth main switch S4 is equal to Vcbus1, and the voltage of the fourth auxiliary switch Ssub4 is equal to Vcbus 2.

At this point, when the modulation wave is at the position of positive half cycle position of sine, the three-level power supply conversion device sequentially and repeatedly completes the six working modes, so that the input low-voltage direct-current electric energy is uninterruptedly converted into high-voltage alternating-current electric energy and is output to a rear-stage load. In this position (PositionA), the potential difference VNL between the output nodes N and L takes two values, -Vbus and- (1/2) Vbus.

Fig. 10 is a modulation waveform diagram of another power converter according to an embodiment of the present invention, which may correspond to position b and position c time periods of a positive half cycle of a sine, fig. 11-16 are operation mode diagrams of the power converter, which may sequentially correspond to mode 1 in fig. 10, i.e., [ t0-t1] time period, mode 2, i.e., [ t1-t2] time period, mode 3, i.e., [ t2-t3] time period, mode 4, i.e., [ t3-t4] time period, mode 5, i.e., [ t4-t5] time period, and mode 6, i.e., [ t5-t5] time period;

referring to fig. 11, in this phase, i.e. mode 1, the second main switch S2, the third main switch S3, the second auxiliary switch Ssub2 and the fourth auxiliary switch Ssub4 are turned on, on one hand, the first inductor Lin is charged by the first direct current power source Uin from the first path through the second main switch S2 and the second auxiliary switch Ssub2, and is charged from the second path through the second main switch S2 and the fourth auxiliary switch Ssub4, the first inductor Lin stores energy, and the inductor current gradually rises; on the other hand, the first bus capacitor Cbus1 supplies energy to the output side via the third main switch S3, the fourth auxiliary switch Ssub4 and the second electromagnetic isolation module T2. The potential difference VNL between the output nodes N and L is equal to the first bus capacitor voltage-Vcbus 1, the voltage of the first main switch S1 is equal to Vcbus1, the voltage of the first auxiliary switch Ssub1 is equal to Vcbus2, the voltage of the fourth main switch S4 is equal to Vcbus1, and the voltage of the third auxiliary switch Ssub3 is equal to Vcbus 2.

Referring to fig. 12, at this stage, modes 2[ t1-t2 ]: the second main switch S2, the fourth main switch S4, the second auxiliary switch Ssub2 and the fourth auxiliary switch Ssub4 are turned on, on one hand, the direct-current power source Uin charges the first inductor Lin through the second main switch S2 and the second auxiliary switch Ssub2 through a first path, and charges the first inductor Lin through the fourth main switch S4 and the fourth auxiliary switch Ssub4 through a second path, the first inductor Lin stores energy, and the inductor current continues to gradually rise; on the other hand, the potential difference VNL between the output nodes N and L is clamped equal to zero, the voltage of the first main switch S1 is equal to Vcbus1, the voltage of the first auxiliary switch Ssub1 is equal to Vcbus2, the voltage of the third main switch S3 is equal to Vcbus1, and the voltage of the third auxiliary switch Ssub3 is equal to Vcbus 2.

Referring to fig. 13, at this stage, modality 3[ t2-t3 ]: the second main switch S2, the fourth main switch S4, the first auxiliary switch Ssub1 and the third auxiliary switch Ssub3 are turned on, on one hand, the first inductor Lin bears a reverse voltage drop (Vcbus2-Uin), energy begins to be released, the inductor current gradually drops, the second bus capacitor Cbus2 is charged, and the bus voltage balance is maintained; on the other hand, the potential difference VNL between the output nodes N and L is clamped equal to zero, the voltage of the first main switch S1 is equal to Vcbus1, the voltage of the second auxiliary switch Ssub2 is equal to Vcbus2, the voltage of the third main switch S3 is equal to Vcbus1, and the voltage of the fourth auxiliary switch Ssub4 is equal to Vcbus 2.

Referring to fig. 14, at this stage, modality 4[ t3-t4 ]: the second main switch S2, the fourth main switch S4, the second auxiliary switch Ssub2 and the third auxiliary switch Ssub3 are turned on, on one hand, the direct-current power source Uin charges the first inductor Lin through the second main switch S2 and the second auxiliary switch Ssub2, the first inductor Lin stores energy, and the inductor current gradually rises; on the other hand, the second bus capacitor Cbus2 supplies energy to the output side via the fourth main switch S4, the third auxiliary switch Ssub3 and the second electromagnetic isolation module T2. The potential difference VNL between the output nodes N and L is equal to the second bus capacitor voltage-Vcbus 2, the voltage of the first main switch S1 is equal to Vcbus1, the voltage of the first auxiliary switch Ssub1 is equal to Vcbus2, the voltage of the third main switch S3 is equal to Vcbus1, and the voltage of the fourth auxiliary switch Ssub4 is equal to Vcbus 2.

Referring to fig. 15, at this stage, modes 5[ t4-t5 ]: the switching state of each switch substantially coincides with mode 2. The potential difference VNL between the output nodes N and L is clamped equal to zero, the voltage of the first main switch S1 is equal to Vcbus1, the voltage of the first auxiliary switch Ssub1 is equal to Vcbus2, the voltage of the third main switch S3 is equal to Vcbus1, and the voltage of the third auxiliary switch Ssub3 is equal to Vcbus 2.

Referring to fig. 16, at this stage, modality 6[ t5-t 6 ]: the first main switch S1, the third main switch S3, the second auxiliary switch Ssub2 and the fourth auxiliary switch Ssub4 are turned on, on one hand, the first inductor Lin bears a reverse voltage drop (Vcbus1-Uin), energy begins to be released, the inductor current gradually drops, the first bus capacitor Cbus1 is charged, and the bus voltage balance is maintained; on the other hand, the potential difference VNL between the output nodes N and L is clamped equal to zero, the voltage of the second main switch S2 is equal to Vcbus1, the voltage of the first auxiliary switch Ssub1 is equal to Vcbus2, the voltage of the fourth main switch S4 is equal to Vcbus1, and the voltage of the third auxiliary switch Ssub3 is equal to Vcbus 2.

At this point, when the modulation wave is at the position of posion b or posion c of the sine positive half cycle, the power conversion device sequentially and repeatedly completes the six working modes, so that the input low-voltage direct-current electric energy is uninterruptedly converted into high-voltage alternating-current electric energy and is output to a rear-stage load. In this position, the potential difference VNL between the output nodes N and L takes two values, Vbus- (1/2) and 0.

In summary, no matter what state the power conversion device works in, the voltage stress of the main switch and the auxiliary switch is half of the bus voltage Vbus, and the potential difference VNL between the output nodes N and L has three states of-Vbus, - (1/2) Vbus and 0, i.e. the circuit realizes the output voltage three-level function. In addition, the current ripple frequency of the first inductor Lin and the current ripple frequency of the second inductor Lo are both 2 times the frequency of the first carrier signal Vtri1 (or the second carrier signal Vtri 2).

At least one of the first main switch S1, the second main switch S2, the third main switch S3, the fourth main switch S4, the first auxiliary switch Ssub1, the second auxiliary switch Ssub2, the third auxiliary switch Ssub3, and the fourth auxiliary switch Ssub4 is a III-N transistor.

In particular, the III-N transistor may be, for example, a Field Effect Transistor (FET), such as a High Electron Mobility Transistor (HEMT), a Heterojunction Field Effect Transistor (HFET), a POLFET, JFET, MESFET, CAVET, or any other III-N transistor structure suitable for power switching applications.

In some embodiments, fig. 17-19 are schematic structural diagrams of switches provided by embodiments of the invention, and as shown in fig. 17, the III-N transistor is an enhancement-mode (E-mode) device, i.e., a normally-off device, such that the threshold voltage is greater than 0V, e.g., about 1.5V-2V or greater than 2V, and the enhancement-mode (E-mode) device does not include a reverse body diode, which can reduce conduction loss of the power supply apparatus when the device freewheels in a reverse direction. The III-N transistor is formed by cascading a high voltage III-N depletion (D-type) transistor, which is a normally-on device such that the threshold voltage is less than 0V, and a low voltage enhancement (E-type) transistor, which is a low voltage Si MOS device, as shown in fig. 18, and in some embodiments, the III-N transistor of fig. 18 further includes an external reverse parallel diode for reducing the device reverse recovery loss, as shown in fig. 19.

In some embodiments, the III-N transistor is a high voltage switching transistor. As used herein, a high voltage switching transistor is a transistor optimized for high voltage switching applications. That is, when the transistor is off, it is able to block high voltages, such as about 300V, or more about 600V, or more about 1200V, or more, and when the transistor is on, it has a sufficiently low on-resistance (Rdson) for the above-mentioned applications, i.e., when a large amount of current is passed through the device, a lower on-loss is achieved.

Both the first and second anti-reflux modules D1 and D2 may employ III N rectifying devices, which may be at least two lateral III N diodes having an insulating or semi-insulating portion on opposite sides of the semiconductor body with respect to all electrodes. The III N diode includes an insulating or semi-insulating portion, a semiconductor body including a III N buffer layer (such as GaN) and a III N barrier layer (such as AlGaN), a two-dimensional electron gas (2DEG) channel, an anode contact contacting the semiconductor body on opposite sides of the insulating or semi-insulating portion and forming a schottky contact with the semiconductor material of the semiconductor body, and a cathode contact forming an ohmic contact with the 2DEG channel. The III-N diode may optionally include a conductive or semiconductive portion, such as a silicon substrate.

Fig. 20-21 are schematic structural diagrams of electrical connections of III N diodes provided by embodiments of the present invention, and in some embodiments, the III N diodes in the III N rectifying device may be in a common anode connection manner, as shown in fig. 20, including an input terminal a1 and two output terminals K1 and K2, or in a common cathode connection manner, as shown in fig. 21, including two input terminals a1, a2 and an output terminal K1.

Fig. 22-23 are cross-sectional plan views of III N diode package structures provided by embodiments of the invention, in some embodiments the III N rectifying device is formed by two independently packaged III N diodes and electrically connected externally, the independently packaged III N diodes being as shown in fig. 22, and the plan view of fig. 22 illustrating portions of the package and the electronic device packaged or encapsulated in the package. The electronic component 90 includes a single III-N diode 22 encapsulated, wrapped or sealed in a separate package. The individual packages include a plurality of sealing structure portions, such as package base 94, and non-structure portions, such as

pins

91, 92, and 93. As used herein, a "structural portion" of a package is a portion that forms the basic shape or form of the package and provides the structural rigidity of the package required to protect the enclosed device. In most cases, when electronic components including packages are used in discrete circuits, the structural portions of the packages are mounted directly to the circuit or circuit board. In the stand-alone package of fig. 22, the package base 94 is formed of a conductive material, i.e., the package base 94 is a conductive structural portion of the package. The single package includes at least two pins, an anode pin 91 and a cathode pin 93, and optionally at least one other pin, such as an open pin 92. Pins 9193 are all formed from a conductive material. When open pin 92 is included, it may be electrically connected to package base 94 or electrically isolated from package base 94, and all other pins are electrically isolated from the package base. As used herein, two or more contacts or other items are said to be "electrically connected" if they are connected by a material that is sufficiently conductive to ensure that the potential at each of the contacts or other items is always the same, i.e., approximately the same, under any bias conditions.

When III N diode 22 is used in a III N rectifying device, III N diode 22 is mounted inside a single package and connected as follows, an electrical bond wire 3839, which may be a single or multiple wire bonds, is used to electrically connect portions of the package and III N diode 22 to each other. With the corresponding insulating or semi-insulating substrate of III-N diode 22 in contact with package base 94. Cathode contact 29 of III-N diode 22 is electrically connected to a conductive structural portion of the package, such as package base 94, or may otherwise be electrically connected to a cathode lead 93 of the package, such as by a conductive bond wire 39. Anode contact 28 of III N diode 22 is electrically connected to an anode lead 91 of the package, such as by a conductive bond wire 38.

In some other embodiments, the III N rectifying device is a dual-barreled package of III N diodes, as shown in fig. 23, the plan view of fig. 23 illustrating portions of the package and the electronic devices encapsulated or encapsulated in the package. The electronic component 90 'includes a III N diode 22 and a III N diode 22' both encapsulated, enveloped, or sealed in a dual tube package. The dual tube package includes a plurality of sealing structure portions, such as package base 94, and non-structure portions, such as

pins

91, 92 and 93. As used herein, a "structural portion" of a package is a portion that forms the basic shape or form of the package and provides the structural rigidity of the package required to protect the enclosed device. In most cases, when electronic components including packages are used in discrete circuits, the structural portions of the packages are mounted directly to the circuit or circuit board. In a dual-tube package, the package base 94 is formed of a conductive material, i.e., the package base 94 is a conductive structural portion of the package. A single package includes at least three pins, an anode pin 91, an anode pin 93, and a common cathode pin 92. Pins 9193 are all formed from a conductive material. The common cathode lead 92 may be electrically connected to the package base 94 or electrically isolated from the package base 94, and all other leads are electrically isolated from the package base. As used herein, two or more contacts or other items are said to be "electrically connected" if they are connected by a material that is sufficiently conductive to ensure that the potential at each of the contacts or other items is always the same, i.e., approximately the same, under any bias conditions.

When III N diodes are used in the III N rectifying device, III N diodes 22 and 22 ' are mounted inside a dual-tube package and connected as follows,

electrical bond wires

38, 38 ', 39, which may be single or multiple wire bonds, are used to electrically connect portions of the package, III N diodes 22, and III N diodes 22 ' to each other. Wherein the respective insulating or semi-insulating substrates of III N diode 22 and III N diode 22' are both in contact with package base 94. Cathode contact 29 of III N diode 22 and cathode contact 29 'of III N diode 22' are electrically connected to a conductive structural portion of the package, such as package base 94, and are additionally electrically connected to common cathode lead 92 of the package by conductive bond wire 39. Anode contact 28 of III N diode 22 is electrically connected to an anode lead 91 of the package, such as by an electrically conductive bond wire 38, and anode contact 28 ' of III N diode 22 ' is electrically connected to an anode lead 93 of the package, such as by an electrically conductive bond wire 38 '.

The electromagnetic isolation module is a high-frequency transformer, the transmission ratio of the input side to the output side of the electromagnetic isolation module can be 1, and only the functions of electrical isolation and voltage clamping are realized. At this time, the input-output voltage transfer ratio of the power conversion device is (M/(1-D)), where D is the duty ratio of the first fixed pulse width signal Vpwm1 (or the second fixed pulse width signal Vpwm2), and M is the duty ratio of the first sinusoidal pulse width signal Vspwm1 (or the second sinusoidal pulse width signal Vspwm 2).

In some other embodiments, the input-side to output-side transmission ratio of the electromagnetic isolation module may be N (N > 1), and the input-output voltage transmission ratio of the three-level power conversion device may be raised to (N × M/(1-D)).

Fig. 24 to fig. 26 are graphs of experimental results of the power conversion device according to the embodiment of the present invention, where fig. 24 shows currents ILin and ILo of the first inductor Lin and the second inductor Lo of the power conversion device, and the first carrier signal Vtri1, and it can be seen that the current ripple frequencies of the two inductors are both 2 times of the switching frequency. Therefore, the power conversion device can greatly reduce the size of the filter inductor compared with the traditional two-level inverter under the same power level. Fig. 25 shows the bus voltage Vbus of the power converter, the voltage stresses of the main switches S1 to S4, and the voltage stresses of the auxiliary switches Ssub1 to Ssub4, and it can be seen that the voltage stresses of all the main switches and the auxiliary switches are half of the bus voltage Vbus, and satisfy the three-level voltage stress characteristic. Fig. 26 shows the input voltage Vin of the dc power source Uin, the voltage Vo of the load Rl, and the potential difference VNL of the output nodes N and L of the power conversion device, and it can be seen that the power conversion device meets the application requirement of three levels of output voltage while completing single-stage boosting and dc-ac power conversion.

Fig. 27 is a schematic circuit structure diagram of a power conversion system provided in an embodiment of the present invention, where the power conversion system includes a power conversion device provided in any embodiment of the present invention and a switch control module 40, and the switch control module 40 is configured to control a first main switch, a second main switch, a third main switch, a fourth main switch, a first auxiliary switch, a second auxiliary switch, a third auxiliary switch, and a fourth auxiliary switch to be turned on or off.

Specifically, in this embodiment, the switch control module 40 may be utilized to control each switch to operate in the above modes, so that the power conversion apparatus can complete three-level voltage conversion.

Optionally, the switch control module 40 comprises a first comparator Comp1, a second comparator Comp2, a third comparator Comp3, a fourth comparator Comp4, a fifth comparator Comp5, a first combinational logic unit 401 and a second combinational logic unit 402;

the non-inverting input terminal of the first comparator Comp1 inputs the first modulated wave signal Vsine, the inverting output terminal of the first comparator Comp1 inputs the first carrier signal Vtri1, and the output terminal of the first comparator Comp1 is electrically connected to the third input terminal of the first combinational logic unit 401; the first modulation wave signal is a sine signal, and the first carrier wave signal is a sawtooth wave signal;

the non-inverting input terminal of the second comparator Comp2 inputs the second modulated wave signal Vdc, the inverting input terminal of the second comparator Comp2 inputs the first carrier signal Vtri1, and the output terminal of the second comparator Comp2 is electrically connected to the second input terminal of the first combinatorial logic unit 401; the second modulation wave signal is a direct current signal;

the non-inverting input terminal of the third comparator Comp3 inputs the first modulated wave signal, the inverting input terminal of the third comparator Comp3 inputs the second carrier signal Vtri2, and the output terminal of the third comparator Comp3 is electrically connected to the third input terminal of the second combinatorial logic unit 402; the second carrier signal is a sawtooth wave signal;

the non-inverting input terminal of the fourth comparator Comp4 inputs the second modulated wave signal, the inverting input terminal of the fourth comparator Comp4 inputs the second carrier signal, and the output terminal of the fourth comparator Comp4 is electrically connected to the second input terminal of the second combinational logic unit;

the non-inverting input terminal of the fifth comparator Comp5 inputs the first modulated wave signal, the inverting input terminal of the fifth comparator Comp5 inputs the ground reference signal of the switch control module, and the output terminal of the fifth comparator Comp5 is electrically connected to the first input terminals of the first combinatorial logic unit 401 and the second combinatorial logic unit 402;

Vgs2＝(Vzero'·Vspwm1)'·Vpwm1；Vgs1＝Vgs2'；

Vgs4＝(Vzero·Vspwm1)'·Vpwm1；Vgs3＝Vgs4'；

the first output end, the second output end, the third output end and the fourth output end of the second combined logic unit are respectively and electrically connected with the control end of the second auxiliary switch, the control end of the first auxiliary switch, the control end of the fourth auxiliary switch and the control end of the third auxiliary switch, and the logic function of the second combined logic unit is as follows:

Vgsub2＝(Vzero'·Vspwm2)'·Vpwm2；Vgsub1＝Vgsub2'；

Vgsub4＝(Vzero·Vspwm2)'·Vpwm2；Vgsub3＝Vgsub4'；

As an embodiment, the first combinational logic unit 401 includes a first nand gate P1, a second nand gate P2, a third nand gate P3, a fourth nand gate P4, a first and gate Q1 and a second and gate Q2;

the first input end of the first NAND gate and the first input end of the second NAND gate are electrically connected with the first input end of the first combinational logic unit, wherein the first input end of the first NAND gate is a negation input end, the second input end of the first NAND gate and the second input end of the second NAND gate are electrically connected with the third input end of the first combinational logic unit, the output end of the first NAND gate is electrically connected with the first input end of the third NAND gate and the first input end of the first AND gate, the output end of the second NAND gate is electrically connected with the first input end of the fourth NAND gate and the first input end of the second AND gate, and the second input end of the first combinational logic unit is electrically connected with the second input end of the first AND gate, the second input end of the third NAND gate, the second input end of the second AND gate and the second input end of the fourth NAND gate; the output end of the first NAND gate is electrically connected with the control end of the second main switch, the output end of the third NAND gate is electrically connected with the control end of the first main switch, the output end of the second AND gate is electrically connected with the control end of the fourth main switch, and the output end of the fourth NAND gate is electrically connected with the control end of the third main switch;

the second combinational logic unit comprises a fifth nand gate P5, a sixth nand gate P6, a seventh nand gate P7, an eighth nand gate P8, a third and gate Q3 and a fourth and gate Q4;

a first input end of a fifth NAND gate and a first input end of a sixth NAND gate are electrically connected with a first input end of a second combined logic unit, wherein the first input end of the fifth NAND gate is a negation input end, a second input end of the fifth NAND gate and a second input end of the sixth NAND gate are electrically connected with a third input end of the second combined logic unit, an output end of the fifth NAND gate is electrically connected with a first input end of a seventh NAND gate and a first input end of a third AND gate, an output end of the sixth NAND gate is electrically connected with a first input end of an eighth NAND gate and a first input end of a fourth AND gate, and a second input end of the second combined logic unit is electrically connected with a second input end of the third AND gate, a second input end of the seventh NAND gate, a second input end of the fourth AND gate and a second input end of the eighth NAND gate; the output end of the third AND gate is electrically connected with the control end of the second auxiliary switch, the output end of the seventh NAND gate is electrically connected with the control end of the first auxiliary switch, the output end of the fourth AND gate is electrically connected with the control end of the fourth auxiliary switch, and the output end of the eighth NAND gate is electrically connected with the control end of the third auxiliary switch.

Specifically, the first carrier signal Vtri1, the second carrier signal Vtri2, the first modulated wave signal Vsine, and the second modulated wave signal Vdc may all be provided by a signal generator, the phase difference between the first carrier signal Vtri1 and the second carrier signal Vtri2 is 180 degrees, the peak values thereof are the same, and the frequencies thereof are also the same, and the corresponding pulse width signal may be generated by the corresponding comparator, that is, the analog signal is converted into a digital signal, and the digital signal is then passed through the first combinational logic unit 401 or the second combinational logic unit 402 to generate the corresponding driving signal to drive the corresponding switch to be turned on or off, so that the input low-voltage dc power is finally converted into high-voltage ac power. The switch control module 40 has the advantages of simple structure, low cost and the like, and further, the overall cost of the power conversion device can be reduced.

An embodiment of the present invention further provides a method for controlling a power conversion system, where the power conversion system is the above-mentioned power conversion system, fig. 28 is a flowchart of a method for controlling a power conversion system according to an embodiment of the present invention, and as shown in fig. 28, the method includes:

step S501, inputting a first modulation wave signal to a non-inverting input end of a first comparator, and inputting a first carrier signal to an inverting input end of the first comparator;

step S502, inputting a second modulation wave signal to the non-inverting input end of a second comparator, and inputting a first carrier signal to the inverting input end of the second comparator;

step S503, inputting the first modulated wave signal to the non-inverting input terminal of the third comparator, and inputting the second carrier signal to the inverting input terminal of the third comparator;

step S504, a second modulation wave signal is input to the non-inverting input end of the fourth comparator, and a second carrier signal is input to the inverting input end of the fourth comparator;

in step S505, the first modulated wave signal is input to the non-inverting input terminal of the fifth comparator, and the reference ground signal is input to the inverting input terminal of the fifth comparator.

Specifically, in this embodiment, step 501, step 502, step 503, step 504, and step 505 may be performed simultaneously, the potential of the ground reference signal is zero, and the detailed working process of the control method may refer to the description of the power conversion apparatus and the power conversion system of the present invention, which is not described herein again. The control method of the power supply conversion system provided by the embodiment of the invention has simpler control logic, can generate stable alternating current output and is beneficial to the application of the power supply conversion system.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A power conversion apparatus, characterized by comprising:

the input end of the first filter network is electrically connected with the direct-current power supply, the first output end of the first filter network is electrically connected with the input end of the first anti-backflow module, and the second output end of the first filter network is electrically connected with the output end of the second anti-backflow module; the first switch network comprises a first main switch, a second auxiliary switch and a first auxiliary switch which are sequentially connected in series between the positive bus and the negative bus; the second switch network comprises a third main switch, a fourth auxiliary switch and a third auxiliary switch which are sequentially connected in series between the positive bus and the negative bus; the first bus capacitor and the second bus capacitor are sequentially connected in series between the positive bus and the negative bus;

a first output end of the first anti-backflow module is connected between the first main switch and the second main switch, and a second output end of the first anti-backflow module is connected between the third main switch and the fourth main switch; a first input end of the second backflow prevention module is connected between the first auxiliary switch and the second auxiliary switch, and a second input end of the second backflow prevention module is connected between the third auxiliary switch and the fourth auxiliary switch; a first input end of the first electromagnetic isolation module is connected between the first main switch and the second main switch, a second input end of the first electromagnetic isolation module is connected between the first auxiliary switch and the second auxiliary switch, a first output end of the first electromagnetic isolation module is electrically connected with a first input end of the second filtering module, and a second output end of the first electromagnetic isolation module is electrically connected with a second output end of the second electromagnetic isolation module;

a first input end of the second electromagnetic isolation module is connected between the third main switch and the fourth main switch, a second input end of the second electromagnetic isolation module is connected between the third auxiliary switch and the fourth auxiliary switch, and a first output end of the second electromagnetic isolation module is electrically connected with a second input end of the second filter network; and a first output end and a second output end of the second filter network are used as output ends of the power supply conversion device.

2. The power conversion device of claim 1, wherein the first filter network comprises a first capacitor and a first inductor;

3. The power conversion device according to claim 1, wherein the first anti-backflow module comprises a first diode and a second diode, an anode of the first diode and an anode of the second diode are electrically connected to serve as an input terminal of the first anti-backflow module, a cathode of the first diode serves as a first output terminal of the first anti-backflow module, and a cathode of the second diode serves as a second output terminal of the first anti-backflow module; and/or the presence of a gas in the gas,

4. The power conversion device of claim 1, wherein the first electromagnetic isolation module is a first transformer; and/or the presence of a gas in the gas,

the second electromagnetic isolation module is a second transformer.

5. The power conversion device according to claim 4, wherein a voltage transfer ratio of the first electromagnetic isolation module is 1 or more, and a voltage transfer ratio of the second electromagnetic isolation module is 1 or more.

6. The power conversion device according to claim 1, wherein at least one of the first main switch, the second main switch, the third main switch, the fourth main switch, the first auxiliary switch, the second auxiliary switch, the third auxiliary switch, and the fourth auxiliary switch is a III-N transistor.

7. A power conversion system, comprising the power conversion apparatus according to any one of claims 1 to 6 and a switch control module;

8. The power conversion system of claim 7, wherein the switch control module comprises a first comparator, a second comparator, a third comparator, a fourth comparator, a fifth comparator, a first combinational logic unit, and a second combinational logic unit;

a non-inverting input end of the first comparator inputs a first modulated wave signal, an inverting input end of the first comparator inputs a first carrier signal, and an output end of the first comparator is electrically connected with a third input end of the first combinational logic unit; the first modulation wave signal is a sine signal, and the first carrier wave signal is a sawtooth wave signal; a non-inverting input end of the second comparator inputs a second modulated wave signal, an inverting input end of the second comparator inputs a first carrier signal, and an output end of the second comparator is electrically connected with a second input end of the first combinational logic unit; the second modulation wave signal is a direct current signal; a non-inverting input end of the third comparator inputs a first modulated wave signal, an inverting input end of the third comparator inputs a second carrier signal, and an output end of the third comparator is electrically connected with a third input end of the second combinational logic unit; the second carrier signal is a sawtooth wave signal; a non-inverting input end of the fourth comparator inputs a second modulated wave signal, an inverting input end of the fourth comparator inputs a second carrier signal, and an output end of the fourth comparator is electrically connected with a second input end of the second combinational logic unit; a first modulation wave signal is input to a non-inverting input end of the fifth comparator, a reference ground signal of the switch control module is input to an inverting input end of the fifth comparator, and an output end of the fifth comparator is electrically connected with first input ends of the first combination logic unit and the second combination logic unit;

Vgs2＝(Vzero'·Vspwm1)'·Vpwm1；Vgs1＝Vgs2'；

Vgs4＝(Vzero·Vspwm1)'·Vpwm1；Vgs3＝Vgs4'；

Vgsub2＝(Vzero'·Vspwm2)'·Vpwm2；Vgsub1＝Vgsub2'；

Vgsub4＝(Vzero·Vspwm2)'·Vpwm2；Vgsub3＝Vgsub4'；

9. The power conversion system of claim 8,

the first combined logic unit comprises a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, a first AND gate and a second AND gate;

10. The power conversion system of claim 8, wherein the first carrier signal is 180 degrees out of phase with the second carrier signal.