CN114429982A - Groove type power device - Google Patents

Groove type power device Download PDF

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Publication number
CN114429982A
CN114429982A CN202210008464.1A CN202210008464A CN114429982A CN 114429982 A CN114429982 A CN 114429982A CN 202210008464 A CN202210008464 A CN 202210008464A CN 114429982 A CN114429982 A CN 114429982A
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China
Prior art keywords
region
trench
contact hole
gate
power device
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Pending
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CN202210008464.1A
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Chinese (zh)
Inventor
刘华明
徐云
李亮
熊淑平
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Priority to CN202210008464.1A priority Critical patent/CN114429982A/en
Publication of CN114429982A publication Critical patent/CN114429982A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention discloses a trench type power device, which comprises a device unit area and a terminal area, wherein the device unit area is provided with a plurality of grooves; the structure in the device unit area includes: the trench gate, the body region, the source region and the first contact hole, wherein the bottom of the first contact hole penetrates through the source region and contacts with the body region; the terminal region surrounds the periphery of the device unit region, and the structure of the terminal region comprises: the body region is also formed on the surface of the first epitaxial layer of the termination region; a second contact hole is formed at the top of the body region of the termination region outside the trench side on the outermost side in the device cell region, and the tops of the first and second contact holes are connected to a source electrode composed of a front metal layer; the second contact hole is contacted with the body region at the bottom to reduce the contact resistance of the body region at the interface of the terminal region and the device unit region, so that the parasitic triode at the interface is prevented from being abnormally started, and the avalanche breakdown energy of the device is improved.

Description

Groove type power device
Technical Field
The present invention relates to semiconductor integrated circuits, and more particularly, to a trench power device.
Background
As shown in fig. 1, the diagram is a schematic diagram of a layout structure of a conventional trench power device; FIG. 2A is a cross-sectional view taken along the dotted line BB in FIG. 1; FIG. 2B is a cross-sectional view taken along the dotted line CC in FIG. 1; taking an N-type trench power MOSFET as an example, a conventional trench power device includes a device cell region and a termination region. In fig. 1, the device cell region and the termination region are located on the left and right sides of the dotted line AA, respectively.
A plurality of device cells are formed in the device cell region; the structure in the device cell region includes:
the trench gate includes a gate dielectric layer 105 and a gate conductive material layer 102 formed in the gate trench.
The gate trench is formed in an N-doped first epitaxial layer 101.
A P-type doped body region 106 is formed in the first epitaxial layer 101, and the depth of the gate trench is greater than the junction depth of the body region 106. Thus, the surface of the body region 106 covered by the layer of gate conductive material 102 is used to form a conductive channel.
An N-type heavily doped source region 107 self-aligned with the trench gate is formed on the surface of the body region 106.
Contact holes 103 are formed at the top of the source regions 107, and the bottoms of the contact holes 103 contact the body regions 106 through the source regions 107.
The termination region surrounds the periphery of the device cell region, and the structure of the termination region includes:
the body region 106 is also formed at the surface of the first epitaxial layer 101 of the termination region.
In general, in a plan view, the layout shape of the device cell in the device cell region includes: bar, square, and hexagon. In fig. 1, the layout shape of the device unit is a stripe shape, and at this time, the layout structure of the device unit region includes:
the contact hole 103 has a first bar-shaped structure.
The trench gate comprises second and third stripe structures 102a, 102 b.
The second bar structures 102a include a plurality of strips parallel to the first bar structures, and each of the first bar structures is located between two adjacent second bar structures 102 a.
The third bar structures 102b are perpendicular to the second bar structures 102a, and the end portions of the second bar structures 102a are connected to the third bar structures 102 b.
The outermost trench gate in the device cell region includes the third stripe structure 102b, and a dotted line BB in fig. 1 corresponds to an outer side surface position of the third stripe structure 102 b.
The trench gate is also arranged in the terminal region; on a plane of depression, the layout shape of the trench gate in the terminal area is a fourth bar-shaped structure 102 c; the fourth bar-shaped structures 102c are parallel to the second bar-shaped structures 102a, and the distance between the fourth bar-shaped structures 102c is larger than the distance between the second bar-shaped structures 102 a.
A first end of the fourth strip-shaped structure 102c is connected to the third strip-shaped structure 102b and a second end of the fourth strip-shaped structure 102c is connected to a gate bus.
The trench power device is a trench power MOSFET.
The first epitaxial layer 101 is formed on a semiconductor substrate 104.
The semiconductor substrate 104 is N-type heavily doped, and the drain region is composed of the semiconductor substrate 104 with a thinned back surface; alternatively, the drain region is composed of a doped region formed by performing N-type heavily doped ion implantation on the semiconductor substrate 104 with the thinned back surface.
Typically, the semiconductor substrate 104 comprises a silicon substrate. The first epitaxial layer 101 comprises a silicon epitaxial layer; the gate dielectric layer 105 comprises a gate oxide layer; the gate conductive material layer 102 comprises a polysilicon gate.
An interlayer film 108 is formed on the front surface of the semiconductor substrate 104, and the interlayer film 108 covers the trench gate and the source region 107 of the device unit region and covers the surface of the body region 106 of the termination region; the contact hole 103 penetrates the interlayer film 108.
Avalanche breakdown Energy (EAS) of a power MOSFET under a non-clamped inductive switching (UIS) condition is an important parameter of a power device, and reflects the magnitude of impact energy (peak voltage current) that the power device can bear in an application circuit.
EAS is mainly determined by three factors, namely the layout design of the device, the actual manufacturing process and the flow, and EAS failure of the device usually occurs in the terminal region around the chip. Under the condition of the same layout size and the same manufacturing process, optimizing the layout design of the terminal is particularly important.
Disclosure of Invention
The invention aims to provide a trench type power device which can improve avalanche breakdown Energy (EAS) of the device.
In order to solve the above technical problem, the present invention provides a trench type power device including a device cell region and a termination region.
A plurality of device cells are formed in the device cell region; the structure in the device cell region includes:
and the trench gate comprises a gate dielectric layer and a gate conductive material layer which are formed in the gate trench.
The gate trench is formed in a first epitaxial layer doped with a first conductivity type.
And a body region doped with a second conductive type is formed in the first epitaxial layer, and the depth of the gate trench is greater than the junction depth of the body region.
And a source region which is self-aligned with the trench gate and is heavily doped with the first conductive type is formed on the surface of the body region.
A first contact hole is formed at the top of the source region, and the bottom of the first contact hole penetrates through the source region and contacts the body region.
The termination region surrounds the periphery of the device cell region, and the structure of the termination region includes:
the body region is also formed at the surface of the first epitaxial layer of the termination region.
A second contact hole is formed at the top of the body region of the termination region outside the trench side on the outermost side in the device cell region, and the tops of the first contact hole and the second contact hole are connected to a source electrode composed of a front metal layer; the second contact hole contacts the body region at the bottom to reduce contact resistance of the body region at the interface of the termination region and the device cell region, thereby preventing abnormal turn-on of a parasitic triode at the interface of the termination region and the device cell region and improving EAS of the device.
In a further improvement, in a plane of view from above, the layout shape of the device unit in the device unit region includes: bar, square, and hexagon.
In a further improvement, in a plane of view from above, the layout shape of the second contact hole of the termination region includes: circular, square and rectangular.
In a further improvement, a plurality of the second contact holes form an array structure.
In a further improvement, a distance between each second contact hole and the adjacent trench gate is equal to a distance between each first contact hole and the adjacent trench gate.
The further improvement is that the width of the second contact hole is 1-1.5 times of the width of the first contact hole.
The further improvement is that when the layout shape of the device unit is strip, the layout structure of the device unit area comprises:
the first contact hole is of a first strip-shaped structure.
The trench gate comprises a second strip structure and a third strip structure.
The second strip-shaped structures comprise a plurality of strips which are parallel to the first strip-shaped structures, and each first strip-shaped structure is positioned between two adjacent second strip-shaped structures.
The third bar structures are perpendicular to each of the second bar structures, and an end of each of the second bar structures is connected to the third bar structures.
In a further improvement, the outermost trench gate in the device unit region includes the third stripe structure.
In a further improvement, the trench gate is also disposed in the termination region; on a plane of depression, the layout shape of the trench gate of the terminal area is in a fourth strip structure;
the fourth bar structures are parallel to the second bar structures, and the distance between the fourth bar structures is larger than that between the second bar structures;
the first end of the fourth stripe structure is connected with the third stripe structure, and the second end of the fourth stripe structure is connected with the gate bus line.
In a plane of plan view, each second contact hole is in a fifth strip structure or an array structure formed by a plurality of second contact holes is in a fifth strip structure;
the fifth bar structures and the third bar structures are parallel, and each of the fifth bar structures is disposed in a spaced area of each of the fourth bar structures.
In a further improvement, a body contact region heavily doped with the second conductivity type is further formed at the bottom of the first contact hole and the second contact hole.
The further improvement is that the groove type power device is a groove type power MOSFET;
the first epitaxial layer is formed on the semiconductor substrate;
the semiconductor substrate is heavily doped with a first conductivity type, and the drain region consists of the semiconductor substrate with the thinned back; or the drain region is composed of a doped region formed by performing first conductivity type heavily doped ion implantation on the semiconductor substrate with the thinned back surface.
In a further refinement, the semiconductor substrate comprises a silicon substrate.
In a further refinement, the first epitaxial layer comprises a silicon epitaxial layer;
the gate dielectric layer comprises a gate oxide layer;
the gate conductive material layer includes a polysilicon gate.
The further improvement is that the trench type power device is an N type device, the first conduction type is an N type, and the second conduction type is a P type; or, the trench type power device is a P-type device, the first conductivity type is a P-type, and the second conductivity type is an N-type.
The contact hole, namely the second contact hole, is also arranged at the top of the body region of the terminal region, the second contact hole is close to the outer side surface of the groove gate on the outermost side in the device unit region, and the interface between the device unit region and the terminal region is positioned at the groove gate on the outermost side in the device unit region, so that the contact resistance of the body region at the interface between the terminal region and the device unit region can be reduced after the second contact hole is arranged, and the parasitic triode on the interface between the terminal region and the device unit region can be prevented from being abnormally opened, so that the EAS of the device can be improved.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1 is a schematic diagram of a layout structure of a conventional trench type power device;
FIG. 2A is a sectional view along a dotted line BB in FIG. 1;
FIG. 2B is a sectional view of the structure of FIG. 1 taken along the dotted line CC;
fig. 3 is a schematic diagram of a layout structure of a trench power device according to an embodiment of the present invention;
FIG. 4A is a sectional view along a dotted line BB in FIG. 3;
fig. 4B is a sectional view of the structure along a broken line CC in fig. 3.
Detailed Description
As shown in fig. 3, the diagram is a schematic diagram of a layout structure of a trench type power device according to an embodiment of the present invention; FIG. 4A is a cross-sectional view taken along the dashed line BB in FIG. 3; FIG. 4B is a sectional view of the structure taken along the dotted line CC in FIG. 3; the trench power device comprises a device unit area and a terminal area. In fig. 3, the device cell region and the termination region are located on the left and right sides of the dotted line AA, respectively.
A plurality of device cells are formed in the device cell region; the structure in the device cell region includes:
the trench gate includes a gate dielectric layer 205 and a gate conductive material layer 202 formed in the gate trench.
The gate trenches are formed in a first epitaxial layer 201 of a first conductivity type doping.
A body region 206 doped with the second conductivity type is formed in the first epitaxial layer 201, and the depth of the gate trench is greater than the junction depth of the body region 206. Thus, the surface of body region 206 covered by the layer of gate conductive material 202 is used to form a conductive channel.
A heavily doped source region 207 of the first conductivity type is formed on the surface of the body region 206 in self-alignment with the trench gate.
A first contact hole 203 is formed at the top of the source region 207, and the bottom of the first contact hole 203 contacts the body region 206 through the source region 207.
The termination region surrounds the periphery of the device cell region, and the structure of the termination region includes:
the body region 206 is also formed at the surface of the first epitaxial layer 201 of the termination region.
A second contact hole 203a is formed at the top of the body region 206 of the termination region outside the trench side at the outermost side in the device cell region, and the tops of the first contact hole 203 and the second contact hole 203a are both connected to a source electrode composed of a front metal layer; the second contact hole 203a contacts the body region 206 at the bottom to reduce the contact resistance of the body region 206 at the interface of the termination region and the device cell region, to prevent the parasitic transistor at the interface of the termination region and the device cell region from being abnormally turned on and thus improve the EAS of the device.
In an embodiment of the present invention, in a top view plane, a layout shape of the device unit in the device unit region includes: bar, square, and hexagon.
In a plan view, the layout shape of the second contact hole 203a in the termination region includes: circular, square and rectangular. A plurality of the second contact holes 203a constitute an array structure.
The distance between each second contact hole 203a and the adjacent trench gate is equal to the distance between each first contact hole 203a and the adjacent trench gate.
The width of the second contact hole 203a is 1 to 1.5 times the width of the first contact hole 203.
In fig. 3, the layout shape of the device unit is a stripe shape, and at this time, the layout structure of the device unit region includes:
the first contact hole 203 has a first bar-shaped structure.
The trench gate comprises second strip structures 202a and third strip structures 202 b.
The second bar structures 202a comprise a plurality of strips parallel to the first bar structures, and each of the first bar structures is located between two adjacent second bar structures 202 a.
The third bar structures 202b are perpendicular to the second bar structures 202a, and the end of each second bar structure 202a is connected to the third bar structure 202 b.
The outermost trench gate in the device cell region includes the third stripe structure 202b, and a dotted line BB in fig. 3 corresponds to an outer side surface position of the third stripe structure 202 b.
The trench gate is also arranged in the terminal region; on a plane of depression, the layout shape of the trench gate of the terminal area is a fourth strip structure 202 c;
the fourth bar structures 202c are parallel to the second bar structures 202a, and the distance between the fourth bar structures 202c is larger than the distance between the second bar structures 202 a;
a first end of the fourth strip-shaped structure 202c is connected to the third strip-shaped structure 202b and a second end of the fourth strip-shaped structure 202c is connected to a gate bus.
In other embodiments, when the layout shape of the device unit in the device unit region is a square block or a hexagon, the device units are arranged to form an array structure, and each of the second bar-shaped structures 202a, the third bar-shaped structures 202b, and the fourth bar-shaped structures 202c is arranged by the trench gates of the device units arranged in the array structure in a plan view.
In an embodiment of the present invention, on a top view plane, each of the second contact holes 203a is in a fifth stripe structure or an array structure formed by a plurality of the second contact holes 203a is in a fifth stripe structure.
The fifth bar structures are parallel to the third bar structures 202b, and each of the fifth bar structures is disposed in a spaced area of each of the fourth bar structures 202 c.
A body contact region 209 heavily doped with a second conductive type is also formed at the bottom of the first contact hole 203 and the second contact hole 203 a.
The trench power device is a trench power MOSFET.
The first epitaxial layer 201 is formed on a semiconductor substrate 204.
The semiconductor substrate 204 is heavily doped with the first conductivity type, and the drain region is formed by the semiconductor substrate 204 with the thinned back surface; alternatively, the drain region is composed of a doped region formed by performing first conductivity type heavily doped ion implantation on the semiconductor substrate 204 with the thinned back surface.
The semiconductor substrate 204 comprises a silicon substrate.
The first epitaxial layer 201 comprises a silicon epitaxial layer;
the gate dielectric layer 205 comprises a gate oxide layer;
the gate conductive material layer 202 comprises a polysilicon gate.
An interlayer film 208 is formed on the front surface of the semiconductor substrate 204, and the interlayer film 208 covers the trench gate and the source region 207 of the device unit region and covers the surface of the body region 206 of the termination region; both the first contact hole 203 and the second contact hole 203a pass through the interlayer film 208.
The groove type power device is an N type device, the first conduction type is an N type, and the second conduction type is a P type. In other embodiments can also be: the groove type power device is a P type device, the first conduction type is a P type, and the second conduction type is an N type.
In the embodiment of the invention, the contact hole, namely the second contact hole 203a, is also arranged at the top of the body region 206 of the terminal region, the second contact hole 203a is close to the outer side surface of the outermost trench gate in the device unit region, and the interface of the device unit region and the terminal region is positioned at the outermost trench gate in the device unit region, so that the contact resistance of the body region 206 at the interface of the terminal region and the device unit region can be reduced after the second contact hole 203a is arranged, and the parasitic triode at the interface of the terminal region and the device unit region can be prevented from being abnormally opened, thereby improving the EAS of the device.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (15)

1. A trench type power device is characterized by comprising a device unit area and a terminal area;
a plurality of device cells are formed in the device cell region; the structure in the device cell region includes:
the trench gate comprises a gate dielectric layer and a gate conductive material layer which are formed in the gate trench;
the grid groove is formed in the first epitaxial layer doped with the first conduction type;
a body region doped with a second conductive type is formed in the first epitaxial layer, and the depth of the gate trench is greater than the junction depth of the body region;
a source region of the first conduction type heavily doped self-aligned with the trench gate is formed on the surface of the body region;
a first contact hole is formed at the top of the source region, and the bottom of the first contact hole penetrates through the source region and contacts the body region;
the termination region surrounds the periphery of the device cell region, and the structure of the termination region includes:
the body region is also formed on the surface of the first epitaxial layer of the termination region;
a second contact hole is formed at the top of the body region of the termination region outside the trench side on the outermost side in the device cell region, and the tops of the first contact hole and the second contact hole are connected to a source electrode composed of a front metal layer; the second contact hole contacts the body region at the bottom to reduce the contact resistance of the body region at the interface of the termination region and the device unit region, so that the parasitic triode at the interface of the termination region and the device unit region is prevented from being abnormally turned on, and the avalanche breakdown energy of the device is improved.
2. The trench power device of claim 1 wherein: on a plane of top view, the layout shape of the device unit in the device unit area comprises: bar, square, and hexagon.
3. The trench power device of claim 2 wherein: on a plane of depression, the layout shape of the second contact hole of the terminal area comprises: circular, square and rectangular.
4. The trench power device of claim 3 wherein: and the second contact holes form an array structure.
5. The trench power device of claim 4 wherein: the distance between each second contact hole and the adjacent trench gate is equal to the distance between each first contact hole and the adjacent trench gate.
6. The trench power device of claim 4 wherein: the width of the second contact hole is 1-1.5 times of the width of the first contact hole.
7. The trench power device of claim 4 wherein: when the layout shape of the device unit is strip, the layout structure of the device unit area comprises:
the first contact hole is of a first strip-shaped structure;
the trench gate comprises a second strip-shaped structure and a third strip-shaped structure;
the second strip-shaped structures comprise a plurality of strips which are parallel to the first strip-shaped structures, and each first strip-shaped structure is positioned between two adjacent second strip-shaped structures;
the third bar structures are perpendicular to each of the second bar structures, and an end of each of the second bar structures is connected to the third bar structures.
8. The trench power device of claim 7 wherein: the groove gate on the outermost side in the device unit area comprises the third strip-shaped structure.
9. The trench power device of claim 8 wherein: the trench gate is also arranged in the terminal region; on a plane of depression, the layout shape of the trench gate of the terminal area is in a fourth strip structure;
the fourth bar structures are parallel to the second bar structures, and the distance between the fourth bar structures is larger than that between the second bar structures;
the first end of the fourth stripe structure is connected with the third stripe structure, and the second end of the fourth stripe structure is connected with the gate bus line.
10. The trench power device of claim 9 wherein: on a plane of top view, each second contact hole is in a fifth strip-shaped structure or an array structure formed by a plurality of second contact holes is in a fifth strip-shaped structure;
the fifth bar structures and the third bar structures are parallel, and each of the fifth bar structures is disposed in a spaced area of each of the fourth bar structures.
11. The trench power device of claim 1 wherein: and a body contact region heavily doped with the second conductivity type is also formed at the bottom of the first contact hole and the second contact hole.
12. The trench power device of claim 11 wherein: the groove type power device is a groove type power MOSFET;
the first epitaxial layer is formed on the semiconductor substrate;
the semiconductor substrate is heavily doped with a first conductivity type, and the drain region consists of the semiconductor substrate with the thinned back; or the drain region is composed of a doped region formed by performing first conductivity type heavily doped ion implantation on the semiconductor substrate with the thinned back surface.
13. The trench power device of claim 12 wherein: the semiconductor substrate includes a silicon substrate.
14. The trench power device of claim 13 wherein: the first epitaxial layer comprises a silicon epitaxial layer;
the gate dielectric layer comprises a gate oxide layer;
the gate conductive material layer includes a polysilicon gate.
15. The trench power device of any of claims 1 to 14 wherein: the groove type power device is an N-type device, the first conduction type is an N type, and the second conduction type is a P type; or, the trench type power device is a P-type device, the first conductivity type is a P-type, and the second conductivity type is an N-type.
CN202210008464.1A 2022-01-06 2022-01-06 Groove type power device Pending CN114429982A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210008464.1A CN114429982A (en) 2022-01-06 2022-01-06 Groove type power device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210008464.1A CN114429982A (en) 2022-01-06 2022-01-06 Groove type power device

Publications (1)

Publication Number Publication Date
CN114429982A true CN114429982A (en) 2022-05-03

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