CN114428426B - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
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- CN114428426B CN114428426B CN202210171718.1A CN202210171718A CN114428426B CN 114428426 B CN114428426 B CN 114428426B CN 202210171718 A CN202210171718 A CN 202210171718A CN 114428426 B CN114428426 B CN 114428426B
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- 239000000758 substrate Substances 0.000 title claims abstract description 128
- 239000003990 capacitor Substances 0.000 claims abstract description 19
- 239000012780 transparent material Substances 0.000 claims abstract description 18
- 239000010409 thin film Substances 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 184
- 238000002161 passivation Methods 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 8
- 239000011229 interlayer Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims description 6
- 239000004973 liquid crystal related substance Substances 0.000 claims description 5
- 229920000178 Acrylic resin Polymers 0.000 claims description 4
- 239000004925 Acrylic resin Substances 0.000 claims description 4
- 239000004793 Polystyrene Substances 0.000 claims description 4
- 229920000515 polycarbonate Polymers 0.000 claims description 4
- 239000004417 polycarbonate Substances 0.000 claims description 4
- 229920002223 polystyrene Polymers 0.000 claims description 4
- -1 polytetrafluoroethylene Polymers 0.000 claims description 4
- 229920001343 polytetrafluoroethylene Polymers 0.000 claims description 4
- 239000004810 polytetrafluoroethylene Substances 0.000 claims description 4
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 4
- 239000011787 zinc oxide Substances 0.000 claims description 4
- WGLPBDUCMAPZCE-UHFFFAOYSA-N Trioxochromium Chemical compound O=[Cr](=O)=O WGLPBDUCMAPZCE-UHFFFAOYSA-N 0.000 claims description 3
- 229910000423 chromium oxide Inorganic materials 0.000 claims description 3
- 229910003437 indium oxide Inorganic materials 0.000 claims description 3
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 3
- 239000010408 film Substances 0.000 abstract description 9
- 229910052751 metal Inorganic materials 0.000 abstract description 8
- 239000002184 metal Substances 0.000 abstract description 8
- 238000002834 transmittance Methods 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 229910010272 inorganic material Inorganic materials 0.000 description 3
- 239000011147 inorganic material Substances 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
- G02F1/134354—Subdivided pixels, e.g. for grey scale or redundancy the sub-pixels being capacitively coupled
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
- Geometry (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The embodiment of the application provides an array substrate and a display panel; the array substrate comprises a plurality of sub-pixel units, wherein each sub-pixel unit comprises a public electrode formed by transparent materials and a pixel electrode arranged on one side of the public electrode, the public electrode and the pixel electrode form a storage capacitor of the array substrate, and in the top view direction of the array substrate, the orthographic projection of the pixel electrode on the public electrode is positioned in the public electrode; according to the array substrate, the common electrode in each sub-pixel unit is made of the transparent material, and in the top view direction of the array substrate, the orthographic projection of the pixel electrode on the common electrode is positioned in the common electrode, so that the common electrode forming the storage capacitor completely covers the area, far away from the thin film transistor, of the array substrate, the wiring design of the grid metal film layer adopted by the common electrode is replaced, the aperture ratio of the sub-pixel unit is improved, and the transmittance of the array substrate is further improved.
Description
Technical Field
The application relates to the field of display, in particular to an array substrate and a display panel.
Background
In the field of innovation of terminal products, the transparent screen occupies a place in the fields of outdoor advertising, glass curtain walls and the like in a brand new display mode, light and thin appearance design and high-end technological atmosphere, and brings unprecedented visual experience and brand new application experience to everyone. Liquid crystal displays (Liquid Crystal Display, LCDs), light-Emitting Diode (LED) transparent screens, and Organic Light-Emitting Diode (Organic Light-Emitting Diode) transparent screen applications are growing, rapidly becoming new pets for advertisers and new trends for new media development. However, the transparent display screen has low opening ratio of the back plate due to the metal wiring problem of the driving circuit, so that the transparency of the display screen is low, the overall display brightness is low, and the appearance of people is poor.
Therefore, an array substrate and a display panel are needed to solve the above-mentioned problems.
Disclosure of Invention
The embodiment of the application provides an array substrate and a display panel, which can improve the technical problem that the opening ratio of a backboard of a current transparent display screen is low.
The embodiment of the application provides an array substrate, which comprises a plurality of sub-pixel units; each sub-pixel unit comprises a common electrode formed by transparent materials and a pixel electrode arranged on one side of the common electrode, wherein the common electrode and the pixel electrode form a storage capacitor of the array substrate;
and in the top view direction of the array substrate, the orthographic projection of the pixel electrode on the common electrode is positioned in the common electrode.
Alternatively, in some embodiments of the present application, the common electrodes in two adjacent sub-pixel units are continuously and electrically connected.
Optionally, in some embodiments of the present application, each of the sub-pixel units includes a gate layer and a source-drain layer disposed on the gate layer;
wherein the common electrode, the gate layer and the source/drain layer are arranged in different layers.
Optionally, in some embodiments of the present application, the array substrate further includes an organic insulating layer disposed on the source-drain layer, the common electrode disposed on the organic insulating layer, a passivation layer disposed on the common electrode, and the pixel electrode disposed on the passivation layer;
wherein the dielectric constant of the passivation layer is greater than the dielectric constant of the organic insulating layer.
Optionally, in some embodiments of the present application, the material of the passivation layer is at least one of silicon nitride, silicon oxide, and silicon oxynitride, and the material of the organic insulating layer is at least one of acrylic resin, polytetrafluoroethylene, polycarbonate, and polystyrene.
Optionally, in some embodiments of the present application, a ratio of a thickness of the organic insulating layer to a thickness of the passivation layer is greater than or equal to 2.
Optionally, in some embodiments of the present application, the materials of the common electrode and the pixel electrode each include at least one of indium tin oxide, indium oxide, tin dioxide, zinc oxide, chromium oxide, and indium zinc oxide.
Optionally, in some embodiments of the present application, the array substrate further includes a gate insulating layer disposed on the substrate and covering the gate layer, an active layer disposed on the gate insulating layer and disposed corresponding to the gate layer, and a source drain layer disposed on the gate insulating layer and electrically connected to the active layer.
Optionally, in some embodiments of the present application, the array substrate further includes a light shielding layer disposed on the substrate, a buffer layer disposed on the substrate and covering the light shielding layer, an active layer disposed on the buffer layer, a gate insulating layer disposed on the active layer, a gate layer disposed on the gate insulating layer, an interlayer insulating layer disposed on the buffer layer and completely covering the active layer, the gate insulating layer, the gate layer, and the source drain layer disposed on the interlayer insulating layer.
Correspondingly, the embodiment of the application also provides a display panel, which comprises an array substrate, a counter substrate and a liquid crystal layer arranged between the array substrate and the counter substrate, wherein the array substrate comprises a plurality of sub-pixel units, each sub-pixel unit comprises a common electrode formed by transparent materials and a pixel electrode arranged on one side of the common electrode, and the common electrode and the pixel electrode form a storage capacitor of the array substrate;
and in the top view direction of the array substrate, the orthographic projection of the pixel electrode on the common electrode is positioned in the common electrode.
The embodiment of the application provides an array substrate and a display panel; the array substrate comprises a plurality of sub-pixel units, wherein each sub-pixel unit comprises a public electrode formed by transparent materials and a pixel electrode arranged on one side of the public electrode, the public electrode and the pixel electrode form a storage capacitor of the array substrate, and in the top view direction of the array substrate, the orthographic projection of the pixel electrode on the public electrode is positioned in the public electrode; according to the array substrate, the common electrode in each sub-pixel unit is made of the transparent material, and in the top view direction of the array substrate, the orthographic projection of the pixel electrode on the common electrode is positioned in the common electrode, so that the common electrode forming the storage capacitor completely covers the area, far away from the thin film transistor, of the array substrate, the wiring design of the grid metal film layer adopted by the common electrode is replaced, the aperture ratio of the sub-pixel unit is improved, and the transmittance of the array substrate is further improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a first cross-sectional structure of an array substrate according to an embodiment of the present application;
fig. 2 is a schematic plan view of a common electrode in an array substrate according to an embodiment of the present application;
fig. 3 is a schematic diagram of a second cross-sectional structure of an array substrate according to an embodiment of the present application.
Detailed Description
The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application. Furthermore, it should be understood that the detailed description is presented herein for purposes of illustration and explanation only and is not intended to limit the present application. In this application, unless otherwise indicated, terms of orientation such as "upper" and "lower" are used to generally refer to the upper and lower positions of the device in actual use or operation, and specifically the orientation of the drawing figures; while "inner" and "outer" are for the outline of the device.
According to the embodiment of the application, aiming at the technical problem that the opening ratio of the backboard of the current transparent display screen is low, the technical problem can be improved.
The technical solutions of the present application will now be described with reference to specific embodiments.
Referring to fig. 1 to 3, an embodiment of the present application provides an array substrate 10, where the array substrate 10 includes a plurality of sub-pixel units 20; wherein each of the sub-pixel units 20 includes a common electrode 108 made of a transparent material and a pixel electrode 110 disposed at one side of the common electrode 108, the common electrode 108 and the pixel electrode 110 constituting a storage capacitor of the array substrate 10;
in the top view direction of the array substrate 10, the orthographic projection of the pixel electrode 110 on the common electrode 108 is located in the common electrode 108.
According to the array substrate 10 provided by the embodiment of the invention, the common electrode 108 in each sub-pixel unit 20 is made of a transparent material, and in the top view direction of the array substrate 10, the orthographic projection of the pixel electrode 110 on the common electrode 108 is positioned in the common electrode 108, so that the common electrode 108 forming the storage capacitor completely covers the area, far away from the thin film transistor, on the array substrate 10, and the wiring design of the gate metal film layer adopted by the common electrode 108 is replaced, thereby improving the aperture ratio of the sub-pixel unit 20 and further improving the transmittance of the array substrate 10.
The technical solutions of the present application will now be described with reference to specific embodiments.
Example 1
Fig. 1 is a schematic diagram of a first cross-sectional structure of an array substrate 10 according to an embodiment of the present disclosure; the array substrate 10 includes a plurality of thin film transistors, and each of the thin film transistors has a back channel etching structure.
Specifically, the array substrate 10 includes a plurality of sub-pixel units 20, each sub-pixel unit 20 includes a common electrode 108 made of a transparent material and a pixel electrode 110 disposed on one side of the common electrode 108, and the common electrode 108 and the pixel electrode 110 constitute a storage capacitor of the array substrate 10;
in the top view direction of the array substrate 10, the orthographic projection of the pixel electrode 110 on the common electrode 108 is located in the common electrode 108.
In this embodiment, the array substrate 10 includes a substrate 101, a gate layer 102 disposed on the substrate 101, a gate insulating layer 103 disposed on the substrate 101 and entirely covering the gate layer 102, an active layer 104 disposed on the gate insulating layer 103, a source drain layer 105 disposed on the gate insulating layer 103 and partially covering the active layer 104, a first inorganic insulating layer 106 disposed on the gate insulating layer 103 and partially covering the source drain layer 105 and partially the active layer 104, an organic insulating layer 107 disposed on the first inorganic insulating layer 106, the common electrode 108 disposed on the organic insulating layer 107, a passivation layer 109 disposed on the organic insulating layer 107 and entirely covering the common electrode 108, and a pixel electrode 110 disposed on the passivation layer 109;
wherein, in the top view direction of the array substrate 10, the orthographic projection of the active layer 104 on the substrate 101 is located in the gate layer 102.
In this embodiment, the source-drain layer 105 includes a source 1051 and a drain 1052 separately disposed from the source 1051, the source 1051 is electrically connected to one end of the active layer, and the drain 1052 is further electrically connected to the opposite end of the active layer 104.
Specifically, the passivation layer 109 has an opening 1091, and the depth of the opening 1091 is greater than the thickness of the passivation layer 109; the pixel electrode 110 completely covers the opening 1091, and is directly electrically connected to the drain 1052 of the source-drain layer 105 at the bottom of the opening 1091.
In the embodiment of the present application, the substrate 101 may be a glass substrate or a polyimide film, and the substrate 101 may further be formed of one or more polyimide films. The material of the gate layer 102 may be a metal material having excellent conductivity such as molybdenum, copper, and aluminum; the material of the gate insulating layer 103 may be one or more of inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride, or silicon dioxide, so as to play a role of insulating protection. The material of the active layer 104 may be a metal oxide semiconductor material such as indium gallium zinc oxide or indium zinc oxide. The source/drain layer 105 may be made of a metal material having excellent conductivity, such as molybdenum, copper, or aluminum.
In this embodiment of the present application, the material of the first inorganic insulating layer 106 may be one or more of inorganic materials such as silicon nitride, silicon oxide or silicon oxynitride, which is used for isolating water and oxygen, and playing a role in insulating and protecting other functional film layers; the material of the organic insulating layer 107 is at least one of acrylic resin, polytetrafluoroethylene, polycarbonate, and polystyrene.
In this embodiment, the material of the passivation layer 109 is at least one of silicon nitride, silicon oxide, and silicon oxynitride, and the material of the organic insulating layer 107 is at least one of acrylic resin, polytetrafluoroethylene, polycarbonate, and polystyrene; the materials of the common electrode 108 and the pixel electrode 110 each include at least one of indium tin oxide, indium oxide, tin dioxide, zinc oxide, chromium oxide, and indium zinc oxide.
In this embodiment, the common electrode 108 is disposed in different layers from the gate layer 102 and the source/drain layer 105. Further, the common electrode 108 is disposed on the organic insulating layer 107; this arrangement may be such that the thickness of the insulating material (passivation layer 109 in the embodiment of the present application) present in the storage capacitor constituted by the common electrode 108 and the pixel electrode 110 is within a reasonable range.
In the embodiment of the present application, the dielectric constant of the passivation layer 109 is greater than the dielectric constant of the organic insulating layer 107; this arrangement can increase the storage capacitance of the storage capacitor.
In the embodiment of the present application, the ratio of the thickness of the organic insulating layer 107 to the thickness of the passivation layer 109 is greater than or equal to 2. Wherein the passivation layer 109 is preferably 2000 a/m and the organic insulating layer 107 is preferably 5000 a/m thick.
Further, since the common electrode 108 is disposed on the organic insulating layer 107, the organic insulating layer 107 may serve as a planarization layer to planarize a film layer of the common electrode 108.
Further, since the ratio of the thickness of the organic insulating layer 107 to the thickness of the passivation layer 109 is greater than or equal to 2, the thickness distance between the pixel electrode 110 and the data line 22 arranged in the same layer as the source/drain layer 105 is increased, and the influence of parasitic capacitance (Cpd) generated between the pixel electrode 110 and the data line 22 on signal transmission is reduced; meanwhile, the thickness distance of the scanning line 21, which is formed by the common electrode 108 and the gate layer 102 in the same layer, is increased, and the influence of parasitic capacitance (Cpg) generated between the common electrode 108 and the scanning line 21 on signal transmission is reduced.
Fig. 2 is a schematic plan view of a common electrode 108 in the array substrate 10 according to the embodiment of the present application; specifically, the array substrate 10 includes a plurality of the scan lines 21 arranged in a first direction D1 and a plurality of the data lines 22 arranged in a second direction D2, and the first direction D1 crosses the second direction D2. Regions where the plurality of scanning lines 21 intersect the plurality of data lines 22 form the sub-pixel units 20;
wherein the common electrodes 108 in two adjacent sub-pixel units 20 are continuously and electrically connected.
In this embodiment, the common electrode 108 is disposed in a second area adjacent to the first area 23, where the first area 23 is an area of the array substrate 10 corresponding to the plurality of thin film transistors, and the second area is an area of the array substrate 10 away from the plurality of thin film transistors. In the second region, the common electrode 108 entirely covers the scan lines 21 arranged in the first direction D1 and the data lines 22 arranged in the second direction D2.
Because the common electrode 108 is made of transparent material, the whole surface connection design can be used to replace the wiring design of the metal film layer where the gate layer 102 is located, so that the aperture ratio of the sub-pixel unit 20 can be effectively improved, and the transmittance of the array substrate 10 can be further improved.
Aiming at the technical problem that the opening ratio of the backboard of the current transparent display screen is low, the embodiment of the application provides the array substrate 10; the array substrate 10 includes a plurality of sub-pixel units 20, each sub-pixel unit 20 includes a plurality of thin film transistors with back channel etching type structures, a common electrode 108 made of transparent materials, and a pixel electrode 110 disposed at one side of the common electrode 108, the common electrode 108 and the pixel electrode 110 form a storage capacitor of the array substrate 10, wherein, in a top view direction of the array substrate 10, a front projection of the pixel electrode 110 on the common electrode 108 is located in the common electrode 108; in the above array substrate 10, the common electrode 108 in each sub-pixel unit 20 is made of a transparent material, and in the top view direction of the array substrate 10, the orthographic projection of the pixel electrode 110 on the common electrode 108 is located in the common electrode 108, so that the common electrode 108 forming the storage capacitor completely covers the area of the array substrate 10 far away from the thin film transistor, and the gate metal film routing design adopted by the common electrode 108 is replaced, so that the aperture ratio of the sub-pixel unit 20 is improved, and the transmittance of the array substrate 10 is further improved.
Example two
Fig. 3 is a schematic diagram of a second cross-sectional structure of the array substrate 10 according to the embodiment of the present application; the structure of the array substrate 10 in the second embodiment of the present application is the same as or similar to the structure of the array substrate 10 in the first embodiment of the present application, and the difference is that a plurality of thin film transistors are disposed in the array substrate 10, and the thin film transistors are in a top gate structure. The top gate structure can greatly improve the parasitic capacitance problem caused by the overlapping of the source and drain layers 105 and the gate layer 102 in the vertical direction.
Specifically, the array substrate 10 includes the substrate 101, a light shielding layer 111 provided on the substrate 101, a buffer layer 112 provided on the substrate 101 and entirely covering the light shielding layer 111, the active layer 104 provided on the buffer layer 112, the gate insulating layer 103 provided on the active layer 104, the gate layer 102 provided on the gate insulating layer 103, an interlayer insulating layer 113 provided on the buffer layer 112 and entirely covering the active layer 104, the gate insulating layer 103 and the gate layer 102, the source drain layer 105 provided on the interlayer insulating layer 113, the first inorganic insulating layer 106 provided on the interlayer insulating layer 113 and entirely covering the source drain layer 105, the organic insulating layer 107 provided on the first inorganic insulating layer 106, the common electrode 108 provided on the organic insulating layer 107, the passivation layer 109 provided on the common electrode 108 and the passivation layer 109 provided on the pixel electrode 109;
in the top view direction of the array substrate 10, the orthographic projection of the pixel electrode 110 on the common electrode 108 is located in the common electrode 108.
In this embodiment, the material of the buffer layer 112 may be one or more of inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride or silicon dioxide, which plays a role of isolating water and oxygen. The material of the light shielding layer 111 may be a metal material having excellent conductivity such as molybdenum, copper, and aluminum.
Specifically, in the top view direction of the array substrate 10, the orthographic projection of the active layer 104 on the substrate 101 is located in the light shielding layer 111. This arrangement prevents external light from adversely affecting the active layer 104.
In this embodiment, the array substrate 10 includes a first via 1131, a second via 1132, and a third via 1133; the source 1051 of the source-drain layer 105 is electrically connected to the light shielding layer 111 through a first via 1131, the source 1051 of the source-drain layer 105 is also electrically connected to one end of the active layer 104 through a second via 1132, and the drain 1052 of the source-drain layer 105 is electrically connected to the other end of the active layer 104 through a third via 1133.
Further, the array substrate 10 further includes a fourth via 1092, the fourth via 1092 penetrates through the passivation layer 109, the organic insulating layer 107 and a portion of the first inorganic insulating layer 106 and exposes the drain electrode 1052 of the source/drain layer 105, and the pixel electrode 110 completely fills the fourth via 1092 and is electrically connected to the drain electrode 1052 of the source/drain layer 105.
Aiming at the technical problem that the opening ratio of the backboard of the current transparent display screen is low, the embodiment of the application provides the array substrate 10; the array substrate 10 includes a plurality of sub-pixel units 20, each sub-pixel unit 20 includes a plurality of thin film transistors with top gate structures, a common electrode 108 made of transparent material, and a pixel electrode 110 disposed on one side of the common electrode 108, the common electrode 108 and the pixel electrode 110 form a storage capacitor of the array substrate 10, wherein in a top view direction of the array substrate 10, a front projection of the pixel electrode 110 on the common electrode 108 is located in the common electrode 108; in the above array substrate 10, the common electrode 108 in each sub-pixel unit 20 is made of a transparent material, and in the top view direction of the array substrate 10, the orthographic projection of the pixel electrode 110 on the common electrode 108 is located in the common electrode 108, so that the common electrode 108 forming the storage capacitor completely covers the area of the array substrate 10 far away from the thin film transistor, and the gate metal film routing design adopted by the common electrode 108 is replaced, so that the aperture ratio of the sub-pixel unit 20 is improved, and the transmittance of the array substrate 10 is further improved.
Correspondingly, the embodiment of the application also provides a display panel, which comprises an array substrate 10, a counter substrate and a liquid crystal layer arranged between the array substrate 10 and the counter substrate;
wherein the array substrate 10 includes a plurality of sub-pixel units 20, each sub-pixel unit 20 includes a common electrode 108 made of a transparent material and a pixel electrode 110 disposed at one side of the common electrode 108, and the common electrode 108 and the pixel electrode 110 form a storage capacitor of the array substrate 10;
in the top view direction of the array substrate 10, the orthographic projection of the pixel electrode 110 on the common electrode 108 is located in the common electrode 108.
The display panel is particularly applied to transparent displays, mobile terminals and outdoor large screen displays.
The embodiment of the application provides an array substrate 10 and a display panel; the array substrate 10 comprises a plurality of sub-pixel units 20, wherein each sub-pixel unit 20 comprises a common electrode 108 formed by transparent materials and a pixel electrode 110 arranged on one side of the common electrode 108, the common electrode 108 and the pixel electrode 110 form a storage capacitor of the array substrate 10, and in the top view direction of the array substrate 10, the orthographic projection of the pixel electrode 110 on the common electrode 108 is positioned in the common electrode 108; in the above array substrate 10, the common electrode 108 in each sub-pixel unit 20 is made of a transparent material, and in the top view direction of the array substrate 10, the orthographic projection of the pixel electrode 110 on the common electrode 108 is located in the common electrode 108, so that the common electrode 108 forming the storage capacitor completely covers the area of the array substrate 10 far away from the thin film transistor, and the gate metal film routing design adopted by the common electrode 108 is replaced, so that the aperture ratio of the sub-pixel unit 20 is improved, and the transmittance of the array substrate 10 is further improved.
The foregoing has described in detail an array substrate 10 and a display panel provided in the embodiments of the present application, and specific examples have been applied herein to illustrate the principles and embodiments of the present application, and the description of the foregoing examples is only for aiding in understanding the method and core concept of the present application; meanwhile, those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, and the present description should not be construed as limiting the present application in view of the above.
Claims (6)
1. An array substrate is characterized by comprising a plurality of sub-pixel units; each of the sub-pixel units includes:
a gate layer;
the source-drain electrode layer is arranged on the grid electrode layer;
the organic insulating layer is arranged on the source-drain electrode layer;
a common electrode formed of a transparent material and disposed on the organic insulating layer;
a passivation layer disposed on the common electrode;
the pixel electrode is arranged on the passivation layer, and the common electrode and the pixel electrode form a storage capacitor of the array substrate;
in the top view direction of the array substrate, the orthographic projection of the pixel electrode on the public electrode is positioned in the public electrode, the dielectric constant of the passivation layer is larger than that of the organic insulating layer, and the ratio of the thickness of the organic insulating layer to the thickness of the passivation layer is larger than or equal to 2; the material of the passivation layer is at least one of silicon nitride, silicon oxide and silicon oxynitride, and the material of the organic insulating layer is at least one of acrylic resin, polytetrafluoroethylene, polycarbonate and polystyrene; the common electrode is formed with an opening in a disposition region corresponding to the thin film transistor.
2. The array substrate of claim 1, wherein the common electrodes in two adjacent sub-pixel units are continuously and electrically connected.
3. The array substrate of claim 1, wherein the materials of the common electrode and the pixel electrode each include at least one of indium tin oxide, indium oxide, tin dioxide, zinc oxide, chromium oxide, and indium zinc oxide.
4. The array substrate of claim 1, further comprising:
a gate insulating layer disposed on the substrate and covering the gate layer;
the active layer is arranged on the grid insulating layer and corresponds to the grid layer; and
the source-drain electrode layer is arranged on the gate insulating layer and is electrically connected with the active layer.
5. The array substrate of claim 1, further comprising:
the shading layer is arranged on the substrate;
the buffer layer is arranged on the substrate and covers the shading layer;
an active layer disposed on the buffer layer;
a gate insulating layer disposed on the active layer;
a gate layer disposed on the gate insulating layer;
an interlayer insulating layer disposed on the buffer layer and entirely covering the active layer, the gate insulating layer, and the gate layer; and
the source-drain electrode layer is arranged on the interlayer insulating layer.
6. A display panel comprising an array substrate, a counter substrate, and a liquid crystal layer disposed between the array substrate and the counter substrate, wherein the array substrate is the array substrate according to any one of claims 1 to 5.
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| CN202210171718.1A CN114428426B (en) | 2022-02-24 | 2022-02-24 | Array substrate and display panel |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103278986A (en) * | 2013-04-01 | 2013-09-04 | 京东方科技集团股份有限公司 | Array substrate, display device and manufacturing method of array substrate |
| CN104166278A (en) * | 2013-05-16 | 2014-11-26 | 瀚宇彩晶股份有限公司 | Pixel array substrate |
| CN106855670A (en) * | 2017-02-28 | 2017-06-16 | 厦门天马微电子有限公司 | Array base palte, display panel and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103487999B (en) * | 2013-05-24 | 2016-03-02 | 合肥京东方光电科技有限公司 | A kind of array base palte, preparation method and display device |
| CN103472646B (en) * | 2013-08-30 | 2016-08-31 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof and display device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103278986A (en) * | 2013-04-01 | 2013-09-04 | 京东方科技集团股份有限公司 | Array substrate, display device and manufacturing method of array substrate |
| CN104166278A (en) * | 2013-05-16 | 2014-11-26 | 瀚宇彩晶股份有限公司 | Pixel array substrate |
| CN106855670A (en) * | 2017-02-28 | 2017-06-16 | 厦门天马微电子有限公司 | Array base palte, display panel and display device |
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