CN100452412C - Pixel structure and manufacture method and photoelectronic device with the pixel structure and manufacture method - Google Patents

Pixel structure and manufacture method and photoelectronic device with the pixel structure and manufacture method Download PDF

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CN100452412C
CN100452412C CN 200710105863 CN200710105863A CN100452412C CN 100452412 C CN100452412 C CN 100452412C CN 200710105863 CN200710105863 CN 200710105863 CN 200710105863 A CN200710105863 A CN 200710105863A CN 100452412 C CN100452412 C CN 100452412C
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substrate
layer
thin film
film transistor
pixel structure
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CN101060127A (en
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俞善仁
彭中宏
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友达光电股份有限公司
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Abstract

本发明是有关于一种像素结构及其制造方法以及包含该像素结构的光电装置及其制造方法,像素结构包含至少一栅极线、至少一数据线、至少一薄膜晶体管与至少一像素电极。 The present invention relates to a method of manufacturing the pixel structure and method of manufacturing a photovoltaic device comprising the pixel structure, comprising at least one pixel structure of the gate line, the at least one data line, at least one of the at least one thin film transistor and the pixel electrode. 该方法于一基板形成栅极线与数据线,数据线与栅极线实质上相互交错,并在栅极在线形成薄膜晶体管,薄膜晶体管耦接栅极线与数据线,且于基板形成像素电极,像素电极耦接薄膜晶体管。 The method of forming a gate electrode on a substrate and data lines, the data lines and the gate lines are substantially interdigitated, thin film transistor and the gate line, the thin film transistor coupled to the gate lines and data lines, and a pixel electrode formed on the substrate , a thin film transistor coupled to the pixel electrode.

Description

像素结构与制造方法及含像素结构的光电装置与制造方法 Pixel structure and the manufacturing method and manufacturing method of a photovoltaic device having a pixel structure

技术领域 FIELD

本发明是有关于一种显示器,特别是有关于显示器中的一种像素结构及其制造方法。 The present invention relates to a display, particularly to a method of manufacturing a pixel structure on display.

背景技术 Background technique

由于现今平面显示器,如液晶显示器(LCD)、等离子体显示器(PDP) 与有机发光二极管显示器(OLED display)等,不论在分辨率、重量、厚度、 反应速度以及耗电量等特性上皆优于传统的阴极射线管(Cathode Ray Tube, CRT)显示器,所以平面显示器已渐渐取代传统的阴极射线管显示器。 Because nowadays flat panel display, liquid crystal display (LCD), a plasma display (PDP) and organic light emitting diode display (OLED display) and the like, are superior in resolution regardless of the weight, thickness, and other characteristics of the reaction rate and the power consumption conventional cathode ray tube (cathode ray tube, CRT) display, a flat-panel display thus has gradually substituted for conventional cathode ray tube displays. 再加上, 近年来平面显示器的技术进步突飞猛进,且随着电子产品用途的不断扩大,所以平面显示器的应用也越来越为广泛。 Plus, in recent years, rapid technological advances in flat-panel displays, and with the growing use of electronic products, the application of flat-panel displays are also more and more widely.

公知平面显示器包含多个像素结构,而每一像素结构如图1与图2所示, 其中图1为储存电容设置于公共电极上,图2为储存电容设置于栅极线1:。 Known pixel structure comprises a plurality of flat display, and each of the pixel structure shown in FIGS. 1 and 2, wherein FIG. 1 is a storage capacitor disposed on a common electrode, the storage capacitor 2 is provided to the gate line 1 :. 请参阅图1A与图2B,其为公知像素结构俯视示意图。 Please refer to FIG. 1A and FIG. 2B, which is a schematic top view of a known pixel structure. 如图所示,公知像素结构100包含一栅极线120、 一数据线130、 一薄膜晶体管140、 一像素电极160 与一公共线170,栅极线120、数据线130、薄膜晶体管140、像素电极160 与公共线170,且设置于一第一基板(图未示)上。 As shown, a known pixel structure 100 includes a gate line 120, a data line 130, a thin film transistor 140, a pixel electrode 160 and a common line 170, the gate line 120, data line 130, the thin film transistor 140, a pixel electrode 160 and the common line 170, and is disposed on a first substrate (not shown). 其中,栅极线120与数据线130相互交错。 Wherein the gate line 120 and data line 130 cross each other. 薄膜晶体管140包含一栅极(图未示)、一源极M4、 一漏极146与一半导体层148,薄膜晶体管140的栅极为部分栅极线120所构成, 且薄膜晶体管"0的半导体层148对应于薄膜晶体管140的栅极,半导体层148与薄膜晶体管140的栅极之间设有一绝缘层(图未示),薄膜晶体管140 的源极144与漏极146分别设置于半导体层148的两侧,且分别延伸至栅极线120两侧,而分别耦接数据线130与像素电极160,且像素电极160经山一通孔149耦接漏极146。公共线170与栅极线120平行设置于第一基板上,像素电极160与公共线170间形成一储存电容162。 The thin film transistor 140 comprises a gate electrode (not shown), a source of M4, a drain electrode 146 and a semiconductor layer 148, the thin film transistor 140 a gate portion of the gate line 120 is formed, and a thin film transistor "in the semiconductor layer 0 148 corresponds to the gate of the thin film transistor 140, the semiconductor layer 148 between the gate of the thin film transistor 140 is provided with an insulating layer (not shown), a source electrode 144 of the thin film transistor 140 and the drain 146 are disposed on the semiconductor layer 148 sides, respectively, and extend to both sides of the gate lines 120, respectively coupled to the data line 130 and pixel electrode 160, and the pixel electrode 160 via a through hole 149 mountain coupled to common line 146. the drain electrode 120 parallel with gate line 170 disposed on the first substrate, the pixel electrodes 160 and 162 form a storage capacitor common line 170.

承接上述,由于像素电极160为透明导电材质,所以像素电极160的区域 Continuation of the above, since the pixel electrode 160 is a transparent conductive material, so the area of ​​the pixel electrode 160

即为透光区域,然而公共线170会阻隔部分透光区域。 It is the light-transmitting region, but will block the common line 170 partially transparent region. 现今为了防止像素发生漏光的情形,第一基板或者相对于第一基板的一第二基板(图未示)会在对应于像素电极160的周围设置一黑色矩阵190,如图1B所示,以阻隔光线自透光区域的周围漏出,所以像素电极160未受黑色矩阵190覆盖的区域与未受公共线170阻隔的区域,即为显示区域180。 In order to prevent light leakage in the case of the current pixel occurs, the first substrate or the second substrate with respect to a first substrate (not shown) will be provided corresponding to the pixel electrode 190 surrounding a black matrix 160, shown in Figure 1B, to light from the light-transmissive region surrounding the barrier leakage, the pixel electrode 160 region were not the black matrix region 190 and common line 170 were not covered with the barrier, i.e. the display area 180. 由于常用像素结构IOO的漏极146 及/或源极144整个位于像素电极160所在的透光区域中,再者漏极146与源极144的材质为不透光材质,所以漏极146与源极144也阻挡了部分光线,如此会縮减像素结构100的显示区域180,也即造成像素结构100的开口率(apertureratio)降低,且也会导致透光率降低。 Since the drain IOO common pixel structure 146 and / or 144 the entire source electrode located on the light-transmitting region where the pixel 160, the drain 146 and source addition 144 is made of an opaque material, so that the drain 146 and the source electrode 144 also blocks some of the light, thus the display region 180 will reduce the pixel structure 100, i.e. causing the opening ratio (apertureratio) pixel structure 100 is lowered, and also lead to decrease in light transmittance.

请参阅图2A与图2B,其为具蚀刻终止型薄膜晶体管的公知像素结构的俯视示意图。 Refer to FIG. 2A and FIG. 2B, which is well-known a schematic plan view of a pixel structure having the etch stop type thin film transistor is. 如图所示,图1A与图2A的不同之处在于图2A的像素结构200 的薄膜晶体管240为一蚀刻终止型薄膜晶体管,且设置于栅极线220的一侧, 蚀刻终止型薄膜晶体管240具有一蚀刻停止层241 ,其对应于薄膜晶体管240 的栅极242,且设置于薄膜晶体管240的半导体层(图未示)上,薄膜晶体管240的源极244与漏极246分别设置于蚀刻停止层241的两侧。 As shown, FIG. 1A is different from the pixel structure of FIG. 2A in FIG. 2A, a thin film transistor 200 is an etch stop 240 type thin film transistor, and is disposed on one side of the gate line 220, the etch stop type thin film transistor 240 having an etch stop layer 241, which corresponds to the gate of the thin film transistors 242,240, and is disposed on the semiconductor layer (not shown) on the thin film transistor 240, the source of the thin film transistor 240 and the drain electrode 244 are disposed on the etch stop 246 layer 241 on both sides. 其中,源极244 耦接于数据线230,而像素电极260经由通孔249耦接漏极246。 Wherein, the source 244 is coupled to the data line 230, the pixel electrode 260 via a through hole 249 is coupled to the drain 246. 另外,图2A 的像素结构200的像素电极260也延伸设置于下一级栅极线220上,而形成一储存电容262。 Further, the pixel electrode 260 of the pixel structure 200 of FIG. 2A also extend at an upper gate line 220, a storage capacitor 262 is formed. 由于图2A的像素结构200的薄膜晶体管240设置于栅极线220 的一侧,因此如图2B所示,黑色矩阵290会因为覆盖薄膜晶体管240及其周围而覆盖到栅极线220的侧面区域,而縮减像素结构200的显示区域280因薄膜晶体管240的位置縮小而导致像素结构200的开口率降低,且也会导致透光率降低。 Since the pixel structure 200 of FIG. 2A, a thin film transistor 240 is disposed at a side of the gate line 220, thus shown in Figure 2B, because the black matrix 290 covers the thin film transistor 240 and its surrounding area to cover the side surfaces of the gate line 220 while reducing the pixel structure of the display region 200 of the thin film transistor 280 due to the position of the pixel 240 is reduced resulting in reducing the aperture ratio structure 200 and can also lead to decrease in light transmittance.

发明内容 SUMMARY

本发明的主要目的,在于提供一种像素结构及其制造方法以及包含该像素结构的光电装置及其制造方法,其增加像素结构的显示区域,以增加像素结构的开口率。 The main object of the present invention is to provide a method of manufacturing the pixel structure and the method of manufacturing a photovoltaic device comprising a pixel structure, which increases the display area of ​​the pixel structure in order to increase the aperture ratio of the pixel structure.

本发明的次要目的,在于提供一种像素结构及其制造方法以及包含该像素结构的光电装置及其制造方法,其为利用薄膜晶体管设置于栅极线,以增加像素结构的开口率。 Secondary object of the present invention is to provide a method of manufacturing the pixel structure and the method of manufacturing a photovoltaic device comprising a pixel structure, which is provided by a thin film transistor to the gate lines, to increase the aperture ratio of the pixel structure.

本发明关于一种像素结构,其包含一基板,其上设置实质上相互交错的至少一栅极线与至少一数据线、至少一薄膜晶体管与至少一像素电极,其中薄膜晶体管位于栅极线,且薄膜晶体管耦接栅极线与数据线及像素电极。 The present invention relates to a pixel structure, comprising a substrate having disposed on at least a substantially interdigitated gate line and at least one data line, at least one of the at least one thin film transistor and the pixel electrode, the thin film transistor wherein the gate line, and a thin film transistor coupled to the gate lines and data lines and the pixel electrode.

本发明关于一种像素结构的制造方法,其先提供一基板,并形成至少一栅极线、至少一数据线、至少一薄膜晶体管与至少一像素电极于基板上,其中栅极线与数据线实质上相互交错,薄膜晶体管形成于栅极线而与栅极线相对,并耦接栅极线、数据线与像素电极。 The present invention relates to a method of manufacturing a pixel structure, which first providing a substrate, forming at least one gate line and at least one data line, at least one of the at least one thin film transistor and the pixel electrode on the substrate, wherein the gate lines and data lines substantially interdigitated, thin film transistors formed on the gate line and the gate lines opposite and coupled to the gate line, the data line and the pixel electrode.

本发明关于一种光电装置,其具有本发明所述的像素结构。 The present invention relates to a photovoltaic device having a pixel structure according to the present invention.

本发明关于一种光电装置的制造方法,其具有本发明所述的像素结构的形成方法。 The present invention relates to a method for manufacturing a photovoltaic device having a method of forming the pixel structure of the present invention.

为让本发明上述和其它目的、特征和优点能更明显易懂,下文特举较佳实施例,并配合附图,作详细说明如下。 To make the above and other objects, features and advantages of the present invention can be more fully understood by reading the following preferred embodiments accompanied with figures are described in detail below.

附图说明 BRIEF DESCRIPTION

图1A为公知像素结构俯视示意图; 1A is a schematic top view of a known pixel structure;

图1B为图1A的像素结构的显示区域的俯视示意图; FIG 1B is a schematic top view of the pixel structure of the display area in FIG. 1A;

图2A为公知具有蚀刻终止型薄膜晶体管的像素结构的俯视示意图; Figure 2A schematic top view of a pixel structure having the etch stop type thin film transistor is known;

图2B为图2A的像素结构的显示区域的俯视示意图; 2B is a schematic top view of the pixel structure of the display area in FIG. 2A;

图3A为本发明的像素结构的一实施例的俯视示意图; Figure 3A schematic top view of an embodiment of a pixel structure of the present invention;

图3B为图3A的像素结构的显示区域的俯视示意图; FIG 3B is a top view of the pixel structure of the display region of FIG. 3A;

图4为图3A的一实施例的剖视图; FIG 4 is a cross-sectional view of an embodiment of FIG. 3A;

图5为图3A的另一实施例的剖视图; FIG 5 is a cross-sectional view of another embodiment of the embodiment of FIG. 3A;

图6为图3A的另一实施例的剖视图; FIG 6 is a cross-sectional view of another embodiment of the embodiment of FIG. 3A;

图7为本发明的像素结构的另一实施例的剖视图; A cross-sectional view of another embodiment of the pixel structure of FIG. 7 embodiment of the present invention;

图8为本发明的像素结构的另一实施例的俯视示意图; Another pixel structure of the present invention Figure 8 a schematic top view of the embodiment;

图9为图8的一实施例的剖视图; 9 is a cross-sectional view of the FIG. 8 embodiment;

图IOA为本发明的像素结构的另一实施例的俯视示意图; 图10B为图10A的像素结构的显示区域的俯视示意图; 图11为图10A的一实施例的剖视图; 图12A为本发明的像素结构的另一实施例的俯视示意图;图12B为图12A的像素结构的显示区域的俯视示意图; FIG IOA another pixel structure of the present invention, a schematic top view of an embodiment; FIG. 10B is a schematic top view of the pixel structure of the display area in FIG. 10A; FIG. 10A is a cross-sectional view of the embodiment of Figure 11; FIG. 12A of the present invention. another embodiment of the pixel structure a schematic plan view; FIG. 12B is a schematic top view of the display area of ​​the pixel structure in FIG 12A;

图13为图12A的一实施例的剖视图; 13 is a cross-sectional view of FIG. 12A in the embodiment;

图14为图12A的另一实施例的剖视图; FIG 14 is a cross-sectional view of another embodiment of the embodiment of FIG. 12A;

图15为图12A的另一实施例的剖视图; FIG 15 is a cross-sectional view of another embodiment of the embodiment of FIG. 12A;

图16为本发明的像素结构的另一实施例的俯视示意图; Another pixel structure in FIG. 16 of the present embodiment of the invention a schematic plan view;

图17为图16的一实施例的剖视图;以及 FIG 17 is a cross-sectional view of an embodiment of FIG. 16; and

图18为本发明的光电装置的一实施例的俯视示意图。 Top view of an embodiment of the photovoltaic device 18 of the present invention. FIG.

其中, 附图标记: Wherein, reference numerals:

100 像素结构 314 绝缘层 120栅极线 130 数据线 320 栅极线 412 虚设图案 Gate line 120 structure 314 by 100 pixels insulating layer 130 of the gate line 412 data line 320 dummy pattern

140 薄膜晶体管 322 绝缘层 420 栅极线 140 thin film transistor 322 a gate insulating layer 420 lines

144 源极 330 数据线 422 绝缘层 The source data line 144 330 422 insulating layer

146 漏极 332 掺杂半导体层 424 延伸部 146 332 doped drain extension portion of the semiconductor layer 424

148 半导体层 334 掺杂半导体层 430 数据线 148 The semiconductor layer 334 doped semiconductor layer, the data line 430

149 通孔 340 薄膜晶体管 432 掺杂半导体层 The thin film transistor 149 through hole 340 doped semiconductor layer 432

160 像素电极 344 源极 434 掺杂半导体层 The pixel electrode 344 of the source 160 doped semiconductor layer 434

162 储存电容 346 漏极 440 薄膜晶体管 Drain electrode 162 of the storage capacitor 346 TFT 440

170 公共线 348 半导体层 444 源极 170 common line 348 of the semiconductor layer 444 of the source

180 显示区域 349 通孔 446 漏极 Display region 180 through hole 446 drain electrode 349

190 黑色矩阵 352 保护层 448 半导体层 The black matrix 190 protective layer 448 of the semiconductor layer 352

200 像素结构 360 像素电极 449 通孔 The pixel structure 200 through hole 360 ​​of the pixel electrode 449

220 栅极线 362 具介电系数的层 452 保护层 Gate line 220 layer 452 protective layer 362 dielectric constant

230 数据线 364 绝缘层 454 通孔 230 data lines 364 through the insulating layer 454 hole

240 薄膜晶体管 366 电极 460 像素电极 The thin film transistor 240 of the pixel electrode 366 electrode 460

244 源极 370 公共线 462 具介电系数的层 Layer of dielectric constant 462 244 370 common source line

246 漏极 372 储存电容 470 公共线 246 the drain 372 of the storage capacitor common line 470

249 通孔 380 黑色矩阵 472 储存电容 249 through hole 380 of the black matrix 472 of the storage capacitor

260 像素电极 381 缓冲层 480 黑色矩阵 The pixel electrode 260 a buffer layer 480 of the black matrix 381

262 储存电容 382 显示区域 481 缓冲层 262 of the storage capacitor 382 display region 481 of the buffer layer

280 显示区域 384 滤色片层 484 滤色片层 Display area 384 280 484 color filter layer of the color filter layer

300 像素结构 386 平坦层 486 平坦层 The pixel structure 300 planarization layer 386 planarization layer 486

310 第一基板 388 公共电极 488 公共电极 The first substrate 310 the common electrode 388 common electrode 488

312 虚设图案 390 第二基板 4卯 第二基板 A second dummy pattern 312 of the substrate 390 of the second substrate 4 d

512 虚设图案 400 像素结构 500 像素结构 The pixel structure 400 pixel structure 512 of the dummy pattern 500

520 栅极线 410 第一基板 510 第一基板 Gate line 520 of the first substrate 510 of the first substrate 410

530 数据线 630 数据线 730 数据线 A data line 530 data line 630 data line 730

532 掺杂半导体层 632 掺杂半导体层 732 掺杂半导体层 Doped semiconductor layer 532 doped semiconductor layer 632 doped semiconductor layer 732

534 掺杂半导体层 634 掺杂半导体层 734 掺杂半导体层 534 doped semiconductor layer 634 doped semiconductor layer 734 doped semiconductor layer

540 薄膜晶体管 640 薄膜晶体管 740 薄膜晶体管 The thin film transistor 540 thin-film transistor 740 thin-film transistor 640

544 源极 644 源极 744 源极 The source source 544 644 744 source

546 漏极 646 漏极 746 漏极 Drain 646 746 546 drain the drain

548 半导体层 648 半导体层 748 半导体层 The semiconductor layer 648 of the semiconductor layer 548 of the semiconductor layer 748

549 通孔 649 通孔 749 通孔 549 through hole 649 through hole 749 through hole

552 保护层 650 蚀刻终止层 750 蚀刻终止层 552 protective layer 650 etch stop layer 750 is an etch stop layer

560 像素电极 652 保护层 752 保护层 The pixel electrode 560 a protective layer 652 protective layer 752

562 具介电系数的层 660 像素电极 754 通孔 Dielectric constant layer 562 through-hole 660 of the pixel electrode 754

570 公共线 662 储存电容 760 像素电极 A storage capacitor common line 662 570 the pixel electrode 760

572 储存电容 664 具介电系数的层 762 储存电容 572 of the storage capacitor 664 dielectric constant layer 762 of the storage capacitor

580 黑色矩阵 666 绝缘层 764 具介电系数的层 Layer 764 dielectric constant insulating layer 580 of the black matrix 666

581 缓冲层 670 黑色矩阵 770 黑色矩阵 581 a buffer layer 670 of the black matrix of the black matrix 770

582 显示区域 671 缓冲层 771 缓冲层 582 display region 671 of the buffer layer 771 of the buffer layer

584 滤色片层 672 显示区域 774 滤色片层 The color filter layer 584 color filter layer 672 display region 774

586 平坦层 674 滤色片层 776 平坦层 A color filter layer 586 planarization layer 674 planarization layer 776

588 公共电极 676 平坦层 778 公共电极 Planarization layer 588 common electrode 778 of the common electrode 676

590 第二基板 678 公共电极 780 第二基板 678 common electrode 590 of the second substrate, a second substrate 780

600 像素结构 680 第二基板 800 显示单元 The pixel structure 600 display unit 680 of the second substrate 800

610 第一基板 700 像素结构 802 像素结构 802 pixel 700 pixel structure of a first substrate structure 610

612 绝缘层 710 第一基板 810 光电装置 612 substrate 810 insulating layer 710 of the first photovoltaic device

620 栅极线 720 栅极线 724 延伸部 The gate line 620 extending portion 720 of the gate line 724

622 绝缘层 722 绝缘层 Insulating layer 722 insulating layer 622

具体实施方式 Detailed ways

请参阅图3A,其为本发明的像素结构的第一实施例的俯视示意图。 Please refer to Figure 3A, a top view of a first embodiment of a pixel structure which the present invention. 如图所示,本发明的像素结构300包含一第一基板310 (如图4所示)、至少一栅极线320、至少一数据线330、至少一薄膜晶体管340与至少一像素电极360, 其中栅极线320、数据线330、薄膜晶体管340与像素电极360设置于第一基板310上。 As shown, the pixel structure 300 of the present invention comprises a first substrate 310 (FIG. 4), at least a gate line 320, a data line at least 330, at least one of the at least one thin film transistor 340 and the pixel electrode 360, wherein the gate line 320, data line 330, the thin film transistor 340 and the pixel electrode 360 ​​disposed on the first substrate 310. 栅极线320与数据线330实质上相互交错,此实施例的薄膜晶体管340位于栅极线320上而与栅极线320相对,薄膜晶体管340耦接于栅极线320、 数据线330与像素电极360。 The gate line 320 and data line 330 are substantially interdigitated, thin film transistor 340 is positioned on the gate line 320 and gate line 320 is relatively thin film transistor 340 is coupled to the gate line 320, data line 330 and the pixel of this embodiment electrode 360. 其中,相对于薄膜晶体管340的部分栅极线320 以作为薄膜晶体管340的一栅极,而薄膜晶体管340的一半导体层348设置于栅极上方,也即半导体层348位于栅极线320相对于薄膜晶体管340的区域上方,薄膜晶体管340的一源极344与一漏极346设置于半导体层348上,且皆位于栅极线320上,其中源极344耦接于数据线330。 Wherein a portion of the gate line 320 with respect to the thin film transistor 340 as a gate electrode of the thin film transistor 340, and a semiconductor layer of the thin film transistor 340 is disposed above the gate electrode 348, a semiconductor layer 348 that is positioned with respect to the gate line 320 a region above the thin film transistor 340, a source 340 of the thin film transistor 344 and a drain electrode 346 disposed on the semiconductor layer 348, and are located on the gate line 320, a source 344 which is coupled to data line 330. 像素电极360经由相对于栅极线320的一通孔(Through Hole, TH) 349耦接于漏极346。 The pixel electrode 360 ​​with respect to the gate line through a hole (Through Hole, TH) 320 is coupled to the drain 349 through 346.

承接上述,第一基板310上更设置一公共线370,且公共线370与栅极线320实质上平行,因此公共线370也与数据线330实质上相互交错,且公共线370与像素电极360之间形成一储存电容372。 Continuation of the above, a more common line 370 provided on a first substrate 310, and the common line 370 is substantially parallel with the gate line 320, so the common line 370 and data line 330 is also substantially interdigitated, and the common line 370 and the pixel electrode 360 a storage capacitor 372 is formed between. 在本实施例屮,像素电极360 为透明导电材质,因此像素电极360的区域即为像素结构300的透光区域,但公共线370为非透明导电材质,所以公共线370阻隔了像素结构300部分透光区域。 In the present embodiment Cao embodiment, the pixel electrode 360 ​​is a transparent conductive material, so the area of ​​the pixel electrode 360 ​​is the transmissive region of the pixel structure 300, the common line 370 is non-transparent conductive material, so the common line 370 of the pixel structure 300 portion of the barrier translucent area.

另外,如图3B所示,像素结构300的第一基板310或者相对于第-•基板310的一第二基板390 (如图4所示)会在相对于像素电极360的周围设置一黑色矩阵380,以覆盖部分该栅极线320、部分该数据线330、该薄膜晶体管340及部分该像素电极360,以防止像素发生漏光的情形。 Further, as shown in FIG. 3B, the pixel structure of the first substrate 300 or 310 with respect to the first - • substrate of a second substrate 390,310 (FIG. 4) will be around the pixel electrode with respect to a black matrix 360 is provided 380, to cover a portion of the gate line 320, a portion of the data line 330, the thin film transistor 340 and a portion of the pixel electrode 360 ​​to prevent light leakage in the case of occurrence of a pixel. 由于通过像素电极360的光线会受到黑色矩阵380的遮蔽与受到公共线370阻隔,所以像素电极360未受黑色矩阵380覆盖与未受公共线370阻隔的区域,即为显示区域382。 Since light passing through the pixel electrode 360 ​​of the black matrix will be shielded by the common line 370 and the barrier 380, the pixel electrode 360 ​​were not covered with the black matrix region 380 common line 370 unaffected barrier, i.e. the display area 382. 由于本发明的薄膜晶体管340位于栅极线320上,因此黑色矩阵380覆盖栅极线320的同时也会覆盖薄膜晶体管340,所以由图1B与图3B比较可明显得知, 本发明实施例的像素结构300的开口率较常用像素结构100的开口率大,其主要是因为常用像素结构100的漏极146及/或源极144整个位于像素电极160 所在的透光区域中。 Since the thin film transistor 340 according to the present invention positioned on the gate line 320, and therefore the black matrix 380 while covering the gate line 320 also cover the thin film transistor 340, so the comparison 1B and 3B evident that, embodiments of the present invention. aperture ratio of the pixel structure of the pixel structure 300 of the more common large aperture 100, 146 whose common drain primarily because the pixel structure 100 and / or 144 the entire source region of the transmissive pixel electrode 160 is located. 再者漏极146与源极144的材质为不透光材质,所以漏极 Note that the drain 146 and source 144 is made of an opaque material, so that the drain

146及/或源极144阻挡了部分光线,而使得开口率增加降低,也就是说本发明的像素结构300的显示区域382实质上大于常用像素结构100的显示区域180, 相对而言,本发明的像素结构300的开口率也相对提高。 146 and / or source part 144 blocks the light, such that the opening ratio increases decreases, i.e. the pixel structure of the present invention, the display area is substantially larger than 382,300 common display region 180 of the pixel structure 100, relatively speaking, the present invention the aperture ratio of the pixel structure 300 is also enhanced.

此外,本发明的像素结构300的另一实施例,可不需在第一基板310上设置公共线370,而将像素电极360延伸覆盖至下一栅极线320的部分区域,以在下一栅极线320的部分区域形成储存电容,如此显示区域382即不会受公共线370影响而縮减,因此可增加像素结构300的显示区域382面积以及开口率。 In addition, another pixel structure 300 of the present invention embodiments may be provided without the common line 370 on the first substrate 310, and the pixel electrode 360 ​​extend over a partial region to a next gate line 320 to the next gate forming a partial region of the storage capacitor line 320, i.e., such a display region 382 does not affect the common line 370 by the reduction and thus increases the area of ​​the display region 382 and the opening ratio of the pixel structure 300. 此外,为了检测像素结构300的缺陷,因此第一基板310上更设置至少一虚设图案(dummy pattern) 312,以检测像素结构300的缺陷(如:残留物与像素结构300内任一层导体层及/或半导体层接触所产生的短路等),在此实施例中第一基板310上设置多个虚设图案312,其位于像素结构300的四个角落, 此仅为本发明的一实施例并不局限虚设图案312所设置的位置,也nj选择性地设置于像素结构300中的任一位置,例如:环绕该显示区域、设置于易发生残留物之处、平行栅极线320、数据线330、公共线370的其中至少一者设置、 或其它设置方式。 Further, in order to detect defective pixel structure 300, thus further providing at least a dummy pattern (dummy pattern) 312 on the first substrate 310 to detect defective pixel structure 300 (e.g.,: residue 300 within the pixel structure of a conductor layer according to any one and / or a short circuit in contact with the semiconductor layer generated), in this embodiment, a plurality of dummy patterns on a first substrate 310, 312 located in the four corners of the pixel structure 300, this is merely an embodiment of the present invention and the dummy pattern 312 is not limited to the set position, nj selectively disposed in the pixel structure 300 in any position, for example: around the display region, provided at the prone residues, parallel to the gate line 320, data line 330, common line 370 is provided wherein at least one, or other arrangement. 本发明实施例的虚设图案312是以曝露出第-基板310的通孔为例,但不限于此,也可选择性地为沟槽、狭缝、或上述的混合使用。 Example dummy pattern 312 of the present invention is to expose the first - the through holes of the substrate 310 as an example, but is not limited thereto, and also optionally for the grooves, slits, or the above mixture. 当然, 若像素结构300不需要检测,则虚设图案312也可不设置。 Of course, no need to detect if the pixel structure 300, the dummy pattern 312 may not be provided. 又,本发明的像素结构300,较佳地,更包含至少一遮光层(图未示),其设置于该第一基板310 上,并与该数据线330及该栅极线320的至少一者平行,但不限于此,也可不包含遮光层。 Further, the pixel structure 300 of the present invention, preferably, further comprising at least a light-shielding layer (not shown), which is disposed on the first substrate 310, and at least one of the data line 330 and the gate line 320 They are parallel, but not limited thereto, and may not include the light shielding layer.

请参阅图4,其为图3A的AA'方向的剖视图。 Please refer to FIG. 4, which is a cross-sectional view AA 'direction in FIG. 3A. 如图所示,本发明的像素结构300的栅极线320与公共线370设置于第一基板310上,此实施例的薄膜晶体管340位于栅极线320上,其中相对于薄膜晶体管340的部分栅极线320 以作为薄膜晶体管340的栅极。 As shown, the pixel structure of the present invention, the gate lines 300 and 320 of the common line 370 provided on the first substrate 310, a thin film transistor 340 of this embodiment is located on the gate line 320, wherein the portion of the thin film transistor 340 with respect to the gate line 320 as a gate electrode 340 of the thin film transistor. 一绝缘层322设置于第一基板310、部分栅极线320与/或公共线370上。 An insulating layer 322 disposed on the first substrate 310, the common line or the gate line 320 and the portion 370 /. 半导体层348设置于绝缘层322上,且半导体层348位于相对薄膜晶体管340的部分栅极线320的位置。 The semiconductor layer 348 disposed on the insulating layer 322, and the semiconductor layer 348 located at a position opposing the thin film transistor 340 portion of the gate line 320. 源极344与漏极346 设置于半导体层348的二端。 The source 344 and drain 346 disposed at the two ends of the semiconductor layer 348. 再者,本发明的实施例,较佳地,设置掺杂半导体层332、 334于半导体层348上,且分别位于与源极344及漏极346接触之处,以降低电阻值。 Furthermore, embodiments of the present invention, preferably, provided a doped semiconductor layer 332, 334 on the semiconductor layer 348, electrode 344 and located in contact with the source and the drain electrode 346, to reduce the resistance value. 源极344、漏极346与位于源极344和漏极346之间的半导体层348上设置一保护层352,保护层352也设置于相对部分第一基板310与公共线370的绝缘层322上。 A source electrode 344, drain electrode 346 and 348 positioned on the semiconductor layer between the source electrode 344 and the drain electrode 346 provided with a protective layer 352, protective layer 352 is also disposed on opposing portions of the first substrate 310 and the common line 370 an insulating layer 322 . 像素电极360设置于第一基板310上,且位于保护层352上,而像素电极360经通孔349耦接漏极346,且像素电极360与公共线370之间形成储存电容372。 The pixel electrode 360 ​​is disposed on the first substrate 310 and located on the protective layer 352 and the pixel electrode 360 ​​through the through hole 349 is coupled to the drain electrode 346, and the pixel electrode 360 ​​is formed between the storage capacitor common line 370 and 372.

承接上述,像素结构300更包含有一第二基板390,其相对于第一基板310 设置,第二基板390具有黑色矩阵380、 一滤色片层384与公共电极388。 Continuation of the above, the pixel structure 300 further includes a second substrate 390, 310 is provided with respect to the first substrate, a second substrate 390 having a black matrix 380, a color filter layer 384 and the common electrode 388. 其中黑色矩阵380设置于部分第二基板390,且对应于栅极线320、薄膜晶体管340与数据线(图未示),且滤色片层384设置于对应像素电极360的第二基板390上。 Wherein the black matrix 380 disposed on the second substrate portion 390, and corresponds to the gate line 320, data line 340 (not shown), and the color filter layer 384 disposed on the second substrate corresponding to the pixel electrode 390 of the thin film transistor 360 . 公共电极388设置于滤色片层384上且耦接一共同电压,其与数据线传送至像素电极360的数据信号产生压差变化,因而驱使像素电极360与公共电极388所接触的一具介电系数的层362依据电压差变化显示对应的灰阶亮度。 The common electrode 388 is disposed on the color filter layer 384 and is coupled to a common voltage, which transmits the data signal to the data lines of the pixel electrodes 360 generate pressure changes, thereby driving the pixel electrode 360 ​​via a contact with the common electrode 388 coefficient of layer 362 corresponding to the display gray level according to the voltage difference change. 其中,具介电系数的层362为一液晶层、 一发光层(如:有机材料、无机材料、或上述的组合)或上述的组合,以显示对应的灰阶亮度。 Wherein the layer has a dielectric constant of a liquid crystal layer 362, a light-emitting layer (such as: an organic material, an inorganic material, or combinations thereof) or combinations thereof, in order to display the corresponding gray level. 换句话说,具介电系数的层362是设置于第一基板310及第二基板390之间。 In other words, with a dielectric constant layer 362 is disposed between the first substrate 310 and the second substrate 390. 此外,为了能够降低滤色片层384的剥落的现象产生,在本实施例中,较佳地,包含一缓冲层381设置于黑色矩阵380与第二基板3卯上,但不限于此,也可不形成缓冲层381或形成于滤色片层384之下及/或部分黑色矩阵380上。 Further, in order to reduce the phenomenon of peeling of the color filter layer 384 to generate, in the present embodiment, preferably, it comprises a buffer layer 381 disposed on the black matrix 380 and the second substrate 3 Maoshang, but is not limited thereto, and may not be formed / or upper portion of the black matrix 380 and the color filter layer 384 below the buffer layer 381 or formed. 当然,若为了解决滤色片层384的落差问题,在本实施例中,较佳地,包含一平坦层386 设置于黑色矩阵380与滤色片层384上,但不限于此,也可不设置平坦层386。 Of course, if the gap in order to solve the problem of the color filter layer 384, in this embodiment, preferably, comprises a planar layer 386 disposed on the black matrix 380 and the color filter layer 384, but is not limited thereto, and may not be provided planarization layer 386.

请参阅图5,其为图3A的另一实施例的剖视图。 Refer to FIG. 5, a cross-sectional view of another example of embodiment thereof in FIG. 3A. 图5的剖视方向同为图3A的AA'方向。 FIG 5 is a sectional view of the same direction in FIG. 3A direction AA '. 本发明可适用于滤色片于阵列上(Color filter On Array, COA) 型式的像素结构,此种型式的像素结构的滤色片层384位于第一基板310,且位于薄膜晶体管340上。 The present invention can be applied on the array (Color filter On Array, COA) pixel structure type color filter, a color filter layer of this type of pixel structure 384 of the first substrate 310 and located on the thin film transistor 340. 如图所示,此实施例的像素结构300同样具有第一基板310、栅极线320、薄膜晶体管340、像素电极360与储存电容372,而栅极线320、薄膜晶体管340、像素电极360与储存电容372设置于第一基板310 上。 As shown, the pixel structure 300 of this embodiment likewise has a first substrate 310, a gate line 320, the thin film transistor 340, the pixel electrode 360 ​​and storage capacitor 372, and 320, the thin film transistor 340, the pixel electrode 360 ​​and the gate line the storage capacitor 372 is provided on the first substrate 310. 部分栅极线320对应于薄膜晶体管340而作为薄膜晶体管340的栅极。 Portion of the gate line 320 corresponding to the thin film transistor 340 as a gate electrode of the thin film transistor 340. 薄膜晶体管340包含有绝缘层322而设置于栅极线320、部分第一基板310与公共线370上;半导体层348设置于部分绝缘层322上且对应于薄膜晶体管340 的栅极;源极344与漏极346分别设置于半导体层348的二端。 The thin film transistor 340 includes an insulating layer 322 disposed on the gate line 320, a first portion of the substrate 310 and the common line 370; a semiconductor layer 348 disposed on a portion corresponding to the insulating layer 322 and the gate of the thin film transistor 340; source 344 and the drain 346 are provided at two ends of the semiconductor layer 348. 再者,本发明的实施例,较佳地,设置掺杂半导体层332、 334于半导体层348上,且分别与源极344及漏极346接触,以降低电阻值。 Furthermore, embodiments of the present invention, preferably, provided a doped semiconductor layer 332, 334 on the semiconductor layer 348 and the electrode 344 and the drain 346 respectively contact with the source, in order to reduce the resistance. 保护层352设置于源极344、漏极346与部分半导体层348上。 The protective layer 352 disposed on the source electrode 344, drain electrode 346 and the upper portion of the semiconductor layer 348. 像素电极360设置于部分保护层352上,且像素电极360经由通孔349耦接漏极346,此外像素电极360更对应于公共线370 而形成储存电容372。 The pixel electrode 360 ​​is disposed on a portion of the protective layer 352, and the pixel electrode 360 ​​via a through hole 349 is coupled to the drain electrode 346, the pixel electrode 360 ​​in addition to the more common line 370 corresponds to the storage capacitor 372 is formed.

承接上述,像素结构300,较佳地,更包含另一绝缘层364,其设置于薄膜晶体管340与像素电极360上,黑色矩阵380设置于绝缘层364上,由于黑色矩阵380相对于栅极线320,而薄膜晶体管340位于栅极线320上,因此黑色矩阵380同样相对于薄膜晶体管340,滤色片层384设置于绝缘层364上, 但不限于此,也可不设置另一绝缘层364。 Continuation of the above, the pixel structure 300, preferably, further comprising another insulating layer 364, which is disposed on the thin film transistor 340 and the pixel electrode 360, the black matrix 380 is disposed on the insulating layer 364, since the black matrix 380 with respect to the gate line 320, the thin film transistor 340 is located on the gate line 320, the black matrix 380 so the same with respect to the thin film transistor 340, a color filter layer 384 disposed on the insulating layer 364, but is not limited thereto, and another insulating layer 364 may not be provided. 滤色片层384与部分的黑色矩阵380 上设置有平坦层386,但不限于此,也可不设置平坦层386。 The color filter layer 384 with a planarization layer 386 and the upper portion of the black matrix 380 is provided, but are not limited to, planarization layer 386 may not be provided. 也就是,滤色片层384依着的前结构轮廓来形成具有多阶的结构。 That is, 384 according to the outline of the structure of the color filter layer before forming a structure having a plurality of order. 此外,为了能够降低滤色片层384的剥落的现象产生,在本实施例中,较佳地,包含缓冲层381设置于部分绝缘层364及黑色矩阵380上,但不限于此,也可不形成缓冲层381或形成于滤色片层384之下及/或部分黑色矩阵380上。 Further, the color filter layer 384 in order to reduce the peeling phenomenon, in the present embodiment, preferably, comprising a buffer layer 381 disposed on the upper portion of the insulating layer 364 and the black matrix 380, but is not limited thereto, and may not be formed or the buffer layer 381 is formed under the color filter layer 384 / or 380 and the black matrix portion. 再者,像素结构300所包含的第二基板390设有公共电极388,第二基板390相对于第一基板310。 Further, the second substrate 300 included in the pixel structure 390 is provided with a common electrode 388, a second substrate 390 with respect to the first substrate 310.

此外,第一基板310与第二基板390之间还设置有具介电系数的层362 而位于平坦层386与公共电极388之间,此实施例中具介电系数的层362为^ -液晶层,但不限于此,也可为一发光层(如:有机材料、无机材料、或上述的组合)或上述的组合。 In addition, it provided between the first substrate 310 and the second substrate 390 with a layer having a dielectric constant of 362 and 388 located between the planar layer 386 and the common electrode, the dielectric layer 362 in this embodiment according to the coefficient of ^ - liquid crystal layer, but it is not limited thereto, but may be a light-emitting layer (such as: an organic material, an inorganic material, or combinations thereof) or combinations thereof. 由于本发明可用于滤色片于阵列上型式的像素结构中, 也就是滤色片位于薄膜晶体管阵列上型式的像素结构300的薄膜晶体管340 位于栅极线320,因此本发明可让滤色片于阵列上型式的像素结构增加显示区域,以提升显示效能。 Since the present invention can be used in the color filter pattern on the pixel array structure, the color filter is located on the pixel structure type thin film transistor array 340 of thin film transistor 300 the gate line 320, thus the present invention allows the filter on an array type structure increases the pixel display region, to improve the display performance.

请参阅图6,其为图3A的另一实施例的剖视图。 Refer to FIG. 6, a cross-sectional view of another example of embodiment thereof in FIG. 3A. 图6的剖视方向同为图3A的AA'方向。 FIG 6 is a cross-sectional view of the same direction in FIG. 3A direction AA '. 本发明也适用于阵列于滤色片上(Array On Color filter, AOC) 的像素结构,此种型式的像素结构的滤色片层384位于第一基板310,且薄膜晶体管340位于滤色片层384上。 The present invention is also applicable to a pixel on a color filter array structure (Array On Color filter, AOC), the color filter layer of this type of pixel structure 384 of the first substrate 310, the thin film transistor 340 and the color filter layer 384 is located on. 如图所示,此实施例的像素结构300也具有第一基板310,且第一基板310上设有黑色矩阵380、滤色片层384与平坦层386。 As shown, the pixel structure 300 of this embodiment also has a first substrate 310 and the black matrix 380 is provided on the first substrate 310, the color filter layer 384 and the planarization layer 386. 滤色片层384与部分的黑色矩阵380上设置有平坦层386,但不限于此, 也可不设置平坦层386。 The color filter layer 384 with a planarization layer 386 and the upper portion of the black matrix 380 is provided, but are not limited to, planarization layer 386 may not be provided. 此外,为了能够降低滤色片层384的剥落的现象产生, 在本实施例中,较佳地,包含缓冲层381设置于部分第一基板310上及黑色矩阵380上,但不限于此,也可不形成缓冲层381或形成于滤色片层384之下及 Further, in order to reduce the phenomenon of peeling of the color filter layer 384 to generate, in the present embodiment, preferably, comprising a buffer layer 381 disposed on the upper portion of the first substrate 310 and the black matrix 380, but is not limited thereto, and The buffer layer 381 may not be formed or is formed below the color filter layer 384 and

/或部分黑色矩阵380上。 / Or the upper portion of the black matrix 380. 再者,为了改善栅极线320与平坦层386的吸附性, 较佳地,更设置一绝缘层314于平坦层386上。 Further, in order to improve the gate line 320 and the flat absorbent layer 386, preferably, a further insulating layer 314 disposed on the planarization layer 386. 此实施例的栅极线320、薄膜晶体管340、像素电极360与储存电容372设置于绝缘层314上,且薄膜晶体管340与储存电容372电性相接,但不限于此,也可不设置另一绝缘层314。 This embodiment 320 of the gate line embodiment, the thin film transistor 340, the pixel electrode 360 ​​and storage capacitor 372 is provided on the insulating layer 314, and the thin film transistor 340 is electrically in contact with the storage capacitor 372, but is not limited thereto, and may not be further provided the insulating layer 314. 此实施例的薄膜晶体管340位于栅极线320上,对应于薄膜晶体管340的部分栅极线320作为薄膜晶体管340的栅极,且薄膜晶体管340同样包含绝缘层322、半导体层348、源极344、漏极346与保护层352。 The thin film transistor 340 of this embodiment is located on the gate line 320, a portion corresponding to the gate line 320, the thin film transistor 340 the gate electrode 340 of the thin film transistor, and the thin film transistor 340 also includes insulating layer 322, semiconductor layer 348, source electrode 344 drain 346 and the protective layer 352. 源极344与漏极346 分别设置于半导体层348的二端。 The source 344 and drain 346 are respectively disposed at two ends of the semiconductor layer 348. 再者,本发明的实施例,较佳地,设置掺杂半导体层332、 334于半导体层348上,且分别接触源极344与漏极346,以降低电阻值。 Furthermore, embodiments of the present invention, preferably, provided a doped semiconductor layer 332, 334 on the semiconductor layer 348, and respectively contact the source 344 and drain 346, to reduce the resistance value. 部分保护层352上设置像素电极360,且像素电极360经由通孔349耦接漏极346,并对应于设置在绝缘层314的公共线370,以形成于储存电容372。 Part of the protective layer 352 is provided on the pixel electrode 360, and the pixel electrode 360 ​​via a through hole 349 is coupled to the drain electrode 346, and the insulating layer disposed corresponding to the common line 314 370 to form the storage capacitor 372.

此外,像素结构300尚包含第二基板390,其相对于第一基板310而设置, 且设有公共电极388。 Further, the pixel structure 300 includes a second substrate 390 yet, with respect to the first substrate 310 is provided, and the common electrode 388 is provided. 公共电极388与第一基板310的像素电极360之间设置有具介电系数的层362,其中,具介电系数的层362为一液晶层、 一发光层(如: 有机材料、无机材料、或上述的组合)或上述的组合,以显示对应的灰阶亮度。 A common electrode 388 and the pixel electrode 310 between the first substrate 360 ​​with a layer 362 having a dielectric constant, wherein the layer having a dielectric constant of a liquid crystal layer 362, a light-emitting layer (such as: an organic material, an inorganic material, or) combination of the foregoing or a combination thereof, in order to display the corresponding gray level. 由于阵列于滤色片上型式的像素结构可运用本发明,而使得薄膜晶体管340 位于栅极线320,因此可提升阵列于滤色片上型式的像素结构的显示区域,以提升显示效能。 Since the color filter array pattern of the pixel structure of the present invention can use, so that the thin film transistor 340 and the gate line 320, and thus can improve the display region of the pixel array in the configuration of the color filter type, to improve display performance.

图3A的的像素结构300的另一实施例为有机发光型式的像素结构,其剖视图如图7所示,此种型式的像素结构不需设有通孔349而与像素电极360 耦接薄膜晶体管340的漏极346。 The pixel structure 300 of FIG. 3A according to another embodiment of the pixel structure of the organic light-emitting type, which is a cross-sectional view shown in Figure 7, the pixel structure of this type of a through-hole 349 need not be coupled with the thin film transistor connected to the pixel electrode 360 the drain of 346,340. 如图所示,此实施例的像素结构300包含有第一基板310、栅极线320、数据线(图未示)、薄膜晶体管340与像素电极360,以及具介电系数的层362,而此实施例的具介电系数的层362为有机发光层。 As shown, the pixel structure 300 of this embodiment includes a first substrate 310, gate lines 320, data lines (not shown), a thin film transistor 360, and the dielectric constant layer 362 and the pixel electrode 340, and layer has a dielectric constant according to this embodiment of the organic light emitting layer 362. 栅极线320与数据线实质上相互交错,而此实施例的薄膜晶体管340 位于栅极线320上,其中与薄膜晶体管340相对的部分栅极线即为薄膜晶体管340的栅极,薄膜晶体管340也包含绝缘层322、半导体层348、源极344、漏极346与保护层352。 The gate line 320 and data line are substantially interleaved, and this embodiment of the thin film transistor 340 is located on the gate line 320, the thin film transistor 340 in which the relative portions of the gate line is the gate of the thin film transistor, the thin film transistor 340 of 340 also includes an insulating layer 322, a semiconductor layer 348, source electrode 344, drain electrode 346 and the protective layer 352. 绝缘层322设置于部分第一基板310与栅极线320上, 半导体层348设置于部分绝缘层322上,且位于相对薄膜晶体管340的部分栅极线320的位置。 An insulating layer 322 disposed on a portion of the first substrate 310 and the gate line 320, a semiconductor layer 348 disposed on the upper portion of the insulating layer 322, and the thin film transistor located at a position opposing portion of the gate line 340 320. 源极344与漏极346分别设置于半导体层348的二端。 The source 344 and drain 346 are respectively disposed at two ends of the semiconductor layer 348. 再者, Furthermore,

本实施例,较佳地,半导体层348上设置掺杂半导体层332、 334,其分别接触源极344与漏极346,以降低电阻值。 The present embodiment, preferably, provided a doped semiconductor layer 332, 334 on the semiconductor layer 348, 344 respectively contacting the source electrode and the drain electrode 346, to reduce the resistance value. 其中源极344耦接数据线。 Wherein the source is coupled to data line 344. 像素电极360设置于部分绝缘层322上,且耦接漏极346。 The pixel electrode 360 ​​is disposed on the portion of the insulating layer 322, and coupled to the drain 346. 在本发明的实施例中,是以漏极346与像素电极360的交界处实质上呈现水平为实施范例,但不限于此, 也可选择性为部分像素电极360于漏极346之上或之下。 In an embodiment of the present invention, based on the pixel electrode 346 and the drain junction 360 is substantially level presented embodiment examples, but is not limited thereto, optionally also as a part of the pixel electrode 346 or the drain 360 of the above under.

承接上述,部分像素电极360上设置具介电系数的层362,而具介电系数的层362上设置一电极366。 Continuation of the above, is provided having a dielectric constant layer 362 on the part of the pixel electrode 360, an electrode 366 is provided over the layer 362 of dielectric constant. 而源极344、漏极346、部分半导体层348与电极366上设置保护层352。 And the source electrode 344, drain electrode 346, a portion of the semiconductor layer 348 and the upper electrode 366 protective layer 352. 本发明是让像素结构300增加显示区域的面积,因而提升有机发光型式的像素结构的显示效能。 The present invention is to increase the area of ​​the pixel structure of the display region 300, and thus enhance the effectiveness of the display pixel structure of the organic light emitting type.

请参阅图8,其为本发明的另一实施例的像素结构的俯视示意图。 Referring to FIG. 8, a schematic top view of a pixel structure according to another embodiment of the present invention thereof. 如图所示,本发明的像素结构400包含第一基板410 (如图9所示)、栅极线420、 数据线430、薄膜晶体管440、像素电极460与储存电容472,而栅极线420、 数据线430、薄膜晶体管440、像素电极460以及储存电容472设置于第一基板410上,其中,栅极线420与数据线430实质上相互交错。 As shown, the pixel structure 400 of the present invention comprises a first substrate 410 (FIG. 9), a gate line 420, data line 430, the thin film transistor 440, the pixel electrode 460 and storage capacitor 472, and the gate line 420 , the data line 430, the thin film transistor 440, the pixel electrode 460 and storage capacitor 472 is provided on the first substrate 410, wherein the gate line 420 and data line 430 cross each other substantially. 此实施例的薄膜晶体管440位于栅极线420上,且薄膜晶体管440耦接于栅极线420、数据线430与像素电极460,而薄膜晶体管440与储存电容472电性相接。 The thin film transistor 440 of this embodiment the gate line 420, and the thin film transistor 440 is coupled to the gate line 420, data line 430 and the pixel electrode 460, the thin film transistor 440 and the capacitor 472 is electrically in contact with the reservoir. 像素结构400更包含一通孔454,其位于栅极线420上,且通孔454的位置对应于薄膜晶体管440,而栅极线420延伸一延伸部424至通孔454,以作为薄膜晶体管440的栅极。 The pixel structure 400 further comprises a through hole 454, which is located on the gate line 420, and the position of the through holes 454 corresponding to the thin film transistor 440, and a gate line extending portion 420 extends through hole 424 to 454, 440 to a thin film transistor gate. 薄膜晶体管440的半导体层448相对于薄膜晶体管440的栅极, 薄膜晶体管440的源极444与漏极446位于半导体层448上,且皆位于栅极线420上,其中源极444耦接于数据线430。 The thin film transistor of the semiconductor layer 448 with the source 440 of transistor 440 to the gate of the thin film, the thin film transistor 440 and the drain electrode 444 positioned on the layer 446 of the semiconductor 448, and 420 are located on the gate line, a source electrode 444 which is coupled to the data line 430. 像素电极460经由对应于漏极446 的通孔449耦接于漏极446,且部分像素电极460相对于设置在第一基板410 的公共线470以形成储存电容472。 Corresponding to the pixel electrode 460 via the through hole 449 of the drain 446 is coupled to the drain 446, and a portion of the pixel electrode 460 is disposed with respect to the common line 470 of the first substrate 410 to form a storage capacitor 472.

此外,本发明的像素结构400的另一实施例,不需设置公共线470于第一基板410上,而延伸像素电极460至下一级栅极线420的部分区域,以在下一级栅极线420形成储存电容。 In addition, another pixel structure 400 of the present embodiment of the invention, without providing the common line 470 on the first substrate 410, the pixel electrode extends to the lower portion of region 460 a gate line 420, a gate to the next the storage capacitance line 420 is formed. 此外,为了检测像素结构400的缺陷,因此第一基板410上更设置至少一虚设图案412,以检测像素结构400的缺陷(如:残留物与像素结构400内任一层导体层及/或半导体层接触所产生的短路等), 其位于像素结构400的四个角落,此仅为本发明的一实施例并不局限虚设图案412所设置的位置,也可选择性地设置于像素结构400中的任一位置,例如: Further, in order to detect defective pixel structure 400, thus further providing at least one dummy pattern 412 on the first substrate 410 to detect defective pixel structure 400 (e.g.,: residue 400 within the pixel structure according to any one conductive layer and / or a semiconductor short circuit generated by the contact layer), which is located at the four corners of the pixel structure 400, this is merely an embodiment of the present invention is not limited to the position of the dummy pattern 412 is provided, also optionally be provided in the pixel structure 400 in any position, for example:

环绕该显示区域、设置于易发生残留物之处、平行栅极线420、数据线430、 公共线470的其中至少一者设置、或其它设置方式。 Around the display region, provided at the prone residues, parallel to the gate line 420, data line 430, wherein the common line 470 is disposed at least one, or other arrangement. 本发明实施例的虚设图案412是以曝露出第一基板410的通孔为例,但不限于此,也可选择性地为沟槽、 狭缝、或上述的混合使用。 Example dummy pattern 412 of the present invention is to expose the through hole of the first substrate 410 as an example, but is not limited thereto, and also optionally for the grooves, slits, or the above mixture. 当然,若像素结构400不需要检测,则虚设图案412也可不设置。 Of course, no need to detect if the pixel structure 400, the dummy pattern 412 may not be provided. 又,本发明的像素结构400更包含至少一遮光层(图未示), 其设置于第一基板410上,并与数据线430与栅极线420的至少一者平行,但不限于此,也可不包含遮光层。 Further, the pixel structure 400 of the present invention further comprises at least a light-shielding layer (not shown), which is disposed on the first substrate 410, and is parallel to at least one of the data lines 430 and the gate line 420, but is not limited thereto, also not include a light shielding layer.

请参阅图9,其为图8的一实施例的剖视图。 Please refer to FIG. 9, a sectional view of one embodiment thereof embodiment of FIG. 8. 图9的剖视方向为图8的BB'方向。 Direction sectional view of FIG. 9 is a BB 'direction in FIG. 8. 如图所示,本发明的像素结构400的栅极线420与公共线470设置于第一基板410上,其中栅极线420上设置通孔454,且通孔454对应于薄膜晶体管440,对应于薄膜晶体管440的部分栅极线420所延伸的延伸部424会经由通孔454延伸至薄膜晶体管440下而作为薄膜晶体管440的栅极。 As shown, the pixel structure of the present invention, a gate line 400 common line 470 and 420 disposed on the first substrate 410, wherein the through-hole 454 is provided on the gate line 420, and the through holes 454 corresponding to the thin film transistor 440, corresponding to the portion 440 of the thin film transistor gate line 420 extending through the extension portion 424 extends through hole 454 to the thin film transistor 440 and the gate electrode 440 of thin film transistor. 本实施例,较佳地,部分栅极线420的延伸部424是以从通孔454的一边延伸但不连接于此通孔454的另一边的栅极线420为例,也就是说延伸部424为部分栅极线420延伸至通孔454中但未贯穿通孔454,但也可以连接至通孔454的另-边,也就是说部分栅极线420也可延伸至通孔454中且贯穿通孔454。 Example extension portion, preferably, the portion of the gate line 420 of the present embodiment is 424 while extending from the through hole 454 but is not connected thereto on the other side of the through hole 454 of the gate line 420 as an example, that the extending portion 424 is a portion of the gate line 420 extends into but not through the through hole 454 through hole 454, but may be connected to the through hole 454 of the other - the edge, that is part of the gate line 420 may extend to the through holes 454 and through the through-hole 454. 薄膜晶体管440包含绝缘层422、半导体层448、源极444、漏极446与保护层452。 The thin film transistor 440 includes an insulating layer 422, a semiconductor layer 448, source electrode 444, drain electrode 446 and the protective layer 452. 绝缘层422设置于栅极线420上,部分第一基板410与/或公共线470上。 Insulating layer 422 disposed on the gate line 420, the upper portion of the first substrate 410 and / or the common line 470. 半导体层448设置于对应薄膜晶体管440的部分绝缘层422上。 The semiconductor layer 448 is disposed on the portion corresponding to the thin film transistor 440 of the insulating layer 422. 源极444与漏极446分别设置半导体层448的二端。 The source 444 and drain 446 are respectively provided in the two ends of the semiconductor layer 448. 再者,本发明的实施例,较佳地,半导体层448上设置掺杂半导体层432、 434,而分别接触源极444与漏极446,以降低电阻值。 Furthermore, embodiments of the present invention, preferably, the semiconductor layer 448 is provided on the doped semiconductor layer 432, 434, 444 respectively contacting the source electrode and the drain electrode 446, to reduce the resistance value. 源极444耦接数据线430 (如图8所示)。 The source 444 is coupled to data line 430 (FIG. 8). 保护层452设置于源极444、漏极446与部分半导体层448上,保护层452也设置于部分第一基板410 与公共线470两者所相对的部分绝缘层422上。 The protective layer 452 disposed on the source electrode 444, drain electrode 446 and the upper portion of the semiconductor layer 448, the protective layer 452 is also provided on a portion of the first substrate 410 and both the portion of the insulating layer 470 opposite to the common line 422. 另外,像素电极460设置于部分保护层452,且经通孔449耦接漏极446,而部分像素电极460相对于公共线470而形成储存电容472。 Further, the pixel electrode 460 is provided on the portion of the protective layer 452, and through the through hole 449 is coupled to the drain 446, while the portion of the pixel electrode 460 with the storage capacitor 472 to the common line 470 is formed.

此外,像素结构400更包含第二基板490,其相对于第一基板410,而部分第二基板490设置有黑色矩阵480、滤色片层484与公共电极488。 Further, the pixel structure 400 further comprises a second substrate 490 with respect to the first substrate 410, and the portion of the second substrate 490 is provided with a black matrix 480, the color filter layer 484 and the common electrode 488. 其中黑色矩阵480设置于部分第二基板490,且对应于栅极线420与薄膜晶体管440, 且滤色片层484设置于对应像素电极460的第二基板490上。 Wherein the black matrix 480 disposed on the second substrate portion 490, and corresponds to the gate line 420 and the thin film transistor 440, and the color filter layer 484 disposed on the second substrate 490 corresponding to the pixel electrode 460. 公共电极488 The common electrode 488

设置于滤色片层484上且耦接一共同电压,其与数据线430传送节像素电极460的数据信号产生压差变化,因而驱使像素电极460与公共电极488所接触的一具介电系数的层462依据电压差变化显示对应的灰阶亮度。 Disposed on the color filter layer 484 and is coupled to a common voltage, the data line 430 with the pixel electrode data signal transmission section 460 generates pressure changes, thereby driving the pixel electrode 460 by a dielectric constant contact with the common electrode 488 462 according to the voltage difference change layer corresponding to the display gray level. 其巾,具介电系数的层462为一液晶层、 一发光层(如:有机材料、无机材料、或上述的组合)或上述的组合,以显示对应的灰阶亮度。 Towel which, having dielectric constant layer 462 is a liquid crystal layer, a light-emitting layer (such as: an organic material, an inorganic material, or combinations thereof) or combinations thereof, in order to display the corresponding gray level. 换句话说,具介电系数的层462 是设置于第一基板410及第二基板490之间。 In other words, with a dielectric constant layer 462 is disposed on the substrate 410 between the first 490 and the second substrate. 此外,为了能够降低滤色片层484的剥落的现象产生,在本实施例中,较佳地,包含一缓冲层481设置于黑色矩阵480与第二基板490上,但不限于此,也可不形成缓冲层481或形成亍滤色片层484之下及/或部分黑色矩阵480上。 Further, in order to reduce the phenomenon of peeling of the color filter layer 484 is produced, in the present embodiment, preferably, comprises a buffer layer 481 disposed on the black matrix 480 and the second substrate 490, but is not limited thereto, but also may forming a buffer layer 481 is formed below the right foot or the color filter layer 484 and / or 480 on the black matrix portion. 当然,若为了解决滤色片层484 的落差问题,在本实施例中,较佳地,包含一平坦层486设置于黑色矩阵480 与滤色片层484上,但不限于此,也可不设置平坦层486。 Of course, if the gap in order to solve the problem of the color filter layer 484, in this embodiment, preferably, comprises a planar layer 486 disposed on the black matrix 480 and the color filter layer 484, but is not limited thereto, and may not be provided planarization layer 486. 又,像素结构400 的通孔454供栅极线420的延伸部424延伸而作为薄膜晶体管440的栅极的设计,也可运用于如图5与图6所示的像素结构型式,而应用于滤色片于阵列上型式的像素结构或阵列于滤色片上型式的像素结构。 Further, the pixel structure 400 of the through hole 454 for a gate line extending portion 424 extends as a gate electrode 420 of the thin film transistor 440 design may also be applied to the pixel structure of the type shown in FIG. 5 and FIG. 6, and applied structure or the color filter array pixel array pattern in the pixel structure of the color filter pattern.

请参阅图IOA,其为本发明的另一实施例的像素结构的俯视示意图。 Referring to FIG IOA, schematic top view of a pixel structure according to another embodiment of the present invention thereof. 如图所示,本发明的像素结构500类似于图3A的像素结构300,且二者呈对称设置。 As shown, the pixel structure of the invention similar to the pixel structure 500 300 3A, and two symmetrically disposed. 像素结构500也是包含第一基板510 (如图ll所示)、栅极线520、数据线530、薄膜晶体管540与像素电极560,其中栅极线520与数据线530设置于第一基板510上,栅极线520与数据线530实质上相互交错。 The pixel structure 500 also includes a first substrate 510 (shown in FIG LL), a gate line 520, data line 530, the thin film transistor 540 and the pixel electrode 560, wherein the gate line 520 and data line 530 is disposed on the first substrate 510 the gate line 520 and data line 530 cross each other substantially. 此实施例的薄膜晶体管540位于栅极线520上,其中薄膜晶体管540的所相对的栅极线520 相反于图3A的薄膜晶体管540所相对的栅极线520,也就是说,此实施例的薄膜晶体管540所设置的位置相反于图3A的薄膜晶体管540所设置的位置。 The thin film transistor 540 of this embodiment is positioned on the gate line 520, wherein the thin film transistor 540 opposite the gate line 520 opposite to the thin film transistor 540 of FIG. 3A opposite to the gate line 520, that is to say, this embodiment the position of the thin film transistor 540 is disposed opposite to the thin film transistor 540 of FIG. 3A set position. 此实施例同样以相对于薄膜晶体管540的部分栅极线520作为薄膜晶体管540 的栅极,薄膜晶体管540的半导体层548位于栅极线520上,且对应于薄膜晶体管540的栅极。 In this embodiment, the same part with respect to the thin film transistor 540 of the gate line 520 as the gate of the thin film transistor 540, a gate located on the gate line 520, and the thin film transistor 540 corresponds to the semiconductor layer of the thin film transistor 540 of 548. 薄膜晶体管540的源极544与漏极546位于半导体层548 上,且源极544与漏极546也位于栅极线520上,其中源极544耦接于数据线530。 Source electrode 544 of the thin film transistor 540 and the drain 546 is located on the semiconductor layer 548, and the source 544 and drain 546 are also positioned on the gate line 520, a source 544 which is coupled to data line 530. 像素电极560经由通孔549耦接于漏极546,其中像素电极560耦接漏极546的位置上下相反于图3A的像素电极560。 The pixel electrode 560 through a via 549 coupled to the drain 546, where the pixel electrode 560 is coupled to the pixel electrode 560 opposite to the vertical position of the drain 546 in FIG. 3A.

此外,像素电极560也相对于设置于第一基板510的公共线570,以形成储存电容572。 Further, the pixel electrode 560 is also provided with respect to a common line 570 of the first substrate 510 to form a storage capacitor 572. 此外,为了检测像素结构500的缺陷,因此第-基板510上更设置至少一虚设图案(dummy pattern) 512,以检测像素结构500的缺陷(如: 残留物与像素结构500内任一层导体层及/或半导体层接触所产生的短路等), 于此实施例中第一基板510上设置多个虚设图案512,其位于像素结构500的四个角落,此仅为本发明的一实施例并不局限虚设图案512所设置的位置,也可选择性地设置于像素结构500中的任一位置,例如:环绕该显示区域、设置于易发生残留物之处、平行栅极线520、数据线530、公共线570的其中至少一者设置、或其它设置方式。 Further, in order to detect defective pixel structure 500, so the first - at least a further disposed dummy pattern (dummy pattern) 512 on the substrate 510 to detect defective pixel structure 500 (e.g.,: residue 500 within the pixel structure of a conductor layer according to any one and / or short circuit in contact with the semiconductor layer generated and the like), this embodiment is provided on the first substrate a plurality of dummy patterns 510 512, which is located in the four corners of the pixel structure 500, this is merely an embodiment of the present invention and not limited to any one position of the dummy pattern 512 disposed position, also optionally be provided in the pixel structure 500, for example: around the display region, provided at the prone residues, parallel to the gate line 520, data line 530, common line 570 is provided wherein at least one, or other arrangement. 本发明实施例的虚设图案512是以曝露出第一基板510的通孔为例,但不限于此,也可选择性地为沟槽、狭缝、或上述的混合使用。 Example dummy pattern 512 of the embodiment of the present invention is to expose the through hole of the first substrate 510 as an example, but is not limited thereto, and also optionally for the grooves, slits, or the above mixture. 当然,若像素结构不需要检测,则虚设图案也可不设置。 Of course, no need to detect if the pixel structure, the dummy pattern may not be provided. 又,本发明的像素结构500更包含至少一遮光层(图未示),其设置于第一基板510上,并与数据线530与栅极线520的至少一者平行,但不限于此,也nj不包含遮光层。 Further, the pixel structure 500 of the present invention further comprises at least one parallel to the at least one light-shielding layer (not shown), which is disposed on the first substrate 510, and the data line 530 and the gate line 520, but is not limited thereto, nj also does not include the light shielding layer. 另外,本发明的像素结构500的另一实施例,第一基板510上可不需设置公共线570,而直接延伸像素电极560至覆盖上一栅极线520的部分区域,以形成储存电容于上一栅极线520的部分区域。 Further, the pixel structure of the present invention, another embodiment 500, the common line 570 may be provided without the first substrate 510, the pixel electrode 560 extends directly to the covering portion 520 on a gate line area to form a storage capacitor on 520 is a partial region of the gate line.

另外,如图10B所示,像素结构500的黑色矩阵580相对于像素电极560 的周围而位于第一基板510或者相对于第一基板510的第二基板5卯(如图11 所示),以覆盖部分该栅极线520、部分该数据线530、该薄膜晶体管540。 Further, as shown in FIG. 10B, the pixel structure of the black matrix around 580,500 with respect to the pixel electrode 560 and the first substrate or the second substrate 510 with respect to the sockets 5 of the first substrate 510 (FIG. 11) to partially covers the gate line 520, the portion of the data line 530, the thin film transistor 540. 由于黑色矩阵580与公共线570会阻隔光线通过,所以未受黑色矩阵580与公共线570阻隔而相对像素电极560的区域即为显示区域582。 Since the black matrix 580 and the common line 570 will block light to pass through it unaffected region of the black matrix 580 and the common line 570 and the barrier 560 is the opposing electrode of the display pixel region 582.

请参阅图11,其为图10A的一实施例的剖视图。 Please refer to FIG. 11, a cross-sectional view of the embodiment of FIG. 10A which is a. 图11的剖视方向为图10A的CC'方向。 Direction cross-sectional view of FIG. 10A FIG. 11 is a CC 'direction. 如图所示,本发明的像素结构500的栅极线520与公共线570设置于第一基板510上,此实施例的薄膜晶体管540位于栅极线520上。 As shown, the pixel structure of the present invention, the gate lines 520 and 570 of the common line 500 provided on the first substrate 510, a thin film transistor 540 of this embodiment is positioned on the gate line 520. 薄膜晶体管540包含绝缘层522、半导体层548与保护层552。 The thin film transistor 540 includes an insulating layer 522, the semiconductor layer 548 and the protective layer 552. 对应于薄膜晶体管540的部分栅极线520以作为薄膜晶体管540的栅极。 The thin film transistor 540 corresponds to a portion of the gate line 520 as a gate electrode 540 of the thin film transistor. 绝缘层522设置于部分第一基板510、栅极线520与/或公共线570上。 Insulating layer 522 is provided on a portion of the first substrate 510, a gate line 520 and / or the common line 570. 对应于薄膜晶体管540 的部分绝缘层522上设置半导体层548。 The thin film transistor 540 corresponds to the portion of the insulating layer 522 is provided on the semiconductor layer 548. 源极544与漏极546设置于半导体层548的二端。 The source 544 and drain 546 disposed at the two ends of the semiconductor layer 548. 再者,本发明的实施例,较佳地,设置掺杂半导体层532、 534 于半导体层548上,而分别接触源极544与漏极546,以降低电阻值。 Furthermore, embodiments of the present invention, preferably, provided the doped semiconductor layer 532, 534 on the semiconductor layer 548, 544 respectively contacting the source electrode and the drain electrode 546, to reduce the resistance value. 源极544、 漏极546与位于源极544和漏极546之间的半导体层548上设置一保护层552, 保护层552也设置于相对部分第一基板510与公共线570的绝缘层522上。 The source 544, drain 546 is provided with a protective layer positioned on the semiconductor layer 548 between the source electrode 544 and the drain electrode 546 552, protective layer 552 is also disposed on opposing portions of the first substrate 510 and the common line 570 an insulating layer 522 . 承接上述,像素电极560设置于第一基板510上,而位于部分保护层552, 且像素电极560经通孔549耦接漏极546,且部分像素电极560对应于公共线570以形成储存电容572。 Continuation of the above, the pixel electrode 560 disposed on the first substrate 510, a protective layer 552 located part, and the pixel electrode 560 through the through hole 549 is coupled to the drain electrode 546, and a portion of the pixel electrode 560 corresponds to a common line 570 to form the storage capacitor 572 . 另外,像素结构500更设置第二基板590,其相对于第一基板510,第二基板590具有黑色矩阵580、 一滤色片层584与公共电极588。 Further, the pixel structure 500 further provided a second substrate 590 with respect to the first substrate 510, second substrate 590 having a black matrix 580, a color filter layer 584 and the common electrode 588. 其中黑色矩阵580设置于部分第二基板590,且对应于栅极线520与薄膜晶体管540,且滤色片层584设置于对应像素电极560的第二基板590上。 Wherein the black matrix 580 disposed on the second substrate portion 590, and corresponds to the gate line 520 and the thin film transistor 540, and the color filter layer 584 disposed on the second substrate 590 corresponding to the pixel electrode 560. 公共电极588设置于滤色片层584上且耦接一共同电压,其与数据线(图未示) 传送至像素电极560的数据信号产生压差变化,因而驱使像素电极560与公共电极588所接触的一具介电系数的层562依据电压差变化显示对应的灰阶亮度。 The common electrode 588 disposed on the color filter layer 584 and is coupled to a common voltage which the data line (not shown) transmits a data signal to the pixel electrode 560 generated pressure changes, thereby driving the pixel electrode 560 and the common electrode 588 a dielectric layer 562 contacting coefficient corresponding to the brightness gradation display according to the voltage difference change. 其中,具介电系数的层562为一液晶层、 一发光层(如:有机材料、无机材料、或上述的组合)或上述的组合,以显示对应的灰阶亮度。 Wherein the layer has a dielectric constant of a liquid crystal layer 562, a light-emitting layer (such as: an organic material, an inorganic material, or combinations thereof) or combinations thereof, in order to display the corresponding gray level. 换句话说,具介电系数的层562是设置于第一基板510及第二基板590之间。 In other words, with a dielectric constant layer 562 is disposed between the first substrate 510 and the second substrate 590. 此外,为了能够降低滤色片层584的剥落的现象产生,在本实施例中,较佳地,包含一缓冲层581设置于黑色矩阵580与第二基板上590,但不限于此,也可不形成缓冲层581或形成于滤色片层584之下及/或部分黑色矩阵580上。 Further, in order to reduce the phenomenon of peeling of the color filter layer 584 is produced, in the present embodiment, preferably, comprises a buffer layer 581 disposed on the black matrix 580 and the second substrate 590, but is not limited thereto, but also may forming a buffer layer 581 or layer 584 is formed under the color filter / or 580 and the black matrix portion. 当然,若为了解决滤色片层584的落差问题,在本实施例中,较佳地,包含一平坦层586 设置于黑色矩阵580与滤色片层584上,但不限于此,也可不设置平坦层586。 Of course, if the gap in order to solve the problem of the color filter layer 584, in this embodiment, preferably, comprises a planar layer 586 disposed on the black matrix 580 and the color filter layer 584, but is not limited thereto, and may not be provided planarization layer 586. 除此之外,图10A的像素结构500可为滤色片于阵列上型式或阵列于滤色片上型式的像素结构,其如图5与图6所示的像素结构型式。 In addition, the pixel structure 500 of FIG. 10A may be a color filter array pattern or array on a pixel pattern on the color filter structure, in which the pixel structure type shown in FIG. 5 and FIG 6.

请参阅图12A,其为本发明的另一实施例的像素结构的俯视示意图。 Please refer to Figure 12A, a schematic top view of a pixel structure according to another embodiment of the present invention thereof. 如图所示,本发明的像素结构600包含第一基板610 (如图13所示)、栅极线620、 数据线630、薄膜晶体管640与像素电极660。 As shown, the pixel structure 600 of the present invention comprises a first substrate 610 (FIG. 13), the gate line 620, data line 630, the thin film transistor 640 and the pixel electrode 660. 栅极线620与数据线630实质上相互交错,此实施例的薄膜晶体管640为一蚀刻终止型薄膜晶体管,且位于栅极线620上,部分栅极线620对应于薄膜晶体管640而作为薄膜晶体管640 的栅极。 The gate line 620 and data line 630 cross each other substantially, the thin film transistor 640 of this embodiment is an etching stop type thin film transistor, and is located on the gate line 620, gate line 620 corresponds to a portion of the thin film transistor 640 and a thin film transistor gate 640. 蚀刻终止型的薄膜晶体管640具有一蚀刻终止层650,其设置于薄膜晶体管640的半导体层648 (如图13所示)上,且对应于薄膜晶体管640的栅极,薄膜晶体管640的源极644与漏极646分别位于蚀刻终止层650两侧, 其中,源极644耦接数据线630,像素电极660经通孔649耦接漏极646,且像素电极660延伸至另一栅极线620而形成储存电容662。 Etch stop thin film transistor 640 having an etch stop layer 650, which is disposed on the semiconductor layer 640 of the thin film transistor 648 (FIG. 13) on, and corresponds to a gate, a source of the thin film transistor 640 thin-film electrode 644 of the transistor 640 and the drain 646 are respectively located on both sides of the etch stop layer 650, wherein source 644 is coupled to data line 630, the pixel electrode 660 via the through-hole 649 is coupled to the drain electrode 646, and the pixel electrode 660 extends to the gate line 620 and the other storage capacitor 662 is formed. 因此,本实施例的蚀刻终止层650,其设置于薄膜晶体管640的半导体层648 (如图13所示)上, Accordingly, the present embodiment the etch stop layer 650, a thin film transistor provided in the semiconductor layer 648 640 (13), the

且蚀刻终止层650 二端分别具有源极644及漏极646。 Etch stop layer 650 and the second end 644 each having a source and a drain 646. 再者,本发明的实施例, 较佳地,设置掺杂半导体层632、 634于源极644、漏极646与半导体层648 接触之处,以降低电阻值。 Furthermore, embodiments of the present invention, preferably, provided the doped semiconductor layer 632, 634 to the source 644, drain 646 of the contact 648 and the semiconductor layer to reduce the resistance.

另外,如图12B所示,相对于像素电极660的周围设置有黑色矩阵670, 其位于第一基板610或者相对于第一基板610的第二基板680(如图13所示), 以覆盖部分该栅极线620、部分该数据线630、该薄膜晶体管640。 Further, 12B, around the pixel electrode 660 with respect to the black matrix 670 is provided, which is located between the first substrate 610 or second substrate 680 with respect to the first substrate 610 (FIG. 13), to cover a portion the gate line 620, part of the data line 630, the thin film transistor 640. 由于黑色矩阵670会阻隔光线通过,所以未受黑色矩阵670阻隔而相对像素电极660 的区域即为显示区域672。 Since the black matrix 670 will block light to pass through it unaffected black matrix 670 opposing the pixel electrode 660 and the barrier region is the display region 672.

此外,本发明的像素结构600的另一实施例,是未将像素电极660延伸至下一栅极线620,而在第一基板610上更设置一公共线(图未示),而部分像素电极660对应公共线,以在像素电极660与公共线之间形成储存电容。 In addition, another pixel structure 600 of the present invention embodiment, the pixel electrode 660 is not extended to the next gate line 620, but rather provided a common line (not shown) on the first substrate 610, and a pixel portion It corresponds to the common electrode line 660 to form a storage capacitance between the pixel electrode 660 and the common line. 此外, 为了检测像素结构600的缺陷,因此第一基板610上更可设S至少一虚设图案(dummy pattern,图未示),以检测像素结构600的缺陷(如:残留物与像素结构600内任一层导体层及/或半导体层接触所产生的短路等),艽中一实施方式,虚设图案可位于像素结构600的四个角落,此仅为本发明的一实施例并不局限虚设图案所设置的位置,也可选择性地设置于像素结构600中的任--位置,例如:环绕该显示区域、设置于易发生残留物之处、平行栅极线620、数据线630的其中至少一者设置、或其它设置方式。 Further, in order to detect defective pixel structure 600, 610 on the first substrate S may be provided at least one more dummy pattern (dummy pattern, not shown) to detect defective pixel structure 600 (e.g.,: residue 600 within the pixel structure according to any one conductive layer and / or short circuit of the semiconductor layer generated by the contact), straminea one embodiment, the dummy pattern may be located at the four corners of the pixel structure 600, this is merely an embodiment of the present invention is not limited to the dummy pattern the set position, also optionally be provided in any of the pixel structure 600 - position, for example: around the display region, is provided to the easy occurrence of the residue, the parallel gate lines 620, data line 630, wherein at least one set, or other arrangement. 本发明可用曝露出第一基板610的通孔以作为虚设图案为例,但不限于此,也可选择性地为沟槽、狭缝、 或上述的混合使用。 The present invention may expose substrate 610 through holes in the first dummy pattern as an example, but is not limited thereto, and also optionally for the grooves, slits, or the above mixture. 当然,若像素结构600不需要检测,则虚设图案也可不设置。 Of course, no need to detect if the pixel structure 600, the dummy pattern may not be provided. 又,本发明的像素结构600更包含至少一遮光层(图未示),其设置于第一基板610上,并与数据线630与栅极线620的至少一者平行,但不限于此, 也可不包含遮光层。 Further, the pixel structure 600 of the present invention further comprises at least a light-shielding layer (not shown), which is disposed on the first substrate 610, the data line 630 and gate line 620 parallel to at least one of, but is not limited thereto, also not include a light shielding layer.

请参阅图13,其为图12A的一实施例的剖视图。 Refer to FIG. 13, which is a cross-sectional view of the embodiment of FIG. 12A is a. 图13的剖视方向为图12A的DD'方向。 FIG 13 is a sectional view of FIG direction DD 'direction 12A. 如图所示,本发明的像素结构600的栅极线620设置于第一基板610上,此实施例的薄膜晶体管640为蚀刻终止型薄膜晶体管,且位于栅极线620上,其中相对于薄膜晶体管640的部分栅极线620用于作为薄膜晶休管640的栅极。 As shown, the pixel structure 600 of the present invention, a gate line 620 disposed on the first substrate 610, a thin film transistor 640 of this embodiment is the etch-stop type thin film transistor, and is located on the gate line 620, wherein the thin film with respect to portion of the gate line 620 is used as the transistor 640 gate of the thin film transistor 640 off. 绝缘层622位于部分第一基板610与栅极线620上,半导体层648设置于对应薄膜晶体管640的部分绝缘层622上。 An insulating layer 622 positioned on the portion of the first substrate 610 and the gate line 620, a semiconductor layer 648 disposed on the insulating layer 622 corresponding to the portion 640 of the thin film transistor. 源极644与漏极646, 分别设置于蚀刻终止层650及半导体层648上。 The source 644 and drain 646, respectively disposed on the etch stop layer 650 and the semiconductor layer 648. 再者,本发明的实施例,较佳 Furthermore, embodiments of the present invention, the preferred

地,半导体层648上设置有掺杂半导体层632、 634,而分别接触源极644与漏极646,以降低电阻值。 Be provided with a doped semiconductor layer 632, 634 on the semiconductor layer 648, 644 respectively contacting the source electrode and the drain electrode 646, to reduce the resistance value. 因此,蚀刻终止层650设置于半导体层648上,且掺杂半导体层632及634、源极644及漏极646位于蚀刻终止层650的二端匕其中薄膜晶体管640的源极644耦接数据线630。 Thus, the etch stop layer 650 is provided on the semiconductor layer 648, and the doped semiconductor layer 632 and 634, a source electrode 644 and drain electrode 644 coupled to the data line 646 is located an etch stop layer 650 of the two ends of the thin film transistor wherein the source dagger 640 630. 保护层652设置于部分绝缘层622、源极644、漏极646与蚀刻终止层650上。 The protective layer 652 is provided on the portion of the insulating layer 622, source 644, drain 646 and the etching stop layer 650. 像素电极660设置于部分保护层652上,且经通孔649耦接薄膜晶体管640的漏极646,像素电极660 对应于下一栅极线620而形成储存电容662。 The pixel electrode 660 is provided on a portion of the protective layer 652, and the through hole is coupled to the drain of the thin film transistor 646 649 640, 660 corresponding to the next pixel electrode 620 and the gate line 662 form a storage capacitor.

另外,像素结构600尚包含第二基板680,其与第一基板610相对。 Further, the pixel structure 600 includes a second substrate 680 yet, which is opposed to the first substrate 610. 部分第二基板680设置黑色矩阵670、 一滤色片层674与公共电极678。 Portion of the second substrate 680 is provided a black matrix 670, a color filter layer 674 and the common electrode 678. 其中黑色矩阵670设置于部分第二基板680,且黑色矩阵670相对于部分栅极线620、 薄膜晶体管640及/或数据线(图未示)。 Wherein the black matrix 670 disposed on the second substrate portion 680, and 670 with respect to the black matrix 640 and / or the data line portion of the gate line 620, a thin film transistor (not shown). 滤色片层674设置于对应像素电极660的第二基板680上。 The color filter layer 674 disposed on the second substrate 680 corresponding to the pixel electrode 660. 公共电极678设置于滤色片层674上且耦接一共同电压,其与数据线630传送至像素电极660的数据信号产生压差变化,因而驱使像素电极660与公共电极678所接触的一具介电系数的层664依据电压差变化显示对应的灰阶亮度。 The common electrode 678 disposed on the color filter layer 674 and is coupled to a common voltage, which generates a pressure change in the data signal 630 is transmitted to the data lines of the pixel electrode 660, thereby driving a pixel electrode 660 and the common electrode 678 in contact with dielectric constant layer 664 corresponding to the brightness gradation display according to the voltage difference change. 其中,具介电系数的层664为一液晶层、 一发光层(如: 有机材料、无机材料、或上述的组合)或上述的组合,以显示对应的灰阶亮度。 Wherein the layer has a dielectric constant of a liquid crystal layer 664, a light-emitting layer (such as: an organic material, an inorganic material, or combinations thereof) or combinations thereof, in order to display the corresponding gray level. 换句话说,具介电系数的层664是设置于第一基板610及第二基板680之间。 In other words, with a dielectric constant layer 664 is disposed between the first substrate 610 and the second substrate 680. 此外,为了能够降低滤色片层674的剥落的现象产生,在本实施例中,较佳地, 包含一缓冲层671设置于黑色矩阵670与第二基板上680,但不限于此,也可不形成缓冲层671或形成于滤色片层674之下及/或部分黑色矩阵670」:。 Further, in order to reduce the phenomenon of peeling of the color filter layer 674 to generate, in the present embodiment, preferably, it comprises a buffer layer 671 disposed on the black matrix 670 and the second substrate 680, but is not limited thereto, but also may forming a buffer layer 671 or the color filter layer 674 is formed under and / or a portion of the black matrix 670 ':. 当然,若为了解决滤色片层674的落差问题,在本实施例中,较佳地,包含一平坦层676设置于黑色矩阵670与滤色片层674上,但不限于此,也可不设置平坦层676。 Of course, if the gap in order to solve the problem of the color filter layer 674, in this embodiment, preferably, comprises a planar layer 676 disposed on the black matrix 670 and the color filter layer 674, but is not limited thereto, and may not be provided planarization layer 676.

请参阅图14,其为图12A的另一实施例的剖视图。 Refer to FIG. 14, a cross-sectional view of another example of embodiment thereof in FIG. 12A. 图14的剖视方向同为图12A的DD,方向。 Cross-sectional view in FIG. 14 with FIG DD, the direction 12A. 如图所示,本发明也可适用于具蚀刻终止型薄膜晶体管的滤色片于阵列上(Color filter On Array, COA)型式的像素结构。 As shown, the present invention can be applied on the array (Color filter On Array, COA) type of pixel structure having the etch stop type thin film transistor of the color filter. 如图所示, 此实施例的像素结构600也包含第一基板610、栅极线620、薄膜晶体管640、 像素电极660与储存电容662,而栅极线620、薄膜晶体管640、像素电极660 与储存电容662设置于第一基板610上。 As shown, the pixel structure 600 of this embodiment also includes a first substrate 610, a gate line 620, the thin film transistor 640, the pixel electrode 660 and storage capacitor 662, the gate line 620, the thin film transistor 640, the pixel electrode 660 the storage capacitor 662 is provided on the first substrate 610. 相对于薄膜晶体管640的部分栅极线620即为薄膜晶体管640的栅极。 With respect to the gate portion of the gate line 620 is the thin film transistor 640 thin-film transistor 640. 此实施例的薄膜晶体管640同样包含绝缘层 The thin film transistor 640 of this embodiment also includes an insulating layer

622、半导体层648、蚀刻终止层650、源极644、漏极646与保护层652。 622, a semiconductor layer 648, an etch stop layer 650, a source electrode 644, drain electrode 646 and the protective layer 652.

承接上述,绝缘层622设置于栅极线620与部分第一基板610上,半导体层648设置于部分绝缘层622上且对应于薄膜晶体管640的栅极线620,蚀刻终止层650设置于半导体层648上,源极644与漏极646分别设置于蚀刻终止层650及半导体层648上。 Continuation of the above, the gate insulating layer 622 is provided on line 620 and the upper portion of the first substrate 610, a semiconductor layer 648 disposed on the upper portion of the insulating layer 622 corresponding to the gate line 620 and the thin film transistor 640, the etching stop layer 650 disposed on the semiconductor layer, on 648, the source electrode 644 and drain electrode 646 are disposed on the etching stop layer 650 and the semiconductor layer 648. 再者,本发明的实施例,较佳地,设置掺杂半导体层632、 634,以降低电阻值。 Furthermore, embodiments of the present invention, preferably, provided the doped semiconductor layer 632, 634, to reduce the resistance value. 所以,蚀刻终止层650设置于半导体层648上, 且蚀刻终止层650的二端上,设置有掺杂半导体层632及634、源极644与漏极646。 Therefore, the etch stop layer 650 is provided on the semiconductor layer 648, and the etch stop layer 650 on the titanium side is provided with a doped semiconductor layer 632 and 634, source 644 and drain 646. 保护层652设置于源极644、漏极646与蚀刻终止层650上,且保护层652也设置于部分绝缘层622上。 The protective layer 652 is provided to the source 644, drain 646 and the etching stop layer 650, and the protective layer 652 is also provided on the portion of the insulating layer 622. 像素电极660设置于部分保护层652上, 且经由通孔649耦接漏极646,此外像素电极660更相对于另一栅极线620的部分区域而形成储存电容662。 The pixel electrode 660 is provided on a portion of the protective layer 652, and the through-hole 649 is coupled via a drain 646, in addition with respect to the pixel electrode 660 more partial region of the gate line 620 to another storage capacitor 662 is formed. 另外,像素结构600更包含另一绝缘层666, 其设置于薄膜晶体管640与像素电极660上,黑色矩阵670设置于绝缘层666 上,其中黑色矩阵670的位置相对于薄膜晶体管640、栅极线620及/或数据线(未图标)。 Further, the pixel structure 600 further comprises another insulating layer 666, which is disposed on the thin film transistor 640 and the pixel electrode 660, the black matrix 670 is disposed on the insulating layer 666, wherein the black matrix 670 relative to the position of the thin film transistor 640, a gate line 620 and / or data lines (not shown). 滤色片层674位于绝缘层666上及部分黑色矩阵670上,但不限于此,也可不设置另一绝缘层666。 The color filter layer 674 is located on the insulating layer 666 and the upper portion of the black matrix 670, but is not limited thereto, and another insulating layer 666 may not be provided.

此外,为了能够降低滤色片层674的剥落现象产生,在本实施例中,较佳地,包含一缓冲层671设置于黑色矩阵670与第二基板上680,但不限于此, 也可不形成缓冲层671或形成于滤色片层674之下及/或部分黑色矩阵670上。 Further, in order to reduce peeling of the color filter layer 674 is produced, in the present embodiment, preferably, comprises a buffer layer 671 disposed on the black matrix 670 and the second substrate 680, but is not limited thereto, and may not be formed or the buffer layer 671 is formed under the color filter layer 674 / or 670 and the black matrix portion. 当然,若为了解决滤色片层674的落差问题,在本实施例中,较佳地,包含一平坦层676设置于黑色矩阵670与滤色片层674上,但不限于此,也可不设置平坦层676。 Of course, if the gap in order to solve the problem of the color filter layer 674, in this embodiment, preferably, comprises a planar layer 676 disposed on the black matrix 670 and the color filter layer 674, but is not limited thereto, and may not be provided planarization layer 676.

此外,像素结构600的第二基板680设有公共电极678,第二基板680相对于第一基板610,且二者之间设置有具介电系数的层664,其中,具介电系数的层664为一液晶层、 一发光层(如:有机材料、无机材料、或上述的组合) 或上述的组合,以显示对应的灰阶亮度。 Further, the pixel structure 680 of the second substrate 600 is provided with a common electrode 678, a second substrate 680 with respect to the first substrate 610, and is provided with a layer 664 having a dielectric constant therebetween, wherein the layer has a dielectric constant 664 is a liquid crystal layer, a light-emitting layer (such as: an organic material, an inorganic material, or combinations thereof) or combinations thereof, in order to display the corresponding gray level. 由于本发明可用于具蚀刻终止型薄膜晶体管的滤色片于阵列上型式的像素结构中,也就是滤色片于阵列上型式的像素结构600的薄膜晶体管640位于栅极线620上,因此本发明可增加具蚀刻终止型薄膜晶体管的滤色片于阵列上型式的像素结构的显示区域,以提升显示效能。 Since the present invention can be used to terminate the etch type thin film transistor having a color filter in the pixel array on the structure type, i.e. on the color filter array pixel structure type thin film transistor 640 of the gate 600 on line 620, thus the present invention can increase the etch stop filter having thin film transistor in the display area of ​​the pixel pattern on the array configuration to improve display performance.

请参阅图15,其为图12A的另一实施例的剖视图。 Please refer to FIG. 15, a cross-sectional view of another example of embodiment thereof in FIG. 12A. 图15的剖视方向同为图12A的DD,方向。 FIG 15 is a sectional view of the same direction as FIG DD, the direction 12A. 本发明也适用于具蚀刻终止型薄膜晶体管的阵列于滤色片上(Array On Color filter, AOC)型式的像素结构。 The present invention is also applicable to the color filter array pixel structure (Array On Color filter, AOC) with an etch stop type thin film transistor. 如图所示,此实施例的像素结构600也包含第--基板610,而黑色矩阵670与滤色片层674设置于第一基板610上,且滤色片层674与部分的黑色矩阵670上设有平坦层676,但不限于此,也可不设置平坦层676。 The pixel structure as shown, this embodiment also includes a first 600 - substrate 610, the black matrix 670 and the color filter layer 674 disposed on the first substrate 610 and the color filter layer 674 and the black matrix portion 670 It is provided on the planarization layer 676, but is not limited thereto, planarization layer 676 may not be provided. 另外,为了能够减少滤色片层674的剥落现象,本实施例中,较佳地,包含缓冲层671,其设置于部分第一基板610上及黑色矩阵670上,但不限于此,也可不形成缓冲层671或形成于滤色片层674之下及/或部分黑色矩阵670上。 Further, in order to reduce the peeling of the color filter layer 674, in this embodiment, preferably, comprising a buffer layer 671, which is disposed on the upper portion of the first substrate 610 and the black matrix 670, but is not limited thereto, but also may forming a buffer layer 671 or layer 674 is formed under the color filter / or 670 and the black matrix portion. 为了改善栅极线620与平坦层676的附着性,本实施例中,较佳地,平坦层676上更设置另一绝缘层612。 In order to improve the flatness of the gate line 620 and the adhesion layer 676, in this embodiment, preferably, another insulating layer 612 is provided more on the planarization layer 676. 此实施例的栅极线620、薄膜晶体管640、像素电极660与储存电容662设置于绝缘层612 上,而薄膜晶体管640与储存电容662电性相接,但不限于此,也可不设置另一绝缘层612。 The gate line 620 of this embodiment, the thin film transistor 640, the pixel electrode 660 and storage capacitor 662 is provided on the insulating layer 612, the thin film transistor 640 and the storage capacitor 662 is electrically in contact with, but is not limited thereto, and may not be further provided the insulating layer 612. 其中相对应于薄膜晶体管640的部分栅极线620即为薄膜品体管640的栅极,且此实施例的薄膜晶体管640同样包含绝缘层622、半导体层648、源极644、漏极646、蚀刻中止层650与保护层652。 Wherein the portion of the gate line corresponding to the thin film transistor 640 is the product of the transistor 620 gate 640, and a thin film transistor of this embodiment 640 also includes an insulating layer 622, semiconductor layer 648, source 644, drain 646, etch stop layer 650 and the protective layer 652.

承接上述,绝缘层622设置于栅极线620与部分第一基板610上,半导体层648设置于部分绝缘层622上,且对应于薄膜晶体管640的栅极线620,蚀刻终止层650设置于半导体层648上,源极644与漏极646分别设置于蚀刻终止层650及半导体层648上。 Continuation of the above, the gate insulating layer 622 is provided on line 620 and the upper portion of the first substrate 610, a semiconductor layer 648 disposed on the upper portion of the insulating layer 622, corresponding to the gate line 620 and the thin film transistor 640, the etching stop layer 650 is provided on a semiconductor layer 648, a source 644 and drain 646 are disposed on the etching stop layer 650 and the semiconductor layer 648. 再者,本发明的实施例,较佳地,设置有掺杂半导体层632、 634,以降低电阻值。 Furthermore, embodiments of the present invention, preferably, there is provided a doped semiconductor layer 632, 634, to reduce the resistance value. 所以,半导体层648上且蚀刻终止层650 的二端,设置有掺杂半导体层632及634、源极644与漏极646。 Therefore, on the semiconductor layer and the etch stop layer 650 second end 648 is provided with a doped semiconductor layer 632 and 634, source 644 and drain 646. 保护层652 设置于源极644、漏极646与蚀刻终止层650上,保护层652也设置于部分相对于第一基板610的绝缘层622上。 The protective layer 652 is provided to the source 644, drain 646 and the etch stop layer 650, protective layer 652 is provided over the insulating layer 622 with respect to the portion of the first substrate 610. 像素电极660设置于部分保护层652上, 且像素电极660经由通孔649耦接漏极646,并延伸至下一级栅极线620的部分区域,以形成于储存电容662。 The pixel electrode 660 is provided on a portion of the protective layer 652, and the pixel electrode 660 through a via 649 coupled to the drain electrode 646, and extends to a region of the lower part of the gate line 620 to form the storage capacitor 662.

此外,像素结构600尚包含第二基板680,其相对于第一基板610而设置, 且设有公共电极678。 Further, the pixel structure 600 includes a second substrate 680 yet, with respect to the first substrate 610 is provided, and the common electrode 678 is provided. 公共电极678与位于第一基板610的像素电极660两者之间设置有具介电系数的层664,其中,具介电系数的层664为-液晶层、一发光层(如:有机材料、无机材料、或上述的组合)或上述的组合,以显示对应的灰阶亮度。 The common electrode 678 positioned between the pixel electrode 660 of the first substrate 610 provided with a layer 664 having a dielectric constant, wherein the layer having a dielectric constant of 664 - liquid crystal layer, a light-emitting layer (such as: organic material, an inorganic material, or a combination thereof), or a combination thereof, in order to display the corresponding gray level.

由于本发明也可用于具蚀刻终止型薄膜晶体管的阵列于滤色片上型式的 Since the present invention can also be used with an array of etch stop thin film transistor on a color filter type

像素结构中,也就是阵列于滤色片上型式的像素结构600的薄膜晶体管640 位于栅极线620上,因此本发明也让具蚀刻终止型薄膜晶体管的阵列于滤色片上型式的像素结构增加显示区域,以提升显示效能。 Pixel structure, that is, the color filter array pattern of the pixel structure 640 of thin film transistor 600 is located on the gate line 620, thus the present invention also allows an array having the etch stop thin film transistor in the pixel structure of the color filter type display increased area to improve display performance. 请参阅图16,其为本发明的另一实施例的像素结构的俯视示意图。 Refer to FIG. 16, a plan view schematically showing a pixel structure according to another embodiment of the present invention thereof. 如图所示,本发明的像素结构700 包含第一基板710 (如图17所示)、栅极线720、数据线730、薄膜晶体管740、 像素电极760与储存电容762,而栅极线720、数据线730、薄膜晶体管740、 像素电极760以及储存电容762设置于第一基板710上,其中,栅极线720 与数据线730实质上相互交错,而薄膜晶体管740与储存电容762电性相接。 As shown, the pixel structure 700 of the present invention comprises a first substrate 710 (FIG. 17), the gate line 720, data line 730, the thin film transistor 740, the pixel electrode 760 and storage capacitor 762, and the gate line 720 , the data line 730, the thin film transistor 740, the pixel electrode 760 and storage capacitor 762 is provided on the first substrate 710, wherein the gate line 720 and data line 730 cross each other substantially, the thin film transistor 740 and the storage capacitor 762 is electrically phase access. 此实施例的薄膜晶体管740位于栅极线720上,且像素结构700更包含-通孔754,其同样位于栅极线720上,且通孔754相对于薄膜晶体管740,而栅极线720的延伸部724延伸至通孔754,以作为薄膜晶体管740的栅极。 The thin film transistor 740 of this embodiment the gate line 720, and the pixel structure 700 further comprises - a through hole 754, which is also located on the gate line 720, and the through-hole 754 with respect to the thin film transistor 740, the gate line 720 extension portion 724 extends to the through holes 754, as the gate electrode of the thin film transistor 740. 此实施例的薄膜晶体管740为一蚀刻终止型的薄膜晶体管,其所包含的蚀刻终止层750相对于薄膜晶体管740的栅极,并位于薄膜晶体管的半导体层(图未示) 上,薄膜晶体管740的源极744与漏极746位于蚀刻终止层750两端上,且皆位于栅极线720上,其中源极744耦接于数据线730。 The thin film transistor 740 of this embodiment is a thin film transistor etch stop, etching it contains a gate layer 750 with respect to the termination of the thin film transistor 740, and the semiconductor layer of the thin film transistor (not shown) on the thin film transistor 740 the source and drain 744 is located an etch stop layer 746 on the ends 750 and 720 are located on the gate line, wherein the source 744 is coupled to data line 730. 像素电极760经由通孔749耦接于漏极746,且部分像素电极760延伸至对应于下一级栅极线720的部分区域,以形成储存电容762。 The pixel electrode 760 through a via 749 coupled to the drain 746, and a portion of the pixel electrode 760 region extends to a corresponding portion of the lower gate line 720, 762 to form a storage capacitor.

此外,本发明的像素结构700的另一实施例,不将像素电极760延伸至下一级栅极线720的部分区域,而设置公共线(图未示)于第一基板710上,以在像素电极760与公共线的间形成储存电容。 In addition, another pixel structure of the present invention embodiment 700, the pixel electrode 760 does not extend to the region of the lower portion of a gate line 720, the common line is provided (not shown) on the first substrate 710, in order to the pixel electrode 760 is formed between the storage capacitor and the common line. 此外,第一基板710上更可设置至少一虚设图案(图未示),以检测像素结构700的缺陷(如:残留物与像素结构700内任一层导体层及/或半导体层接触所产生的短路等),其中一实施方式,虚设图案可位于像素结构700的四个角落,此仅为本发明的一实施例并不局限虚设图案所设置的位置,也可选择性地设置于像素结构700中的任--位置,例如:环绕该显示区域、设置于易发生残留物之处、平行栅极线720、数据线730的其中至少一者设置、或其它设置方式。 In addition, more can be provided at least one dummy pattern (not shown) to detect defective pixel structure 700 (e.g., on a first substrate 710: 700 within the pixel structure of any residue and / or the conductor layer in contact with one semiconductor layer produced as a short circuit), wherein an embodiment, the dummy pattern may be located at the four corners of the pixel structure 700, this is merely an embodiment of the present invention is not limited to the position of the dummy pattern is provided, also optionally be provided in the pixel structure 700 either - position, for example: around the display region, is provided to the easy occurrence of the residue, the parallel gate lines 720, data line 730 is provided wherein at least one, or other arrangement. 本发明可用曝露出第一基板710的通孔以作为虚设图案为例,但不限于此,也可选择性地为沟槽、狭缝、 或上述的混合使用。 The present invention may expose substrate 710 through holes in the first dummy pattern as an example, but is not limited thereto, and may also optionally use a trench, a slit, or a mixture thereof. 当然,若像素结构700不需要检测,则虚设图案也可不设置。 Of course, no need to detect if the pixel structure 700, the dummy pattern may not be provided. 又,本发明的像素结构700更包含至少一遮光层(图未示),其设置于第一基板710上,并与数据线730与栅极线720的至少一者平行,但不限于此, Further, the pixel structure 700 of the present invention further comprises at least a light-shielding layer (not shown), which is disposed on the first substrate 710, and the data line 720 and the gate line 730 parallel to at least one of, but is not limited thereto,

本发明的像素结构700也可不包含遮光层。 A pixel structure 700 of the present invention may also contain opacifying layer.

请参阅图17,其为图16的一实施例的剖视图。 Refer to FIG. 17, a cross-sectional view of the embodiment of FIG. 16 which is an embodiment of. 图17的剖视方向为图16 的EE,方向。 FIG direction cross-sectional view of FIG. 17 EE, the direction 16. 如图所示,本发明的像素结构700的栅极线720设置于第一基板710上,而薄膜晶体管740位于栅极线720上,其中栅极线720上设置通孔754, 且通孔754对应于薄膜晶体管740,对应于薄膜晶体管740的部分栅极线720 会经由通孔754将延伸部724延伸至薄膜晶体管740下而作为薄膜晶体管740 的栅极。 As shown, the pixel structure 700 of the present invention, a gate line 720 disposed on the first substrate 710, the thin film transistor 740 is located on the gate line 720, wherein the through-hole 754 is provided on the gate line 720, and the through hole 754 corresponding to the thin film transistor 740, a portion corresponding to the thin film transistor 740 of the gate lines 720 may extend through a via hole 754 extending to the lower thin film transistors 724 and 740 as a thin film transistor gate 740. 本实施例,较佳地,部分栅极线720的延伸部724是以从通孔754 的一边延伸但不连接于此通孔754的另一边为例,也就是说延伸部724为部分栅极线720延伸至通孔754中但未贯穿通孔754,但也可以连接至通孔754的另一边,也就是说部分栅极线720延伸至通孔754中并贯穿通孔754。 The present embodiment, preferably, the extension portion 720 of the gate lines 724 are through-holes extending from one side 754 but is not connected thereto through holes 754 of the other side as an example, that part of the gate extension portion 724 line 720 extends to the through-hole 754 but not through the through hole 754, but may be connected to the other side of the through hole 754, that portion of the gate line 720 extends to the through holes 754 and 754 through the through hole. 此实施例的薄膜晶体管740包含绝缘层722、半导体层748、源极744、漏极746、蚀刻终止层750与保护层752。 The thin film transistor 740 of this embodiment includes an insulating layer 722, semiconductor layer 748, source electrode 744, drain electrode 746, the etch stop layer 750 and the protective layer 752.

承接上述,绝缘层722设置于栅极线720上与部分第一基板710上。 Continuation of the above, an insulating layer 722 disposed on the gate line 720 and the upper portion of the first substrate 710. 半导体层748设置于对应薄膜晶体管740的部分绝缘层722上。 The semiconductor layer 748 is disposed on the insulating layer 722 corresponding to the portion 740 of the thin film transistor. 蚀刻终止层750 设置于半导体层748上,源极744与漏极746分别设置于半导体层748上及蚀刻终止层750两端上。 Etch stop layer 750 is provided on the semiconductor layer 748, source 744 and drain 746 are disposed on the semiconductor layer 748 and the etch stop layer 750 on both ends. 再者,本发明的实施例,较佳地,半导体层748 i:设置有掺杂半导体层732、 734,而分别接触源极744与漏极746,以降低电阻值。 Furthermore, embodiments of the present invention, preferably, the semiconductor layer 748 i: 732 is provided with a doped semiconductor layer, 734, 744 respectively contacting the source electrode and the drain electrode 746, to reduce the resistance value. 所以,蚀刻终止层750设置于半导体层748上,且掺杂半导体层732及734、 源极744与漏极746设置于蚀刻终止层750的二端。 Therefore, the etch stop layer 750 is provided on the semiconductor layer 748, and the doped semiconductor layer 732 and 734, source 744 and drain 746 disposed on the etch stop layer 750 of the two ends. 保护层752设置于源极744、漏极746与蚀刻终止层750上,保护层752也设置于部分第一基板710 所相对的部分绝缘层722上。 The protective layer 752 disposed on the source electrode 744, drain electrode 746 and the etching stop layer 750, protective layer 752 is also provided in the upper portion of the first substrate 710 opposite to the portion of the insulating layer 722. 另外,像素电极760设置于部分保护层752上, 且经通孔749耦接漏极746,而像素电极760延伸至下--级栅极线720,以形成储存电容762。 Further, the pixel electrode 760 is provided on a portion of the protective layer 752, and through the through hole 749 is coupled to the drain 746, and the pixel electrode 760 extends to the lower - level gate line 720, 762 to form a storage capacitor.

此外,像素结构700更包含第二基板780,其相对于第一基板710,而部分第二基板780设置有黑色矩阵770、滤色片层774与公共电极778。 Further, the pixel structure 700 further comprises a second substrate 780 with respect to the first substrate 710, and the portion of the second substrate 780 is provided with a black matrix 770, the color filter layer 774 and the common electrode 778. 其中黑色矩阵770设置于部分第二基板780,且对应于栅极线720与薄膜晶体管740 及/或数据线(图未示),且滤色片层774设置于对应像素电极760的第二基板780上。 Wherein the black matrix 770 disposed on the second substrate portion 780, and corresponds to the gate line 720 and the thin film transistor 740 and / or a data line (not shown), and the color filter layer 774 disposed on the second substrate corresponding to the pixel electrode 760 780 on. 公共电极778设置于滤色片层774上且耦接一共同电压,其与数据线传送至像素电极760的数据信号产生压差变化,因而驱使像素电极760与公共电极778所接触的一具介电系数的层764依据电压差变化显示对应的灰阶亮度。 The common electrode 778 disposed on the color filter layer 774 and is coupled to a common voltage, which transmits the data signal to the data lines of the pixel electrodes 760 generate pressure changes, thereby driving the pixel electrode 760 via a contact with the common electrode 778 coefficient of layer 764 corresponding to the display gray level according to the voltage difference change. 其中,具介电系数的层764为一液晶层、 一发光层(如:有机材料、无机 Wherein the layer having a dielectric constant of a liquid crystal layer 764, a light-emitting layer (such as: an organic material, an inorganic

材料、或上述的组合)或上述的组合,以显示对应的灰阶亮度。 Material, or a combination thereof), or a combination thereof, in order to display the corresponding gray level. 换句话说,具 In other words, with

介电系数的层764是设置于第一基板710及第二基板780之间。 Dielectric constant layer 764 is disposed between the first substrate 710 and the second substrate 780.

此外,为了能够降低滤色片层774的剥落的现象产生,在本实施例中,较佳地,包含一缓冲层771而设置于黑色矩阵770与第二基板上780,但不限于此,也可不形成缓冲层771或形成于滤色片层774之下及/或部分黑色矩阵770 上。 Further, in order to reduce the phenomenon of peeling of the color filter layer 774 to generate, in the present embodiment, preferably, it comprises a buffer layer 771 disposed on the black matrix 770 and the second substrate 780, but is not limited thereto, and the buffer layer 771 may not be formed or is formed under the color filter layer 774 and / or 770 on the black matrix portion. 当然,若为了解决滤色片层774的落差问题,在本实施例中,较佳地,包含一平坦层776设置于黑色矩阵770与滤色片层774上,但不限于此,像素结构700也可不设置平坦层776。 Of course, if the gap in order to solve the problem of the color filter layer 774, in this embodiment, preferably, comprises a planar layer 776 disposed on the black matrix 770 and the color filter layer 774, but is not limited thereto, the pixel structure 700 planarization layer 776 may not be provided. 又,栅极线720的延伸部724延仲至像素结构700的通孔754中而作为薄膜晶体管740的栅极,本实施例也可运用于如图14 与图15所示的像素结构型式,而应用于滤色片于阵列上型式的像素结构或阵列于滤色片上型式的像素结构。 Further, the gate line 724 extending to the secondary 720 extending through holes 700 in the pixel structure 754 as a gate electrode of the thin film transistor 740, the present embodiment also can be applied to the pixel structure of the type shown in FIG. 14 and FIG. 15, It is applied to the pixel structure or the color filter array in the pixel array pattern on the color filter structure type.

再者,本发明上述各实施例所述的第一基板310、 410、 510、 610及710 与第二基板390、 490、 590、 680及780的其中至少一者的材质,包含透明材质(如玻璃、石英、或其它材质)、不透明材质(如陶瓷、硅片、或其它材质) 及可挠性材质(如聚碳酸酯、聚氯乙烯或其它材质)。 Further, each of the first substrate in the embodiment of the present invention 310, 410, 510, 610 and 710 and the second substrate 390, 490, 590, 680 and 780 wherein the at least one material, comprising a transparent material (e.g. glass, quartz, or other materials), an opaque material (e.g., ceramic, silicon, or other materials) and flexible material (such as polycarbonate, polyvinyl chloride or other materials). 又,在上述各实施例中, 缓沖层、保护层、绝缘层及平坦层的其中至少一者的材质包含无机材质(如: 硅氧化物、硅氮化物、硅氮氧化物、碳化硅、氧化铪、或其它材料、或上述的组合)、有机材质(如:光刻胶、聚丙酰醚(polyaryleneether; PAE)、聚酰类、聚酯类、聚醇类、聚烯类、苯并环丁烯(benzocyclclobutene; BCB)、 HSQ (hydrogen silsesquioxane) 、 MSQ (methyl silesquioxane)、硅氧碳氢'it 物(SiOC-H)、或其它材质、或上述的组合)、或上述的组合。 Further, in the above embodiments, wherein at least one of the material of the buffer layer, a protective layer, an insulating layer and the planarization layer comprises an inorganic material (such as: silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, hafnium oxide, or other materials, or combinations thereof), organic material (such as: photoresist, polyacrylic acid ether (polyaryleneether; PAE), polyamide, polyesters, polyvinyl alcohols, polyolefine, benzo ring butene (benzocyclclobutene; BCB), HSQ (hydrogen silsesquioxane), MSQ (methyl silesquioxane), silicone hydrocarbon 'it was (SiOC-H), or other materials, or combinations thereof), or a combination thereof.

在上述各实施例中,是以有机材质的平坦层与无机材质的缓冲层、绝缘层及保护层为实施范例。 In the above embodiments, the planarization layer is an organic material and an inorganic material buffer layer, the insulating layer and the protective layer exemplary embodiment. 若缓冲层的材质为有机材质,为了解决原先的缓冲层与第二基板间的吸附力问题,较佳地,包含一无机材质的绝缘层(未图示)或具有-无机材质及一有机材质的多层绝缘层形成于第二基板上,且其材质如上所述。 If the buffer layer is made of an organic material, in order to solve the problem of the adsorption force between the original substrate and the second buffer layer, preferably comprising an insulating layer (not shown) or a material having an inorganic - organic material and an inorganic material the insulating layers formed on the second substrate, and the material described above. 又,在本发明上述各实施例中,所述的像素电极皆以透明材质(如:铟锡氧化物、铝锌氧化物、镉锡氧化物、铟锌氧化物、铝锡氧化物、或其它材料、 Further, in the above-described embodiments of the present invention, a transparent pixel electrode according to tailor materials (such as: indium tin oxide, aluminum zinc oxide, cadmium tin oxide, indium zinc oxide, aluminum tin oxide, or other material,

或上述的组合)为实施范例,但不限于此,也可选择性地为反射材质(如:铝 Or a combination thereof) of exemplary embodiments, but is not limited thereto, but also selectively reflective material (such as: aluminum

(Al)、金(Au)、银(Ag)、铬(Cr)、钼(Mo)、铌(Nb)、钛、魁、 (Al), gold (Au), silver (Ag), chromium (Cr), molybdenum (Mo), niobium (Nb), titanium, Quebec,

钨、钕、或上述的合金、或其它材料、或上述的组合)、或上述的透明材质与反射材质的组合。 Tungsten, neodymium, or alloys thereof, or other materials, or combinations thereof), or a combination thereof with transparent materials reflective material.

又,本发明上述各实施例,皆以具有黑色矩阵为实施例,但不限于此,也 Further, the above-described embodiments of the present invention, having a black matrix begin embodiments, but is not limited thereto, and

可不设置黑色矩阵,以数据线、栅极线、薄膜晶体管、公共线、遮光层、滤色片层堆栈其中至少一者当作黑色矩阵来使用。 The black matrix may not be provided to the data lines, gate lines, thin film transistors, the common line, the light shielding layer, color filter layer, wherein at least one stack as a black matrix used. 而上述各实施例所设置的黑色矩 And said each of the embodiments set black moment

阵皆以导电材质(如:铝(Al)、金(Au)、银(Ag)、铬(Cr)、钼(Mo)、 铌(Nb)、钛、钽、钨、钕、或上述的合金、或其它材料、或上述的组合) 为实施例,但不限于此,也可选择性地为有机材质(如:有色染料层、有色光刻胶、或至少二有色光刻胶堆栈、或其它材料)、或其它材料、或上述的组合。 Array tailor-conductive material (such as: aluminum (Al), gold (Au), silver (Ag), chromium (Cr), molybdenum (Mo), niobium (Nb), titanium, tantalum, tungsten, neodymium, or alloy thereof , or other materials, or combinations thereof) of Example, but is not limited thereto, and also optionally an organic material (such as: colored dye layer, a colored resist, or at least two colored photoresist stack, or other material), or other materials, or combinations thereof. 又,本发明上述各实施例所述的半导体层及掺杂半导体层的排列方式为垂直排列,也可选择性地为水平排列,且其材质包含含硅的非晶材质、含硅的多晶材质、含硅的微晶材质、含硅的单晶材质、或含锗的材质、或其它材料、或上述的组合。 Further, the present invention is the semiconductor layer of each example of the embodiments and the doped semiconductor layer is arranged in a vertical arrangement, also optionally be arranged horizontally, and the material comprises an amorphous material containing silicon, polycrystalline silicon material, a microcrystalline silicon-containing material, single crystal material containing silicon or germanium-containing materials, or other materials, or combinations thereof. 此外,本发明的半导体层是以非掺杂的半导体层(如本征半导体层) 为实施例,也可选择性地掺杂有掺杂子,且其浓度较掺杂半导体层的浓度较低。 In addition, the semiconductor layer of the present invention is a non-doped semiconductor layer (e.g., an intrinsic semiconductor layer) of Example, also optionally be doped with a doping promoter, and the doping concentration than the low concentration semiconductor layer . 并且若仅有半导体层时,其也可于预定区域形成非掺杂区、第一掺杂区及第二掺杂区的其中至少二者,且其排列方式可为垂直排列或水平排列。 And only if the semiconductor layer, which may also be formed in a predetermined region of the non-doped region, wherein the first doped region and the second doped region is at least two, and which arrangement may be arranged vertically or horizontally arranged.

此外,本发明上述各实施例的储存电容中的夹层皆以绝缘层及保护层的其中至少一者为范例,也可选择性地更夹设蚀刻终止层、半导体层及掺杂半导体层的其中至少一者于其储存电容中。 Further, the present invention is the above-described embodiment, the storage capacitors begin in the interlayer insulating layer and a protective layer wherein at least one of as an example, but also more selectively interposed an etch stop layer, wherein the doped semiconductor layer and the semiconductor layer at least one of the storage capacitor thereof.

如图18所示,本发明的一显示单元800包含多个像素结构802,其中该多个像素结构802为上述各实施例的像素结构的其中的一者,由此增加该多个像素结构802的显示区域,而让显示单元800提升显示效能。 18, a display unit 800 according to the present invention comprises a plurality of pixel structures 802, wherein the plurality of pixels of the pixel structure 802 is the structure in which the various embodiments of one, thereby increasing the plurality of pixel structure 802 display area, and let the display unit 800 to enhance display performance. 显示单元800 可运用于一光电装置810,且光电装置810,更具有至少--电子组件(图未示), 如:控制组件、操作组件、处理组件、输入组件、存储元件、驱动组件、或其它功能组件、或上述的组合。 The display unit 800 can be applied to a photovoltaic device 810, and the photovoltaic device 810, further has at least - an electronic component (not shown), such as: a control assembly, assembly operation, the processing component, an input component, a memory element, the drive assembly, or other functional components, or combinations thereof. 而光电装置810的类型包括携带式产品(如手机、 摄影机、照相机、笔记型计算机、游戏机、手表、音乐播放器、电子信件收发器、电子相框、地图导航器或类似的产品)、影音产品(如影音放映器或类似的产品)、屏幕、电视、室内或室外广告牌等。 The photovoltaic device 810 includes a portable type of products (such as mobile phones, video cameras, cameras, notebook computers, game machines, watches, music players, electronic mail transceiver, a digital photo frame map navigation or similar products), audio-visual products (such as video projection or similar products), screen, television, indoor or outdoor billboards. 又,本实施例的像素结构802 中的薄膜晶体管除了可为以上所述的各实施例中的底栅型,如:蚀刻终止型、 Further, the thin film transistors of the pixel structure 802 of the present embodiment may be in addition to various embodiments of the above-described embodiment, a bottom gate type, such as: type etch stop,

背通道蚀刻型外,也可为其它类型的薄膜晶体管且位于栅极在线,例如顶栅型, An outer back-channel-etch type, a gate line and may be other types of thin-film transistors, for example, a top gate type,

此外以对应于薄膜晶体管的部分栅极线作为薄膜晶体管的栅极。 In addition to a portion corresponding to the thin film transistor of the gate line as a gate of a thin film transistor.

但是以上所述者,仅为本发明的一较佳实施例而已,并非用来限定本发明实施的范围,所有根据本发明权利要求书所述的形状、构造、特征及精神所做的均等变化与修饰,均应包括于本发明的权利要求范围内。 However, those described above, merely a preferred embodiment of the present invention, but not intended to limit the scope of embodiments of the present invention, alterations of the shape of all made according to the present invention as claimed in the claims, structure, feature, or spirit and modifications shall be included in claims of the present invention within the scope of the claims.

Claims (36)

1、 一种像素结构,其包含: 一第一基板;至少一栅极线,设置于该第一基板上;至少一数据线,设置于该第一基板上,且该数据线与该栅极线相互交错: 至少一薄膜晶体管,设置于该第一基板上,并位于该栅极线上,且该薄膜晶体管分别耦接于该栅极线及该数据线;以及至少一像素电极,设置于该第一基板上,并耦接该薄膜晶体管的漏极。 1. A pixel structure comprising: a first substrate; at least a gate line disposed on the first substrate; at least one data line disposed on the first substrate, and the data line and the gate interdigitated lines: at least one thin film transistor disposed on the first substrate, the gate lines and positioned, and the thin film transistor are respectively coupled to the gate line and the data line; and at least a pixel electrode, disposed in the on the first substrate, and coupled to the drain of the thin film transistor.
2、 根据权利要求1所述的像素结构,其特征在于,该薄膜晶体管的类型包含底栅型或顶栅型。 2, the pixel structure according to claim 1, wherein the thin film transistor type comprising a bottom-gate-type or top gate type.
3、 根据权利要求1所述的像素结构,其特征在于,该像素电极经由一通孔耦接该漏极,且该通孔位于该栅极线上方。 3, the pixel structure according to claim 1, wherein the pixel electrode via a through hole coupled to the drain, and the gate line through the side hole is located.
4、 根据权利要求1所述的像素结构,其特征在于,该栅极线中对应f该薄膜晶体管的部分作为该薄膜晶体管的一栅极。 4. The pixel structure of claim 1, wherein the portion of the thin film transistor gate lines corresponding to f as a gate electrode of the thin film transistor.
5、 根据权利要求1所述的像素结构,其特征在于,该栅极线中对应于该薄膜晶体管的位置具有一通孔,该栅极线具有一延伸部延伸至该通孔中,以作为该薄膜晶体管的一栅极。 5. The pixel structure of claim 1, wherein the position of the gate lines corresponding to the thin film transistor having a through hole, the gate line has an extension portion extending to the through hole, as the a gate electrode of the thin film transistor.
6、 根据权利要求1所述的像素结构,其特征在于,更包含: 一第二基板,对应于该第一基板设置,该第二基板具有一公共电极。 6. The pixel structure of claim 1, wherein, further comprising: a second substrate, disposed corresponding to the first substrate, the second substrate having a common electrode.
7、 根据权利要求6所述的像素结构,其特征在于,更包含:一滤色片层,设置于该第一基板及该第二基板的其中一者上。 7. The pixel structure of claim 6, wherein, further comprising: a color filter layer is disposed on one of which the first substrate and the second substrate.
8、 根据权利要求7所述的像素结构,其特征在于,更包含:至少一绝缘层,设置于该第一基板及该第二基板的至少一者上。 8. The pixel structure of claim 7, wherein, further comprising: at least one insulating layer disposed on at least one of the first substrate and the second substrate.
9、 根据权利要求7所述的像素结构,其特征在于,更包含:一缓冲层,设置于该滤色片层之下。 9. The pixel structure of claim 7, wherein, further comprising: a buffer layer disposed beneath the color filter layer.
10、 根据权利要求7所述的像素结构,其特征在于,更包含: 一平坦层,其设置于该滤色片层上。 10. The pixel structure of claim 7, wherein, further comprising: a planarization layer disposed on the color filter layer.
11、 根据权利要求6所述的像素结构,其特征在于,更包含-一黑色矩阵,设置于该第一基板及该第二基板的其中一者上。 11. The pixel structure of claim 6, characterized in that, further comprising - a black matrix, one of which is provided on the first substrate and the second substrate.
12、 根据权利要求11所述的像素结构,其特征在于,该黑色矩阵对应覆盖于部分该像素电极、部分该栅极线及部分该数据线。 12. The pixel structure as claimed in claim 11, characterized in that the black matrix covers the portion corresponding to the pixel electrode, and a portion of the gate line portion of the data line.
13、 根据权利要求1所述的像素结构,其特征在于,更包含.-一公共线,与该栅极线平行设置于该第一基板上。 13. The pixel structure of claim 1, wherein, further comprising a common line .-, parallel to the gate line disposed on the first substrate.
14、 根据权利要求l、 11或13所述的像素结构,其特征在于,更包含: 至少一遮光层,与该数据线及该栅极线的至少一者平行设置于该第•基板上。 14, according to claim L, the pixel structure of claim 11 or 13, characterized in that, further comprising: at least a light-shielding layer, disposed in parallel on the first substrate and • at least one of the data lines and the gate line.
15、 根据权利要求1所述的像素结构,其特征在于,更包含: 至少一虚设图案,设置于该第一基板上。 15. The pixel structure of claim 1, wherein, further comprising: at least one dummy pattern is disposed on the first substrate.
16、 根据权利要求1所述的像素结构,其特征在于,该像素电极上更设置一具介电系数的层。 16. The pixel structure of claim 1, wherein a further layer is provided a dielectric constant on the pixel electrode.
17、 根据权利要求16所述的像素结构,其特征在于,该具介电系数的层包含液晶材料、发光层、或上述的组合。 17. The pixel structure of claim 16, wherein the layer having a dielectric constant comprising a liquid crystal material, a light emitting layer, or a combination thereof.
18、 根据权利要求l所述的像素结构,其特征在于,更包含:至少一储存电容,其电性连接于该薄膜晶体管。 18. The pixel structure as claimed in claim l, characterized in that, further comprising: at least one storage capacitor, which is electrically connected to the thin film transistor.
19、 一种光电装置,包含如权利要求l所述的像素结构。 19. A photovoltaic device, comprising a pixel structure as claimed in claim l.
20、 一种像素结构的制造方法,其包含: 提供一第一基板;形成至少一栅极线于该第一基板上;形成至少一数据线于该第一基板上,且该数据线与该栅极线相互交错-, 形成至少一薄膜晶体管于该第一基板上,且该薄膜晶体管位于该栅极线t,并分别耦接于该栅极线及该数据线;以及形成至少一像素电极于该第一基板上,且该像素电极耦接该薄膜晶体管。 20, a method of manufacturing a pixel structure, comprising: providing a first substrate; at least one gate line is formed on the first substrate; at least one data line formed on the first substrate, and the data line and the interdigitated gate lines -, at least one thin film transistor formed on the first substrate and the thin film transistor is located in the gate line t, and are respectively coupled to the gate line and the data line; and forming at least one pixel electrode on the first substrate, and the pixel electrode is coupled to the thin film transistor.
21、 根据权利要求20所述的方法,其特征在于,更包含: 提供一第二基板,相对于该第一基板,该第二基板具有一公共电极。 21. The method of claim 20, characterized in that, further comprising: providing a second substrate, with respect to the first substrate, the second substrate having a common electrode.
22、 根据权利要求21所述的方法,其特征在于,更包含:形成一滤色片层于该第一基板及该第二基板的其中一者上。 22. The method of claim 21, characterized in that, further comprising: forming a color filter wherein one layer on the first substrate and the second substrate.
23、 根据权利要求22所述的方法,其特征在于,更包含-形成至少一绝缘层于该第一基板及该第二基板的至少一者上。 23. The method of claim 22, characterized in that, further comprising - forming on at least one of the at least one insulating layer on the first substrate and the second substrate.
24、 根据权利要求22所述的方法,其特征在于,更包含:形成一缓冲层于该滤色片层之下。 24. The method of claim 22, characterized in that, further comprising: forming a buffer layer on the color filter layer below.
25、 根据权利要求22所述的方法,其特征在于,更包含: 形成一平坦层于该滤色片层上。 25. The method of claim 22, characterized in that, further comprising: forming a planarization layer on the color filter layer.
26、 根据权利要求21所述的方法,其特征在于,更包含: 形成一黑色矩阵于该第一基板及该第二基板的其中一者上。 26. The method of claim 21, characterized in that, further comprising: forming a black matrix wherein one of the first substrate and the second substrate.
27、 根据权利要求26所述的方法,其特征在于,该黑色矩阵对应覆盖于部分该像素电极、部分该栅极线及部分该数据线。 27. The method of claim 26, characterized in that the black matrix covers the portion corresponding to the pixel electrode, and a portion of the gate line portion of the data line.
28、 根据权利要求20所述的方法,其特征在于,更包含-形成一公共线于该第一基板上,且平行于该栅极线。 28. The method of claim 20, characterized in that, further comprising - forming a common line on the first substrate, and parallel to the gate line.
29、 根据权利要求20、 26或28所述的方法,其特征在于,更包含: 形成至少一遮光层于该第一基板上,且平行于该数据线及该栅极线的至少一者o 29. The method of claim 20, 26 or 28, characterized in that, further comprising: forming at least one of the at least a light-shielding layer on the first substrate, and parallel to the data line and the gate line o
30、 根据权利要求20所述的方法,其特征在于,更包含: 形成至少一虚设图案于该第一基板上。 30. The method according to claim 20, characterized in that, further comprising: at least one dummy pattern is formed on the first substrate to.
31、 根据权利要求20所述的方法,其特征在于,更包含:形成一具介电系数的层于该像素电极上。 31. The method of claim 20, characterized in that, further comprising: forming a layer of a dielectric constant on the pixel electrode.
32、 根据权利要求31所述的方法,其特征在于,该具介电系数的层包含液晶材料、发光层、或上述的组合。 32. The method of claim 31, wherein the layer having a dielectric constant comprising a liquid crystal material, a light emitting layer, or a combination thereof.
33、 根据权利要求20所述的方法,其特征在于,更包含-形成至少一储存电容,且与该薄膜晶体管电性相接。 33. The method of claim 20, characterized in that, further comprising - at least one storage capacitor is formed, and contact with the thin film transistor electrically.
34、 根据权利要求20所述的方法,其特征在于,该栅极线中对应于该薄膜晶体管的部分作为该薄膜晶体管的一栅极。 34. The method of claim 20, wherein the portion of the gate line corresponding to the thin film transistor as a gate electrode of the thin film transistor.
35、 根据权利要求20所述的方法,其特征在于,更包含: 形成一通孔于该栅极线中,该通孔对应于该薄膜晶体管,该栅极线具有-延伸部延伸至该通孔中,以作为该薄膜晶体管的一栅极。 35. The method of claim 20, characterized in that, further comprising: a through hole formed in the gate lines, the through-hole corresponding to the thin film transistor having the gate line - extending portion extending to the through hole in order as a gate electrode of the thin film transistor.
36、 一种光电装置的制造方法,包含如权利要求20所述的制造方法。 36, a method of manufacturing a photovoltaic device, comprising a production method as claimed in claim 20.
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