CN114423147B - Printed circuit board link connection device, method, printed circuit board and equipment - Google Patents
Printed circuit board link connection device, method, printed circuit board and equipment Download PDFInfo
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- CN114423147B CN114423147B CN202210076479.1A CN202210076479A CN114423147B CN 114423147 B CN114423147 B CN 114423147B CN 202210076479 A CN202210076479 A CN 202210076479A CN 114423147 B CN114423147 B CN 114423147B
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- 239000010410 layer Substances 0.000 description 4
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/0245—Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/40—Constructional details, e.g. power supply, mechanical construction or backplane
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/184—Components including terminals inserted in holes through the printed circuit board and connected to printed contacts on the walls of the holes or at the edges thereof or protruding over or into the holes
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Details Of Connecting Devices For Male And Female Coupling (AREA)
Abstract
The application provides a printed circuit board link connection device, a method, a printed circuit board and equipment, wherein the device comprises a public port, a first control port and a second control port; each port comprises a first polarity pin and a second polarity pin, and the polarities of the first polarity pin and the second polarity pin of the common port are reversed and then are connected with the corresponding polarity pins of the storage connector; the polarity of the first polarity pin and the polarity of the second polarity pin of the first control port are reversed and then are connected with the corresponding polarity pins of the memory controller; and the polarity of the first polarity pin and the polarity of the second polarity pin of the second control port are reversed and then are connected with the corresponding polarity pins of the central processing unit. Based on the device, a link connection method, a printed circuit board and equipment are also provided. The application ensures the correct interconnection between the central processing unit and the storage connector and between the storage controller and the storage connector, reduces the number of the through holes in the link and reduces the impedance discontinuous effect caused by the through holes.
Description
Technical Field
The application belongs to the technical field of printed circuit board design, and particularly relates to a printed circuit board link connection device, a printed circuit board link connection method, a printed circuit board and equipment.
Background
In the design of personal computers on domestic platforms, the configuration of the system is becoming diversified, for example, for an m.2 link, some customers need to support PCIE configuration, and some customers need to support SATA configuration. In this case, the motherboard designer adds a Switch chip, i.e., a switching chip, which has two input ports and selects one of the two input ports for output. The two input ports are PCIe signals and Sata signals respectively, and the mainboard design needs to select corresponding channels according to customer requirements.
In order to achieve the above function, the mainstream design topology in the prior art is shown in fig. 1 below, wherein the switch chip includes three ports, one of which is connected to the m.2 interface, and the other two ports are respectively connected to the central processor and the SATA controller. The central processing unit sends out PCIe signals, can support the PCIE configuration of M.2, the SATA controller sends out SATA signals, can support the SATA configuration of M.2, and the Switch chip can select a proper port according to the user requirements so as to realize corresponding functions.
Although this design method can realize this function in principle, difficulties are encountered in designing an actual printed circuit board, as shown in fig. 2, the SATA link includes two via diagrams, and since the SATA link is a differential signal, the SATA link includes two signal lines DP and DN, where DP is the positive electrode of the differential signal; DN is the negative of the differential signal. In the whole link, it is required to ensure that DP is always connected to DP between different chips, DN is always connected to DN, and polarity inversion cannot be performed (i.e., DP is connected to DN). In general, in the case of motherboard design, the m.2 interface is far from the switch chip, the sata controller is near to the switch chip, and both the sata controller and the switch chip are on the front side of the printed circuit board, in which case, the switch chip and the sata controller chip near to the switch chip need to exchange signals in order to ensure that DP is connected with DP, DN is connected with DN. For example, after the signals of the sata controller come out of the surface layer of the printed circuit board, the signals cannot be directly connected with the switching chip (crossing of DP and DN occurs), the signals need to be replaced by another layer, and then replaced by the surface layer at the position close to the switching chip, so that the interconnection with the switching chip is realized. Although the design method meets the design requirement of the sata, as the signal needs to be changed for two layers, two through holes are added in the link, more space of the printed circuit board is occupied, additional impedance discontinuity points are introduced, the signal quality is influenced, and the design risk is increased.
Disclosure of Invention
In order to solve the technical problems, the application provides a printed circuit board link connection device, a method, a printed circuit board and equipment. The signal layer exchange between the exchange chip and the link of the memory controller is avoided, the space utilization rate of the board card is improved, the number of the link via holes is reduced, the signal quality is improved, and the risk of system design is reduced.
In order to achieve the above purpose, the present application adopts the following technical scheme:
a printed circuit board link connection device comprises a switching chip; the switching chip comprises a public port, a first control port and a second control port;
the common port comprises a first polarity pin and a second polarity pin, and the polarities of the first polarity pin and the second polarity pin of the common port are reversed and then are connected with the corresponding polarity pins of the storage connector;
the first control port comprises a first polarity pin and a second polarity pin, and the polarity of the first polarity pin and the polarity of the second polarity pin of the first control port are reversed and then are connected with the corresponding polarity pins of the memory controller;
the second control port comprises a first polarity pin and a second polarity pin, and the polarity of the first polarity pin and the polarity of the second polarity pin of the second control port are reversed and then are connected with the corresponding polarity pins of the central processing unit.
Further, the first polarity pin is a differential signal positive electrode pin; the second polarity pin is a differential signal negative electrode pin.
Further, the storage connector includes, but is not limited to, an m.2 connector.
Further, the storage controller includes, but is not limited to, a SATA controller.
Further, after polarity inversion of the differential signal positive electrode pin and the differential signal negative electrode pin of the common port of the exchange chip, the inverted differential signal positive electrode pin is connected to the positive electrode pin of the M.2 connector; the positive terminal of the differential signal after inversion is connected to the negative terminal of the m.2 connector.
Further, after polarity inversion of the differential signal positive electrode pin and the differential signal negative electrode pin of the first control port of the exchange chip, the inverted differential signal positive electrode pin is connected to the positive electrode pin of the SATA controller; the positive electrode pin of the differential signal after inversion is connected to the negative electrode pin of the SATA controller.
Further, after the polarities of the differential signal positive electrode pin and the differential signal negative electrode pin of the second control port of the exchange chip are reversed, the reversed differential signal positive electrode pin is connected to the positive electrode pin of the central processing unit; the positive electrode pin of the differential signal after inversion is connected to the negative electrode pin of the central processing unit.
The application also provides a printed circuit board link connection method based on the printed circuit board link connection device, which comprises the following steps:
the polarity of the first polarity pin and the polarity of the second polarity pin of the common port of the exchange chip are reversed and then are connected with the corresponding polarity pins of the storage connector;
the polarities of a first polarity pin and a second polarity pin of a first control pin of the exchange chip are reversed and then are connected with a corresponding storage controller of the storage connector;
and the polarity of the first polarity pin and the polarity of the second polarity pin of the second control pin of the exchange chip are reversed and then are connected with the corresponding central processing unit of the storage connector.
The application also provides a printed circuit board, which comprises the printed circuit board link connecting device.
The application also proposes a device comprising a printed circuit board.
The effects provided in the summary of the application are merely effects of embodiments, not all effects of the application, and one of the above technical solutions has the following advantages or beneficial effects:
the application provides a printed circuit board link connection device, a method, a printed circuit board and equipment, wherein the device comprises a public port, a first control port and a second control port; the common port comprises a first polarity pin and a second polarity pin, and the polarities of the first polarity pin and the second polarity pin of the common port are reversed and then are connected with the corresponding polarity pins of the storage connector; the first control port comprises a first polarity pin and a second polarity pin, and the polarity of the first polarity pin and the polarity of the second polarity pin of the first control port are reversed and then are connected with the corresponding polarity pins of the memory controller; the second control port comprises a first polarity pin and a second polarity pin, and the polarity of the first polarity pin and the polarity of the second polarity pin of the second control port are reversed and then are connected with the corresponding polarity pins of the central processing unit. According to the application, after the polarities of the differential signal positive pins and the differential signal negative pins of the three ports of the exchange chip are reversed, on the premise of meeting the design requirement of the SATA link, the correct interconnection between the central processing unit and the storage connector and between the storage controller and the storage connector is ensured, meanwhile, the number of through holes in the link is reduced, the impedance discontinuity effect caused by the through holes is reduced, the signal integrity problem is reduced, and the reliability of the system is improved.
Based on a printed circuit board link connection device, a printed circuit board link connection method, a printed circuit board and equipment are also provided. The same effects as described above are obtained.
Drawings
FIG. 1 is a schematic diagram of a prior art M.2 connector link topology;
FIG. 2 is a schematic diagram of a SATA link of the prior art with two portions Kong Tapu;
fig. 3 is a schematic diagram of a link topology of an m.2 connector in embodiment 1 of the present application;
fig. 4 is a schematic diagram of the working principle of the exchange chip in embodiment 1 of the present application;
fig. 5 is a flowchart of a method for connecting a printed circuit board link according to embodiment 2 of the present application.
Detailed Description
In order to clearly illustrate the technical features of the present solution, the present application will be described in detail below with reference to the following detailed description and the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different structures of the application. In order to simplify the present disclosure, components and arrangements of specific examples are described below. Furthermore, the present application may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and processes are omitted so as to not unnecessarily obscure the present application.
Example 1
The embodiment 1 of the application provides a printed circuit board link connection device. The system topology supporting two configurations of the M.2 connector and the sata controller is required, and the polarity inversion design method of the exchange chip is provided, so that signal exchange layers between the exchange chip and a link of the storage controller are avoided, the space utilization rate of the board card is improved, the number of link through holes is reduced, the signal quality is improved, and the risk of system design is reduced.
The conventional design topology introduces two vias in the SATA link, but the SATA protocol does not support signal polarity inversion of the differential signal positive pin and the differential signal negative pin of the active device, and cannot eliminate the vias. According to the embodiment 1 of the application, the polarity of all ports of the switch chip is changed by means of the passive characteristic of the switch chip, namely the switch chip does not recognize the differential signal positive electrode pin and the differential signal negative electrode pin, and meanwhile, the correct interconnection of links is ensured by the design of the printed circuit board, so that the purpose of optimizing the SATA links is achieved, the influence of the through holes on signals can be effectively reduced, and the reliability of the system is improved.
Fig. 3 is a schematic diagram of a link topology of an m.2 connector in embodiment 1 of the present application; the device comprises an exchange chip; the switching chip comprises a public port, a first control port and a second control port;
the common port comprises a first polarity pin and a second polarity pin, and the polarities of the first polarity pin and the second polarity pin of the common port are reversed and then are connected with the corresponding polarity pins of the storage connector;
the first control port comprises a first polarity pin and a second polarity pin, and the polarity of the first polarity pin and the polarity of the second polarity pin of the first control port are reversed and then are connected with the corresponding polarity pins of the memory controller;
the second control port comprises a first polarity pin and a second polarity pin, and the polarity of the first polarity pin and the polarity of the second polarity pin of the second control port are reversed and then are connected with the corresponding polarity pins of the central processing unit.
Wherein DP is the positive electrode pin of the differential signal, and DN is the negative electrode pin of the differential signal.
M.2 connector is a storage connector, SATA controller is a storage controller, switch chip is a switching chip, CPU is a central processing unit.
In fig. 3, only the DP and DN polarities of three ports of the switch chip are changed, and the DP and DN polarities of the rest chips are unchanged.
After polarity inversion of the differential signal positive electrode pin and the differential signal negative electrode pin of the common port of the exchange chip, connecting the inverted differential signal positive electrode pin to the positive electrode pin of the M.2 connector; the positive terminal of the differential signal after inversion is connected to the negative terminal of the m.2 connector.
After polarity inversion of the differential signal positive electrode pin and the differential signal negative electrode pin of the first control port of the exchange chip, connecting the inverted differential signal positive electrode pin to the positive electrode pin of the SATA controller; the positive electrode pin of the differential signal after inversion is connected to the negative electrode pin of the SATA controller.
After the polarities of the differential signal positive electrode pin and the differential signal negative electrode pin of the second control port of the exchange chip are reversed, the reversed differential signal positive electrode pin is connected to the positive electrode pin of the central processing unit; the positive electrode pin of the differential signal after inversion is connected to the negative electrode pin of the central processing unit.
In fig. 3, PCIE signals are between Switch and CPU, supporting polarity inversion (i.e., DP and DN connected), without regard to this problem. The switch to M.2 interface is far away, the topology itself contains a via hole, correct interconnection of signal polarity can be realized at the via hole, and different connection modes can be selected according to requirements by a polarity adjustment mode at the via hole.
Fig. 4 is a schematic diagram illustrating the working principle of the exchange chip in embodiment 1 of the present application. The chip is an analog switch and is only responsible for port gating, and whether DP or DN is recognized by the chip itself is not. Therefore, the design method can ensure the correct interconnection between the CPU and the M.2 connector and between the sata Controller and the M.2 connector, simultaneously reduce the number of the through holes in the link, reduce the impedance discontinuous effect caused by the through holes, reduce the signal integrity problem and improve the reliability of the system.
The embodiment 1 of the application provides a printed circuit board link connecting device, which ensures correct interconnection between a central processing unit and a storage connector and between the storage controller and the storage connector on the premise of meeting the design requirement of a SATA link after polarity inversion of differential signal positive pins and differential signal negative pins of three ports of a switching chip, reduces the number of through holes in the link, reduces impedance discontinuity effect caused by the through holes, reduces the signal integrity problem and improves the reliability of the system.
Example 2
Based on the printed circuit board link connection device provided in embodiment 1 of the present application, embodiment 2 of the present application further provides a printed circuit board link connection method, as shown in fig. 5, which is a flowchart of a printed circuit board link connection method in embodiment 2 of the present application.
In step S501, the polarities of the first polarity pin and the second polarity pin of the common port of the switch chip are reversed and then connected with the corresponding polarity pins of the memory connector;
in step S502, the polarities of the first polarity pin and the second polarity pin of the first control pin of the switch chip are reversed and then connected with the corresponding memory controller of the memory connector;
in step S503, the polarities of the first polarity pin and the second polarity pin of the second control pin of the switch chip are reversed and then connected to the central processor corresponding to the memory connector.
After polarity inversion of the differential signal positive electrode pin and the differential signal negative electrode pin of the common port of the exchange chip, connecting the inverted differential signal positive electrode pin to the positive electrode pin of the M.2 connector; the positive terminal of the differential signal after inversion is connected to the negative terminal of the m.2 connector.
After polarity inversion of the differential signal positive electrode pin and the differential signal negative electrode pin of the first control port of the exchange chip, connecting the inverted differential signal positive electrode pin to the positive electrode pin of the SATA controller; the positive electrode pin of the differential signal after inversion is connected to the negative electrode pin of the SATA controller.
After the polarities of the differential signal positive electrode pin and the differential signal negative electrode pin of the second control port of the exchange chip are reversed, the reversed differential signal positive electrode pin is connected to the positive electrode pin of the central processing unit; the positive electrode pin of the differential signal after inversion is connected to the negative electrode pin of the central processing unit.
The embodiment 2 of the application provides a printed circuit board link connection method, which ensures correct interconnection between a central processing unit and a storage connector and between the storage controller and the storage connector on the premise of meeting the design requirement of a SATA link after polarity inversion of differential signal positive pins and differential signal negative pins of three ports of a switching chip, reduces the number of through holes in the link, reduces impedance discontinuity effect caused by the through holes, reduces the signal integrity problem, and improves the reliability of the system.
Example 3
The embodiment 1 of the application provides a printed circuit board link connection device, and the embodiment 3 of the application provides a printed circuit board. The printed circuit board includes a printed circuit board link connection device.
Fig. 3 is a schematic diagram of a link topology of an m.2 connector in embodiment 1 of the present application; the device comprises an exchange chip; the switching chip comprises a public port, a first control port and a second control port;
the common port comprises a first polarity pin and a second polarity pin, and the polarities of the first polarity pin and the second polarity pin of the common port are reversed and then are connected with the corresponding polarity pins of the storage connector;
the first control port comprises a first polarity pin and a second polarity pin, and the polarity of the first polarity pin and the polarity of the second polarity pin of the first control port are reversed and then are connected with the corresponding polarity pins of the memory controller;
the second control port comprises a first polarity pin and a second polarity pin, and the polarity of the first polarity pin and the polarity of the second polarity pin of the second control port are reversed and then are connected with the corresponding polarity pins of the central processing unit.
Wherein DP is the positive electrode pin of the differential signal, and DN is the negative electrode pin of the differential signal.
M.2 connector is a storage connector, SATA controller is a storage controller, switch chip is a switching chip, CPU is a central processing unit.
In fig. 3, only the DP and DN polarities of three ports of the switch chip are changed, and the DP and DN polarities of the rest chips are unchanged.
After polarity inversion of the differential signal positive electrode pin and the differential signal negative electrode pin of the common port of the exchange chip, connecting the inverted differential signal positive electrode pin to the positive electrode pin of the M.2 connector; the positive terminal of the differential signal after inversion is connected to the negative terminal of the m.2 connector.
After polarity inversion of the differential signal positive electrode pin and the differential signal negative electrode pin of the first control port of the exchange chip, connecting the inverted differential signal positive electrode pin to the positive electrode pin of the SATA controller; the positive electrode pin of the differential signal after inversion is connected to the negative electrode pin of the SATA controller.
After the polarities of the differential signal positive electrode pin and the differential signal negative electrode pin of the second control port of the exchange chip are reversed, the reversed differential signal positive electrode pin is connected to the positive electrode pin of the central processing unit; the positive electrode pin of the differential signal after inversion is connected to the negative electrode pin of the central processing unit.
In fig. 3, PCIE signals are between Switch and CPU, supporting polarity inversion (i.e., DP and DN connected), without regard to this problem. The switch to M.2 interface is far away, the topology itself contains a via hole, correct interconnection of signal polarity can be realized at the via hole, and different connection modes can be selected according to requirements by a polarity adjustment mode at the via hole.
Fig. 4 is a schematic diagram illustrating the working principle of the exchange chip in embodiment 1 of the present application. The chip is an analog switch and is only responsible for port gating, and whether DP or DN is recognized by the chip itself is not. Therefore, the design method can ensure the correct interconnection between the CPU and the M.2 connector and between the sata Controller and the M.2 connector, simultaneously reduce the number of the through holes in the link, reduce the impedance discontinuous effect caused by the through holes, reduce the signal integrity problem and improve the reliability of the system.
The embodiment 3 of the application provides a printed circuit board, which ensures correct interconnection between a central processing unit and a storage connector and between the storage controller and the storage connector on the premise of meeting the design requirement of a SATA link after polarity inversion of differential signal positive pins and differential signal negative pins of three ports of a switching chip, reduces the number of through holes in the link, reduces impedance discontinuity effect caused by the through holes, reduces signal integrity problem, and improves system reliability.
Example 4
The printed circuit board according to embodiment 3 of the present application and the device according to embodiment 4 of the present application are provided. The apparatus includes a printed circuit board including a printed circuit board link connection device.
Fig. 3 is a schematic diagram of a link topology of an m.2 connector in embodiment 1 of the present application; the device comprises an exchange chip; the switching chip comprises a public port, a first control port and a second control port;
the common port comprises a first polarity pin and a second polarity pin, and the polarities of the first polarity pin and the second polarity pin of the common port are reversed and then are connected with the corresponding polarity pins of the storage connector;
the first control port comprises a first polarity pin and a second polarity pin, and the polarity of the first polarity pin and the polarity of the second polarity pin of the first control port are reversed and then are connected with the corresponding polarity pins of the memory controller;
the second control port comprises a first polarity pin and a second polarity pin, and the polarity of the first polarity pin and the polarity of the second polarity pin of the second control port are reversed and then are connected with the corresponding polarity pins of the central processing unit.
Wherein DP is the positive electrode pin of the differential signal, and DN is the negative electrode pin of the differential signal.
M.2 connector is a storage connector, SATA controller is a storage controller, switch chip is a switching chip, CPU is a central processing unit.
In fig. 3, only the DP and DN polarities of three ports of the switch chip are changed, and the DP and DN polarities of the rest chips are unchanged.
After polarity inversion of the differential signal positive electrode pin and the differential signal negative electrode pin of the common port of the exchange chip, connecting the inverted differential signal positive electrode pin to the positive electrode pin of the M.2 connector; the positive terminal of the differential signal after inversion is connected to the negative terminal of the m.2 connector.
After polarity inversion of the differential signal positive electrode pin and the differential signal negative electrode pin of the first control port of the exchange chip, connecting the inverted differential signal positive electrode pin to the positive electrode pin of the SATA controller; the positive electrode pin of the differential signal after inversion is connected to the negative electrode pin of the SATA controller.
After the polarities of the differential signal positive electrode pin and the differential signal negative electrode pin of the second control port of the exchange chip are reversed, the reversed differential signal positive electrode pin is connected to the positive electrode pin of the central processing unit; the positive electrode pin of the differential signal after inversion is connected to the negative electrode pin of the central processing unit.
In fig. 3, PCIE signals are between Switch and CPU, supporting polarity inversion (i.e., DP and DN connected), without regard to this problem. The switch to M.2 interface is far away, the topology itself contains a via hole, correct interconnection of signal polarity can be realized at the via hole, and different connection modes can be selected according to requirements by a polarity adjustment mode at the via hole.
Fig. 4 is a schematic diagram illustrating the working principle of the exchange chip in embodiment 1 of the present application. The chip is an analog switch and is only responsible for port gating, and whether DP or DN is recognized by the chip itself is not. Therefore, the design method can ensure the correct interconnection between the CPU and the M.2 connector and between the sata Controller and the M.2 connector, simultaneously reduce the number of the through holes in the link, reduce the impedance discontinuous effect caused by the through holes, reduce the signal integrity problem and improve the reliability of the system.
The embodiment 4 of the application provides equipment, which ensures correct interconnection between a central processing unit and a storage connector and between the storage controller and the storage connector on the premise of meeting the design requirement of a SATA link after polarity inversion of differential signal positive pins and differential signal negative pins of three ports of a switching chip, reduces the number of through holes in the link, reduces impedance discontinuity effect caused by the through holes, reduces signal integrity problem and improves system reliability.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements is inherent to. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In addition, the parts of the above technical solutions provided in the embodiments of the present application, which are consistent with the implementation principles of the corresponding technical solutions in the prior art, are not described in detail, so that redundant descriptions are avoided.
While the specific embodiments of the present application have been described above with reference to the drawings, the scope of the present application is not limited thereto. Other modifications and variations to the present application will be apparent to those of skill in the art upon review of the foregoing description. It is not necessary here nor is it exhaustive of all embodiments. On the basis of the technical scheme of the application, various modifications or variations which can be made by the person skilled in the art without the need of creative efforts are still within the protection scope of the application.
Claims (10)
1. A printed circuit board link connection device is characterized by comprising a switching chip; the switching chip comprises a public port, a first control port and a second control port;
the common port comprises a first polarity pin and a second polarity pin, and the polarities of the first polarity pin and the second polarity pin of the common port are reversed and then are connected with the corresponding polarity pins of the storage connector;
the first control port comprises a first polarity pin and a second polarity pin, and the polarity of the first polarity pin and the polarity of the second polarity pin of the first control port are reversed and then are connected with the corresponding polarity pins of the memory controller;
the second control port comprises a first polarity pin and a second polarity pin, and the polarity of the first polarity pin and the polarity of the second polarity pin of the second control port are reversed and then are connected with the corresponding polarity pins of the central processing unit.
2. The printed circuit board link connection of claim 1, wherein the first polarity pin is a differential signal positive pin; the second polarity pin is a differential signal negative electrode pin.
3. A printed circuit board link connection according to claim 2 wherein the storage connector includes, but is not limited to, an m.2 connector.
4. The printed circuit board link connection of claim 2 wherein the storage controller includes, but is not limited to, a SATA controller.
5. A printed circuit board link connection according to claim 3, wherein after polarity inversion of the differential signal positive pin and the differential signal negative pin of the common port of the switch chip, the inverted differential signal positive pin is connected to the positive pin of the m.2 connector; the positive terminal of the differential signal after inversion is connected to the negative terminal of the m.2 connector.
6. The printed circuit board link connection device of claim 4, wherein after polarity inversion of the differential signal positive pin and the differential signal negative pin of the first control port of the switch chip, the inverted differential signal positive pin is connected to the positive pin of the SATA controller; the positive electrode pin of the differential signal after inversion is connected to the negative electrode pin of the SATA controller.
7. The device according to claim 2, wherein after polarity inversion of the differential signal positive pin and the differential signal negative pin of the second control port of the switching chip, the inverted differential signal positive pin is connected to the positive pin of the central processing unit; the positive electrode pin of the differential signal after inversion is connected to the negative electrode pin of the central processing unit.
8. A printed circuit board link connection method based on the printed circuit board link connection device according to any one of claims 1 to 7, characterized by comprising the steps of:
the polarity of the first polarity pin and the polarity of the second polarity pin of the common port of the exchange chip are reversed and then are connected with the corresponding polarity pins of the storage connector;
the polarities of a first polarity pin and a second polarity pin of a first control pin of the exchange chip are reversed and then are connected with a corresponding storage controller of the storage connector;
and the polarity of the first polarity pin and the polarity of the second polarity pin of the second control pin of the exchange chip are reversed and then are connected with the corresponding central processing unit of the storage connector.
9. A printed circuit board comprising the printed circuit board link connection device of any one of claims 1 to 7.
10. A printed circuit board link connection apparatus comprising a printed circuit board as claimed in claim 9.
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| CN202210076479.1A CN114423147B (en) | 2022-01-21 | 2022-01-21 | Printed circuit board link connection device, method, printed circuit board and equipment |
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| CN202210076479.1A CN114423147B (en) | 2022-01-21 | 2022-01-21 | Printed circuit board link connection device, method, printed circuit board and equipment |
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| CN114423147B true CN114423147B (en) | 2023-08-15 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016082518A1 (en) * | 2014-11-28 | 2016-06-02 | 中兴通讯股份有限公司 | Method and device for forming via-holes in pcb |
| CN206226833U (en) * | 2016-11-25 | 2017-06-06 | 湖南长城银河科技有限公司 | The printed circuit board (PCB) of optimal inspection via arrangement |
| CN210042315U (en) * | 2019-05-15 | 2020-02-07 | 深圳市红邦半导体有限公司 | Control circuit board, control chip and control system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101965095A (en) * | 2009-07-23 | 2011-02-02 | 鸿富锦精密工业（深圳）有限公司 | Printed circuit board |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016082518A1 (en) * | 2014-11-28 | 2016-06-02 | 中兴通讯股份有限公司 | Method and device for forming via-holes in pcb |
| CN206226833U (en) * | 2016-11-25 | 2017-06-06 | 湖南长城银河科技有限公司 | The printed circuit board (PCB) of optimal inspection via arrangement |
| CN210042315U (en) * | 2019-05-15 | 2020-02-07 | 深圳市红邦半导体有限公司 | Control circuit board, control chip and control system |
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| Title |
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| 印制电路板的设计;龙子夜;张杰;寇琼月;;武汉工业学院学报(第04期);全文 * |
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