CN114422654A - SDI output method, device, video processing equipment and readable storage medium - Google Patents
SDI output method, device, video processing equipment and readable storage medium Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/06—Generation of synchronising signals
- H04N5/067—Arrangements or circuits at the transmitter end
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/62—Queue scheduling characterised by scheduling criteria
- H04L47/622—Queue service order
Abstract
The invention relates to the field of video processing, and discloses a SDI output method, a device, video processing equipment and a readable storage medium, wherein the method comprises the following steps: the video data is written into the first-in first-out queue according to the first clock and the first timing. And reading the video data from the first-in first-out queue according to a second clock and the SDI protocol timing sequence, and sending the video data to the SDI interface for output through the serializer deserializer, wherein the second clock is a user clock of the serializer deserializer. And adjusting the user clock according to the number of the video data stored in the first-in first-out queue, so that the frequency of reading the video data from the first-in first-out queue is synchronous with the frequency of writing the video data into the first-in first-out queue. The frame synchronization of the SDI interface and the video data output by other video output interfaces is realized. When the video is displayed by splicing a plurality of interfaces, the spliced picture has no tearing phenomenon, and the display effect is effectively improved.
Description
Technical Field
The present application relates to the field of video processing, and in particular, to an SDI output method, an SDI output device, a video processing apparatus, and a readable storage medium.
Background
The video processing device is configured to receive a video signal, process the video signal, and output the video signal through a plurality of interfaces, where the commonly used video signal output interfaces include a display Interface (DP), a High Definition Multimedia Interface (HDMI), and a Digital Serial Interface (SDI).
The clock of the SDI interface is asynchronous with the clocks of video interfaces such as the DP interface and the HDMI interface, the SDI interface timing protocol is different from other interfaces, and cross-clock domain processing needs to be performed on data before output. This can lead to the unable video data frame synchronization with other video output interface outputs of SDI interface, and then leads to when using a plurality of interfaces concatenation to show the video, and the picture after the concatenation has the tearing phenomenon, and the display effect is not good.
Disclosure of Invention
The application mainly aims to provide an SDI output method, an SDI output device, video processing equipment and a readable storage medium, and aims to solve the problems that an SDI interface cannot be in frame synchronization with video data output by other video output interfaces, and therefore when a plurality of interfaces are used for splicing and displaying videos, the spliced images are torn, and the display effect is poor.
In a first aspect, the present application provides an SDI output method, including:
and writing the video data into the first-in first-out queue according to a first clock and a first time sequence, wherein the first clock is a clock used in non-SDI interface and video processing, and the first time sequence is a time sequence used in non-SDI interface and video processing.
And reading the video data from the first-in first-out queue according to a second clock and the SDI protocol timing sequence, and sending the video data to the SDI interface for output through the serializer deserializer, wherein the second clock is a user clock of the serializer deserializer.
And adjusting the user clock according to the number of the video data stored in the first-in first-out queue, so that the frequency of reading the video data from the first-in first-out queue is synchronous with the frequency of writing the video data into the first-in first-out queue.
In some embodiments, adjusting the user clock according to the number of video data stored in the fifo queue includes:
and when the number of the video data stored in the first-in first-out queue is larger than the first threshold value and continuously increases, reducing the frequency of the user clock so as to enable the number of the video data stored in the first-in first-out queue to be smaller than the first threshold value.
And when the number of the video data stored in the first-in first-out queue is smaller than the second threshold value and continuously decreases, increasing the frequency of the user clock so as to enable the number of the video data stored in the first-in first-out queue to be larger than the second threshold value.
In some embodiments, reducing the frequency of the user clock and/or increasing the frequency of the user clock comprises:
the frequency of the clock output by the phase locked loop is reduced by the phase interpolator controller module in the serializer deserializer so that the frequency of the user clock is reduced. And/or increasing the clock frequency output by the phase-locked loop through a phase interpolator controller module in the serializer deserializer so that the frequency of the user clock is increased.
In a second aspect, the present application further provides an SDI output device comprising:
the writing module is used for writing the video data into the first-in first-out queue according to a first clock and a first time sequence, wherein the first clock is a clock used in non-SDI interface and video processing, and the first time sequence is a time sequence used in non-SDI interface and video processing;
the reading module is used for reading the video data from the first-in first-out queue according to a second clock and an SDI protocol time sequence and sending the video data to an SDI interface for output through a serializer deserializer, and the second clock is a user clock of the serializer deserializer;
and the adjusting module is used for adjusting the user clock according to the number of the video data stored in the first-in first-out queue so as to synchronize the frequency of reading the video data from the first-in first-out queue with the frequency of writing the video data into the first-in first-out queue.
In some embodiments, the adjusting module is specifically configured to, when the number of video data stored in the first-in first-out queue is greater than a first threshold and continuously increases, decrease the frequency of the user clock so that the number of video data stored in the first-in first-out queue is smaller than the first threshold;
and when the number of the video data stored in the first-in first-out queue is smaller than the second threshold value and continuously decreases, increasing the frequency of the user clock so as to enable the number of the video data stored in the first-in first-out queue to be larger than the second threshold value.
In some embodiments, the adjusting module is specifically configured to reduce, by the phase interpolator controller module in the serializer, a clock frequency output by the phase-locked loop, so that a frequency of the user clock is reduced; and/or increasing the clock frequency output by the phase-locked loop through a phase interpolator controller module in the serializer deserializer so that the frequency of the user clock is increased.
In a third aspect, the present application further provides a video processing apparatus, including: the device comprises a video processing module, a first-in first-out queue module, a serializer deserializer and an output interface, wherein the output interface at least comprises an SDI interface. The input end of the video processing module is used for receiving input video signals, the output end of the video processing module is connected with the input end of the first-in first-out queue module, the output end of the video processing module outputs video data through a first clock and a first time sequence, and the first clock and the first time sequence are a clock and a time sequence used in non-SDI interface and video processing. The output end of the first-in first-out queue module is connected with the input end of the serializer deserializer, the serializer deserializer reads video data from the first-in first-out queue module through a second clock and an SDI protocol time sequence, and the second clock is a user clock of the serializer deserializer. And the output end of the deserializer is connected with the SDI interface.
In some embodiments, the video processing device further comprises an ultra high definition SDI soft core module. The ultra-high definition SDI soft core module is arranged between the video processing module and the first-in first-out queue module.
In some embodiments, the video processing device further comprises a phase interpolator controller module. The phase interpolator controller module is connected with the serializer deserializer.
In a fourth aspect, the present application also provides a computer-readable storage medium having a computer program stored thereon, where the computer program, when executed by a processor, implements the method as provided in the first aspect above.
According to the SDI output method, the device, the video processing equipment and the readable storage medium, video data are firstly written into the first-in first-out queue through the first clock and the first time sequence, then the number of the video data stored in the first-in first-out queue is adjusted, so that a certain time delay is generated when the video data are read from the first-in first-out queue, the frequency of reading the video data from the first-in first-out queue is synchronous with the frequency of the video data written into the first-in first-out queue through the time delay, and the frame synchronization of the video data output by the SDI interface and other video output interfaces is realized. When the video is displayed by splicing a plurality of interfaces, the spliced picture has no tearing phenomenon, and the display effect is effectively improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a video processing apparatus according to an embodiment of the present application;
fig. 2 is a schematic flowchart of an SDI output method according to an embodiment of the present application;
fig. 3 is a schematic flowchart of implementing S230 in an SDI output method according to an embodiment of the present application;
fig. 4 is a schematic block diagram of an SDI output device according to an embodiment of the present application.
The implementation, functional features and advantages of the objectives of the present application will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The flow diagrams depicted in the figures are merely illustrative and do not necessarily include all of the elements and operations/steps, nor do they necessarily have to be performed in the order depicted. For example, some operations/steps may be decomposed, combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.
The SDI output method provided by the embodiment of the application can be applied to video processing equipment, and the video processing equipment can be equipment with video processing and output capabilities, such as a desktop computer, a video acquisition card, a server and the like. The type of video processing device is not limited in this application.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
Fig. 1 is a schematic structural diagram of a video processing apparatus according to an embodiment of the present application.
In some embodiments, referring to fig. 1, the video processing apparatus 1 includes a video Processing (PGM) module 11, a First-in-First-out (FIFO) module 12, a Serializer/Deserializer (SerDes) 13, and an Output interface 14, where the Output interface includes at least one SDI interface 141. The input end of the video processing module 11 is used for receiving an input video signal, the output end of the video processing module 11 is connected with the input end of the first-in first-out queue module 12, the output end of the video processing module 11 outputs video data through a first clock and a first time sequence, the first clock is a clock (PgmClk) used when a non-SDI interface and a video are processed, and the first time sequence is a time sequence (Timing) used when the non-SDI interface and the video are processed. The output end of the fifo queue module 12 is connected to the input end of the serializer deserializer 13, the serializer deserializer 13 reads the video data from the fifo queue module 12 through a second clock (TxUserClk) of the serializer deserializer 13 and the SDI protocol timing, and the frequency of the user clock is synchronous with the first clock. The output terminal of the serializer deserializer 13 is connected to the SDI interface 141.
The video Processing module may be a Field Programmable Gate Array (FPGA), a Graphics Processing Unit (GPU), a Digital Signal Processing (DSP) chip, or the like. A serializer deserializer may be integrated into the video processing module, for example, a SerDes may be integrated into an FPGA and provide a SerDes interface.
The FIFO queue module may be an FIFO memory, the FIFO memory is divided into a write-in dedicated area and a read dedicated area, the read operation and the write operation may be performed asynchronously, and the data written in the write-in area may be read out from the area of the read end according to the write-in sequence. The video data inputted from the input terminal is stored in the write-dedicated area, and the serializer deserializer can read the stored video data from the read-dedicated area through the output terminal.
In some embodiments, the output Interface 14 may further include a DP Interface 142, an HDMI Interface 143, a Digital Visual Interface (DVI) Interface 144, and the like.
In some embodiments, the video processing device 1 further comprises an Ultra High Definition (UHD) SDI soft core (IP) module 15. The ultra-high definition SDI soft core module 15 is arranged between the video processing module and the first-in first-out queue module. The method is used for realizing framing and unframing of an SDI interface protocol layer.
In some embodiments, the video processing device 1 further includes a Phase Interpolator PPM Control (PICXO) module 16. The phase interpolator controller module 16 is connected to the serializer deserializer 13. As an example, the PICXO may be integrated in the SerDes of the FPGA, e.g., may be a Transmit (TX) PICXO in the SerDes. The FPGA can control a clock output by a Phase Locked Loop (PLL) through the PICXO, thereby adjusting the TxUserClk.
Note that, in fig. 1, the signaling route indicated by a solid line uses the PGM clock domain, that is, the clock thereof is PgmClk. While the signaling path, indicated by the dashed line, uses the TxUsrClk clock domain, i.e., its clock is TxUsrClk.
Fig. 2 is a schematic flowchart of an SDI output method according to an embodiment of the present application. The SDI output method provided by the present application can be used for the video processing apparatus shown in fig. 1.
Referring to fig. 2, the SDI output method includes:
and S210, writing the video data into a first-in first-out queue according to the first clock and the first time sequence.
In some embodiments, the first clock is a clock used in non-SDI interface and video processing, and the first timing is a timing used in non-SDI interface and video processing. For example, referring to the video processing apparatus shown in fig. 1, the first clock may be a clock PgmClk of the video processing module, and the first timing may be a timing of the video processing module.
It should be noted that the clock and the timing of other video output interfaces such as the DP interface and the HDMI interface in the video processing apparatus are also the first clock and the first timing.
In some embodiments, the video processing module may write the video data into the FIFO memory at the timing of the PgmClk and the video processing module. And the video processing module is used for processing the video data according to the received video signal and the time sequence of the PgmClk and the video processing module. The video signal can be a video signal collected by a camera, a video signal from a network, historical video data stored in a video processing module, or the like.
And S220, reading the video data from the first-in first-out queue according to the second clock and the SDI protocol timing sequence, and sending the video data to an SDI interface through a serializer deserializer for output.
In some embodiments, the second clock is a user clock (TxUserClk) of the serializer deserializer. The SerDes user clock may be adjusted by a Phase Interpolator (PI) control (Ctrl) signal sent by the PICXO. The PI Ctrl signal may control the clock output by the PLL in the SerDes, thereby adjusting TxUserClk.
And S230, adjusting the user clock according to the number of the video data stored in the first-in first-out queue, so that the frequency of reading the video data from the first-in first-out queue is synchronous with the frequency of writing the video data into the first-in first-out queue.
In this application, the synchronization of the frequency of reading video data from the fifo queue (reading frequency) and the frequency of writing video data to the fifo queue (writing frequency) means that the reading frequency is the same as or close to the writing frequency. For example, when the read frequency is the same as the write frequency, it can be confirmed that the read frequency is synchronized with the write frequency. Alternatively, when the difference between the reading frequency and the writing frequency is smaller than a preset threshold, it can be confirmed that the reading frequency and the writing frequency are synchronous.
The embodiments described in S210 to S230 are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The flow chart shown in fig. 2 is merely an illustration, and does not necessarily include all of the contents and operations/steps, nor does it necessarily have to be performed in the order described. For example, some operations/steps may be decomposed, combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.
Fig. 3 is a schematic flowchart of implementing S230 in an SDI output method according to an embodiment of the present disclosure.
In some embodiments, referring to fig. 3, adjusting the number of video data stored in the fifo queue to synchronize the frequency of the user clock with the first clock includes:
s231, when the number of the video data stored in the first-in first-out queue is larger than the first threshold value and continuously increases, reducing the frequency of the user clock so as to enable the number of the video data stored in the first-in first-out queue to be smaller than the first threshold value.
And S232, when the number of the video data stored in the first-in first-out queue is smaller than the second threshold value and continuously decreases, increasing the frequency of the user clock so as to enable the number of the video data stored in the first-in first-out queue to be larger than the second threshold value.
In this embodiment, in order to implement synchronization of multiple video output interfaces, synchronization of the SDI interface and other interfaces needs to be implemented. Since the frequency of writing data into the FIFO is synchronized with the other interfaces, it is necessary to synchronize the frequency of reading FIFO data with the frequency of writing data into the FIFO. When the number of the video data stored in the FIFO is greater than the second threshold and less than the first threshold, the time delay between the FIFO write data and the read data may cause the frequency of reading the FIFO data to be the same as or similar to the frequency of writing the FIFO data, i.e. the frequency of reading the FIFO data is synchronized with the frequency of writing the FIFO data.
As an example, when the storage depth of the FIFO is 4096, the first threshold value may be 3000 and the second threshold value may be 2000. That is, when the number of video data stored in the FIFO is 2000 to 3000, the frequency of reading out FIFO data is synchronized with the frequency of writing data in the FIFO.
In some embodiments, referring to the above example, the video processing module may obtain the number of data in the FIFO every 1 microsecond.
When the number of the video data stored in the FIFO is larger than 3000 and continuously increases, the frequency of the TxUserClk can be increased, and the speed of reading the video data in the FIFO is increased, so that the number of the video data stored in the FIFO is smaller than 3000.
When the number of the video data stored in the FIFO is less than 2000 and continuously decreases, the frequency of the TxUserClk can be reduced, and the speed of reading the video data in the FIFO is reduced, so that the number of the video data stored in the FIFO is less than 2000.
When the number of video data stored in the FIFO is greater than 2000 and less than 3000, the frequency of TxUserClk can be kept unchanged.
In some embodiments, reducing the frequency of the TxUserClk may reduce the frequency of the user clock by sending a reduced frequency PI Ctrl signal through the PICXO module to the PLL in the SerDes module to reduce the clock frequency of the PLL output.
The frequency of the TxUserClk is increased, a PI Ctrl signal for increasing the frequency can be sent to a PLL in a SerDes module through a PICXO module, and the clock frequency output by the PLL is increased, so that the frequency of a user clock is increased.
In this embodiment, the first clock and the first timing sequence write the video data into the fifo queue first, and then adjust the number of the video data stored in the fifo queue, so that a certain time delay is generated when the video data is read from the fifo queue, and the frequency of reading the video data from the fifo queue is synchronized with the frequency of the video data written into the fifo queue by the time delay, thereby realizing frame synchronization of the video data output by the SDI interface and other video output interfaces. When the video is displayed by splicing a plurality of interfaces, the spliced picture has no tearing phenomenon, and the display effect is effectively improved.
The embodiments described in S231 to S232 are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The flow chart shown in fig. 3 is merely an illustration, and does not necessarily include all of the contents and operations/steps, nor is it necessarily performed in the order described. For example, some operations/steps may be decomposed, combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.
Fig. 4 is a schematic block diagram of an SDI output device according to an embodiment of the present application.
Referring to fig. 4, the SDI output apparatus includes:
the writing module 401 is configured to write the video data into the fifo queue according to a first clock and a first timing sequence, where the first clock is a clock used during non-SDI interface and video processing, and the first timing sequence is a timing sequence used during non-SDI interface and video processing. And a reading module 402, configured to read the video data from the first-in first-out queue according to a second clock and an SDI protocol timing sequence, and send the video data to the SDI interface for output through the serializer deserializer, where the second clock is a user clock of the serializer deserializer. The adjusting module 403 is configured to adjust the user clock according to the number of the video data stored in the fifo queue, so that the frequency of the user clock is synchronized with the first clock.
In some embodiments, the adjusting module 403 is specifically configured to increase the frequency of the user clock when the number of the video data stored in the fifo queue is greater than the first threshold and continuously increases, so that the number of the video data stored in the fifo queue is smaller than the first threshold. And when the number of the video data stored in the first-in first-out queue is smaller than the second threshold value and continuously decreases, reducing the frequency of the user clock so as to enable the number of the video data stored in the first-in first-out queue to be larger than the second threshold value.
In some embodiments, the adjusting module 403 is specifically configured to decrease the clock frequency output by the phase-locked loop through a phase interpolator controller module in the serializer deserializer, so that the frequency of the user clock is decreased; and/or increasing the clock frequency output by the phase-locked loop through a phase interpolator controller module in the serializer deserializer so that the frequency of the user clock is increased.
It should be noted that, as will be clear to those skilled in the art, for convenience and brevity of description, the specific working processes of the apparatus and each module and unit described above may refer to the corresponding processes in the foregoing SDI output method embodiment, and no further description is provided herein.
The embodiments of the present application further provide a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the computer program implements the steps in the above-mentioned method embodiments.
The embodiments of the present application provide a computer program product, which when running on a mobile terminal, enables the mobile terminal to implement the steps in the above method embodiments when executed.
An embodiment of the present application provides a chip system, where the chip system includes a memory and a processor, and the processor executes a computer program stored in the memory to implement the steps in the foregoing method embodiments.
An embodiment of the present application provides a chip system, where the chip system includes a processor, the processor is coupled to a computer-readable storage medium, and the processor executes a computer program stored in the computer-readable storage medium to implement the steps in the above-mentioned method embodiments.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments. While the invention has been described with reference to specific embodiments, the scope of the invention is not limited thereto, and those skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the invention. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. An SDI output method, comprising:
writing video data into a first-in first-out queue according to a first clock and a first time sequence, wherein the first clock is a clock used in non-SDI interface and video processing, and the first time sequence is a time sequence used in non-SDI interface and video processing;
reading video data from the first-in first-out queue according to a second clock and an SDI protocol time sequence, and sending the video data to an SDI interface through a serializer deserializer for output, wherein the second clock is a user clock of the serializer deserializer;
and adjusting the user clock according to the number of the video data stored in the first-in first-out queue, so that the frequency of reading the video data from the first-in first-out queue is synchronous with the frequency of writing the video data into the first-in first-out queue.
2. The method of claim 1, wherein adjusting the user clock based on the number of video data stored in the fifo queue comprises:
when the number of the video data stored in the first-in first-out queue is larger than a first threshold value and continuously increases, reducing the frequency of the user clock so as to enable the number of the video data stored in the first-in first-out queue to be smaller than the first threshold value;
and when the number of the video data stored in the first-in first-out queue is smaller than a second threshold value and continuously decreases, increasing the frequency of the user clock so as to enable the number of the video data stored in the first-in first-out queue to be larger than the second threshold value.
3. The method of claim 2, wherein reducing the frequency of the user clock and/or increasing the frequency of the user clock comprises:
reducing, by a phase interpolator controller module in the serializer deserializer, a clock frequency output by a phase locked loop to cause a frequency of the user clock to be reduced; and/or the presence of a gas in the gas,
and increasing the clock frequency output by the phase interpolator through the phase interpolator controller module in the deserializer so as to increase the frequency of the user clock.
4. An SDI output device comprising:
the writing module is used for writing the video data into the first-in first-out queue according to a first clock and a first time sequence, wherein the first clock is a clock used in non-SDI interface and video processing, and the first time sequence is a time sequence used in non-SDI interface and video processing;
the reading module is used for reading video data from the first-in first-out queue according to a second clock and an SDI protocol time sequence and sending the video data to an SDI interface for output through a serializer deserializer, wherein the second clock is a user clock of the serializer deserializer;
and the adjusting module is used for adjusting the user clock according to the number of the video data stored in the first-in first-out queue, so that the frequency of reading the video data from the first-in first-out queue is synchronous with the frequency of writing the video data into the first-in first-out queue.
5. The apparatus according to claim 4, wherein the adjusting module is specifically configured to decrease the frequency of the user clock when the number of video data stored in the fifo queue is greater than a first threshold and continuously increases, so that the number of video data stored in the fifo queue is smaller than the first threshold;
and when the number of the video data stored in the first-in first-out queue is smaller than a second threshold value and continuously decreases, increasing the frequency of the user clock so as to enable the number of the video data stored in the first-in first-out queue to be larger than the second threshold value.
6. The apparatus according to claim 5, wherein the adjusting module is specifically configured to decrease the clock frequency output by the phase interpolator controller module in the serializer deserializer, so that the frequency of the user clock is decreased; and/or increasing the clock frequency output by the phase interpolator through the phase interpolator controller module in the serializer deserializer so that the frequency of the user clock is increased.
7. A video processing apparatus, comprising: the device comprises a video processing module, a first-in first-out queue module, a serializer deserializer and an output interface, wherein the output interface at least comprises an SDI (serial digital interface);
the input end of the video processing module is used for receiving an input video signal, the output end of the video processing module is connected with the input end of the first-in first-out queue module, the output end of the video processing module outputs video data through a first clock and a first time sequence, and the first clock and the first time sequence are a clock and a time sequence used in non-SDI interface and video processing;
the output end of the first-in first-out queue module is connected with the input end of the serializer deserializer, the serializer deserializer reads video data from the first-in first-out queue module through a second clock and an SDI protocol time sequence, and the second clock is a user clock of the serializer deserializer;
and the output end of the deserializer is connected with the SDI interface.
8. The apparatus of claim 7, further comprising an ultra high definition SDI soft core module;
the ultrahigh-definition SDI soft core module is arranged between the video processing module and the first-in first-out queue module.
9. The apparatus of claim 7 or 8, further comprising a phase interpolator controller module;
the phase interpolator controller module is connected to the serializer deserializer.
10. A computer-readable storage medium, having a computer program stored thereon, wherein the computer program, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 3.
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| CN202111592666.7A CN114422654A (en) | 2021-12-23 | 2021-12-23 | SDI output method, device, video processing equipment and readable storage medium |
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