CN114421566B - Charging management circuit and charging circuit comprising same - Google Patents
Charging management circuit and charging circuit comprising same Download PDFInfo
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- CN114421566B CN114421566B CN202210064044.5A CN202210064044A CN114421566B CN 114421566 B CN114421566 B CN 114421566B CN 202210064044 A CN202210064044 A CN 202210064044A CN 114421566 B CN114421566 B CN 114421566B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/00032—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries characterised by data exchange
- H02J7/00036—Charger exchanging data with battery
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
- H02J7/0031—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits using battery or load disconnect circuits
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
- H02J7/0036—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits using connection detecting circuits
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/007—Regulation of charging or discharging current or voltage
- H02J7/00712—Regulation of charging or discharging current or voltage the cycle being controlled or terminated in response to electric parameters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/02—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries for charging batteries from ac mains by converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J2207/00—Indexing scheme relating to details of circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J2207/20—Charging or discharging characterised by the power electronics converter
Abstract
The invention discloses a charging management circuit and a charging circuit comprising the same. The charging management circuit is connected with the flyback circuit, the flyback circuit is used for charging a load, the primary side comprises a first switching device connected with the primary coil in series, and the secondary side comprises an NMOS tube; the charging management circuit is used for detecting a first voltage between the drain electrode and the source electrode of the NMOS tube and a second voltage between the grid electrode and the source electrode, triggering a shoot through h protection under the condition that the first voltage is larger than a first threshold value and the second voltage is larger than a second threshold value, namely under the condition that the first switching device on the primary side and the NMOS tube on the secondary side are simultaneously conducted, namely outputting a first protection signal to control the first switching device on the primary side to be disconnected, and outputting a second protection signal to control the NMOS tube on the secondary side to be disconnected, so that the NMOS tube on the secondary side is protected from being damaged, and the reliability of the circuit is improved.
Description
Technical Field
The present invention relates to the field of charging technologies, and in particular, to a charging management circuit and a charging circuit including the same.
Background
Electronic devices are increasingly used in everyday life. The charging function is mainly performed by an AC/DC (alternating current/direct current) charger. In order to meet the demands of users, power levels are continuously increasing and electronic devices are continuously shrinking in size. Power conversion efficiency is required by official regulations, not only to achieve energy saving objectives, but also to meet user experience.
In order to improve the power conversion efficiency, different topologies and improved designs thereof are adopted in practical applications. Flyback circuits are a topology widely used for AC/DC conversion. A conventional flyback circuit has an output diode D1 as shown in fig. 1. The state loss of an output diode is proportional to its forward voltage drop and the current flowing through the diode. The output diode losses are very large, especially in high power stage applications, which also affects thermal performance.
In recent years, such output diodes may be replaced with synchronous rectifiers. In other words, a controlled MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, metal-Oxide semiconductor field effect transistor) replaces the output diode. As shown in fig. 2, the output diode D1 in fig. 1 is replaced by an NMOS transistor Q2, and the NMOS transistor Q2 can greatly reduce power loss. However, such synchronous rectifier MOSFETs (SR FETs for short) require precise control timing synchronized with the system operation to operate safely. If the control timing is wrong, the damage may be severe and even the entire design may explode. For example, if the NMOS transistor Q2 is still on when the switching device on the primary side is on, breakdown may occur while a high voltage and high current is sent across the NMOS transistor Q2, which will quickly damage the NMOS transistor Q2 and possibly also the switching device on the primary side, which may be very dangerous.
Disclosure of Invention
The invention aims to overcome the defect that a switching device on a primary side and an SR FET are conducted simultaneously to cause damage to the SR FET in the prior art, and provides a charging management circuit and a charging circuit comprising the same.
The invention solves the technical problems by the following technical scheme:
a first aspect of the present invention provides a charge management circuit connected to a flyback circuit for charging a load, the primary side of a transformer comprising a first switching device in series with a primary winding, the secondary side comprising an NMOS tube;
the charging management circuit is used for detecting a first voltage between the drain electrode and the source electrode of the NMOS tube and a second voltage between the grid electrode and the source electrode of the NMOS tube, and outputting a first protection signal and a second protection signal when the first voltage is larger than a first threshold value and the second voltage is larger than a second threshold value, wherein the first protection signal is used for indicating that the first switching device is disconnected, and the second protection signal is used for indicating that the NMOS tube is disconnected;
the first threshold is determined based on the voltage of the primary side when the NMOS tube is disconnected, the transformation ratio of the transformer and the output voltage of the flyback circuit, and the second threshold is determined based on the starting voltage of the NMOS tube.
Optionally, the flyback circuit is specifically configured to charge the load through a second switching device;
the charge management circuit is further configured to control the second switching device to open if the first voltage is greater than a first threshold and the second voltage is greater than a second threshold.
Optionally, the charging management circuit is connected with the load, and is used for controlling the power output by the flyback circuit to the load, and reducing the working current when the first voltage is smaller than a third threshold value and the second voltage is smaller than a fourth threshold value; the third threshold is determined based on the conduction voltage drop of the built-in diode of the NMOS tube, and the fourth threshold is determined based on the starting voltage of the NMOS tube.
Optionally, the secondary side of the flyback circuit further comprises an SR control chip;
the charge management circuit comprises a PD protocol control chip, a first protection signal and a second protection signal, wherein the PD protocol control chip is used for detecting a first voltage between a drain electrode and a source electrode of the NMOS tube and a second voltage between a grid electrode and the source electrode, and outputting the second protection signal to the SR control chip under the condition that the first voltage is larger than a first threshold value and the second voltage is larger than a second threshold value;
the SR control chip is used for sending a control signal to the grid electrode of the NMOS tube and controlling the NMOS tube to be disconnected under the condition that the second protection signal is received.
Optionally, the charge management circuit includes a PD protocol control chip, configured to send a control signal to a gate of the NMOS transistor, and detect a first voltage between a drain and a source of the NMOS transistor and a second voltage between the gate and the source.
Optionally, the PD protocol control chip is further configured to broadcast information when the first voltage is greater than a first threshold and the second voltage is greater than a second threshold, where the information is used to indicate an abnormality in charging and/or a cause of the abnormality in charging.
Optionally, the PD protocol control chip includes a control unit, a first comparator, a second comparator, an and gate, and a switch;
the non-inverting input end of the first comparator is connected with the first voltage and one end of the switch respectively, the inverting input end of the first comparator is connected with the voltage of the first threshold value, and the output end of the first comparator is connected with the first input end of the AND gate; the other end of the switch is grounded;
the non-inverting input end of the second comparator is connected with the second voltage, the inverting input end of the second comparator is connected with the voltage of the second threshold value, and the output end of the second comparator is connected with the second input end of the AND gate;
the control unit is connected with the output end of the AND gate, and controls the switch to be closed under the condition that the AND gate outputs a high-level signal is detected, so that the NMOS tube is opened; and outputting the first protection signal.
A second aspect of the invention provides a charging circuit comprising a flyback circuit and a charge management circuit as described in the first aspect, the flyback circuit being connected to the charge management circuit.
Optionally, in the secondary side of the flyback circuit, one end of a capacitor is connected with a drain electrode of an NMOS (N-channel metal oxide semiconductor) tube, a source electrode of the NMOS tube is connected with one end of a secondary coil, and the other end of the secondary coil is grounded with the other end of the capacitor; one end of the secondary coil and one end of the primary coil connected with the first switching device are the same-name ends.
Optionally, in the secondary side of the flyback circuit, one end of a capacitor is connected with one end of a secondary coil, the other end of the secondary coil is connected with a drain electrode of an NMOS tube, and both a source electrode of the NMOS tube and the other end of the capacitor are grounded; the other end of the secondary coil and one end of the primary coil connected with the first switching device are the same-name ends.
The invention has the positive progress effects that: if the first voltage between the drain electrode and the source electrode of the NMOS tube is larger than the first threshold value and the second voltage between the gate electrode and the source electrode of the NMOS tube is larger than the second threshold value, the first switching device on the primary side and the NMOS tube on the secondary side are conducted simultaneously, namely a shoot through phenomenon occurs, and the charging process is abnormal. At the moment, the shoot through protection is triggered, namely, the first switching device on the primary side is controlled to be disconnected by outputting a first protection signal, and the NMOS tube on the secondary side is controlled to be disconnected by outputting a second protection signal, so that the NMOS tube on the secondary side is protected from being damaged, and the reliability of the circuit is improved.
Drawings
Fig. 1 is a circuit diagram of a flyback circuit in the prior art.
Fig. 2 is a circuit diagram of another flyback circuit in the prior art.
Fig. 3 is a circuit connection diagram of a charge management circuit according to embodiment 1 of the present invention with a flyback circuit and a load, respectively.
Fig. 4 is a circuit connection diagram of a flyback circuit for charging a load through a second switching device according to embodiment 1 of the present invention.
Fig. 5 is a circuit connection diagram of another charge management circuit according to embodiment 1 of the present invention with a flyback circuit and a load, respectively.
Fig. 6 is a circuit connection diagram of a further charge management circuit according to embodiment 1 of the present invention with a flyback circuit and a load, respectively.
Fig. 7 is an internal structure diagram of a PD protocol control chip according to embodiment 1 of the present invention.
Fig. 8 is a schematic diagram of a flyback circuit according to embodiment 2 of the present invention.
Fig. 9 is a schematic diagram of another flyback circuit according to embodiment 2 of the present invention.
Detailed Description
The invention is further illustrated by means of the following examples, which are not intended to limit the scope of the invention.
Example 1
The present embodiment is implemented by a charge management circuit, as shown in fig. 3, where the charge management circuit is connected to a flyback circuit 100, the flyback circuit 100 is used for charging a load, the primary side of the transformer includes a first switching device connected in series with a primary winding, and the secondary side includes an NMOS transistor Q2.
The charge management circuit is used for detecting a first voltage V between the drain and the source of the NMOS transistor DS And a second voltage V between the gate and the source GS And at the first voltage V DS Greater than a first threshold and the second voltage V GS And outputting a first protection signal and a second protection signal under the condition that the first protection signal is larger than a second threshold value, wherein the first protection signal is used for indicating that the first switching device is disconnected, and the second protection signal is used for indicating that the NMOS tube Q2 is disconnected.
The first threshold is determined based on the voltage of the primary side when the NMOS tube is disconnected, the transformation ratio of the transformer and the output voltage of the flyback circuit. In a specific example, assuming that the voltage on the primary side is 200V, the transformation ratio of the transformer is 5:1, the output voltage of the flyback circuit is 20V, and the voltage on the secondary side can be determined to be 40V according to the voltage on the primary side and the transformation ratio of the transformer, the first threshold may be set to a value smaller than (40v+20v) and corresponding to a high level signal, for example, the first threshold may be set to 20V. The second threshold is determined based on the turn-on voltage of the NMOS transistor. In a specific implementation, the second threshold may be directly set to the turn-on voltage of the NMOS transistor, or may be set to be greater than the turn-on voltage of the NMOS transistor.
The first switching device may be a high-power MOS transistor. The load is a charged object and may be a mobile terminal such as a mobile phone or the like.
In a specific implementation, the charging management circuit may output a first protection signal to a main control circuit on a primary side of the flyback circuit, and the main control circuit controls the first switching device to be turned off based on the received first protection signal.
The principle of operation of the flyback circuit is described below in connection with fig. 3.
As shown in fig. 3, if the main control circuit controls the first switching device to be turned on, the primary coil current starts to rise, at this time, the first voltage between the drain and the source of the NMOS transistor is greater than the first threshold due to the relationship of the same-name ends of the secondary coil, the NMOS transistor Q2 is turned off, the transformer stores energy, and the load is supplied with energy by the output capacitor C1. If the main control circuit controls the first switching device to be disconnected, the induced voltage of the primary coil is reversed, at the moment, the second voltage between the grid electrode and the source electrode of the NMOS tube is larger than a second threshold value, the NMOS tube Q2 is conducted, energy in the transformer supplies power to a load through the NMOS tube Q2, meanwhile, the capacitor is charged, and the energy lost before is supplemented.
In this embodiment, if the first voltage between the drain and the source of the NMOS transistor is greater than the first threshold and the second voltage between the gate and the source of the NMOS transistor is greater than the second threshold, it is indicated that the first switching device on the primary side and the NMOS transistor on the secondary side are turned on simultaneously, i.e., a shoot through phenomenon occurs, and the charging process is abnormal. At the moment, the shoot through protection is triggered, namely, the first switching device on the primary side is controlled to be disconnected by outputting a first protection signal, and the NMOS tube on the secondary side is controlled to be disconnected by outputting a second protection signal, so that the NMOS tube on the secondary side is protected from being damaged, and the reliability of the circuit is improved.
In the event of such an abnormality in the charging process, the flyback circuit may be disconnected from the power supply path to the load in order to ensure that the load is not damaged. In an alternative embodiment, as shown in fig. 4, the flyback circuit is specifically configured to charge the load through a second switching device. The charge management circuit is further configured to control the second switching device to open if the first voltage is greater than a first threshold and the second voltage is greater than a second threshold. In an implementation manner, the second switching device may be a MOS transistor.
In an optional embodiment, the charge management circuit is connected to the load, and is configured to control the power output by the flyback circuit to the load, and reduce the power output to the load when the first voltage is less than a third threshold and the second voltage is less than a fourth threshold. In specific implementation, the charging management circuit can be connected with the load through a Type-C interface, and the power output by the flyback circuit to the load is controlled through a CC pin.
The third threshold is determined based on the conduction voltage drop of the built-in diode of the NMOS tube, and the fourth threshold is determined based on the starting voltage of the NMOS tube. In a specific implementation, the third threshold may be set directly as the conduction voltage drop of the diode built in the NMOS, or may be set to be smaller than the conduction voltage drop of the diode built in the NMOS. Similarly, the fourth threshold may be set directly to the turn-on voltage of the NMOS, or may be set smaller than the turn-on voltage of the NMOS.
In a specific implementation, a comparator and a logic gate circuit may be provided in the charge management circuit to detect whether the first voltage is less than a third threshold value and whether the second voltage is less than a fourth threshold value, and to reduce the power output to the load if the first voltage is less than the third threshold value and the second voltage is less than the fourth threshold value.
In this embodiment, if the first voltage between the drain and the source of the NMOS transistor is less than the third threshold and the second voltage between the gate and the source of the NMOS transistor is less than the fourth threshold, it is indicated that a large current flows from the source to the drain of the NMOS transistor, but the gate is not turned on, and a large current flows through the built-in diode of the NMOS transistor, so that a large loss may occur, and there is a possibility of damaging the NMOS transistor.
In an alternative embodiment, as shown in fig. 5, the secondary side of the flyback circuit further includes an SR control chip; the charge management circuit comprises a PD protocol control chip and is used for detecting a first voltage between the drain electrode and the source electrode of the NMOS tube and a second voltage between the grid electrode and the source electrode of the NMOS tube, and outputting the second protection signal to the SR control chip under the condition that the first voltage is larger than a first threshold value and the second voltage is larger than a second threshold value. The SR control chip is used for sending a control signal to the grid electrode of the NMOS tube and controlling the NMOS tube to be disconnected under the condition that the second protection signal is received.
In an alternative embodiment, as shown in fig. 6, the charge management circuit includes a PD protocol control chip, which is configured to send a control signal to the gate of the NMOS transistor, and detect a first voltage between the drain and the source of the NMOS transistor and a second voltage between the gate and the source of the NMOS transistor.
In the two embodiments, by adding the shootdown protection function to the PD protocol control chip, the system cost can be reduced, and no additional components or circuit board size is required.
It should be noted that the SR control chip or the PD protocol control chip may be configured according to the first voltage V between the drain and the source of the NMOS transistor DS And sending a control signal to the grid electrode of the NMOS tube. Specifically, if the first voltage V DS When the voltage is reduced to a certain value, for example, the voltage is reduced to below 2V, an opening control signal is sent to the grid electrode of the NMOS tube, so that the NMOS tube is opened. If the first voltage V DS Rising to a certain value, e.g. detecting a first voltage V DS From a negative few tens of mV zero crossing, a control signal for disconnection is sent to the gate of the NMOS transistor after a delay for a period of time, so that the NMOS transistor is disconnected.
In an optional implementation manner, the PD protocol control chip is further configured to broadcast information when the first voltage is greater than a first threshold and the second voltage is greater than a second threshold, where the information is used to indicate an abnormality in charging and/or a cause of the abnormality in charging. In this embodiment, the PD protocol control chip notifies the load of the abnormal charging through the broadcast information, and may also notify the reason that the abnormal charging occurs is that the first switching device on the primary side and the NMOS on the secondary side of the flyback circuit are turned on simultaneously, so that a shootdown through phenomenon occurs. After receiving the information broadcast by the PD protocol control chip, the load may perform a corresponding operation, such as opening a charging circuit inside the load, so as to protect the load from damage.
In an alternative embodiment, as shown in fig. 7, the PD protocol control chip includes a control unit, a first comparator U1, a second comparator U2, an and gate U3, and a switch K1.
The non-inverting input end of the first comparator U1 is respectively connected with the first voltage V GS And one end of the switch K1 is connected, and the inverting input end is connected with the first threshold V GS_TH The output end is connected with the first input end of the AND gate U3; the other end of the switch K1 is grounded.
The non-inverting input end of the second comparator U2 is connected with the second voltage V DS The inverting input terminal is connected with a second threshold V DS_TH The output terminal is connected to the second input terminal of the and gate U3.
The control unit is connected with the output end of the AND gate U3, and controls the switch K1 to be closed under the condition that the AND gate U3 outputs a high-level signal is detected, so that the NMOS tube is opened; and outputting the first protection signal.
In the present embodiment, if the first voltage V GS ＞V GS_TH The first comparator U1 outputs a high-level signal, if the second voltage V DS ＞V DS_TH The second comparator U2 outputs a high-level signal, if the first comparator U1 and the second comparator U2 output a high-level signal at the same time, the and gate U3 outputs a high-level signal, and the control unit outputs a second protection signal to control the switch K1 to be closed when detecting that the and gate U3 outputs a high-level signal, so that the NMOS tube is opened; and outputting the first protection signal to instruct the first switching device on the primary side of the flyback circuit to be turned off.
Example 2
The present embodiment provides a charging circuit including a flyback circuit and the charging management circuit of embodiment 1, the flyback circuit being connected with the charging management circuit.
The connection modes of NMOS tubes in the flyback circuit are as follows:
first kind: as shown in fig. 8, in the secondary side of the flyback circuit 100, one end of a capacitor C1 is connected to the drain of an NMOS transistor Q2, the source of the NMOS transistor Q2 is connected to one end of a secondary coil, and the other end of the secondary coil is grounded to the other end of the capacitor C1; one end of the secondary coil and one end of the primary coil connected with the first switching device are the same-name ends.
Second kind: as shown in fig. 9, in the secondary side of the flyback circuit 100, one end of the capacitor C1 is connected to one end of the secondary coil, the other end of the secondary coil is connected to the drain of the NMOS transistor Q2, and both the source of the NMOS transistor Q2 and the other end of the capacitor C1 are grounded; the other end of the secondary coil and one end of the primary coil connected with the first switching device are the same-name ends.
The charging circuit provided in this embodiment is used for charging a load, and if a first voltage between the drain electrode and the source electrode of the NMOS transistor on the secondary side of the flyback circuit is greater than a first threshold value and a second voltage between the gate electrode and the source electrode of the NMOS transistor is greater than a second threshold value, it is indicated that the first switching device on the primary side and the NMOS transistor on the secondary side are simultaneously turned on, that is, a shoot through phenomenon occurs, and the charging process is abnormal. At the moment, the shoot through protection is triggered, namely, the first switching device on the primary side is controlled to be disconnected by outputting a first protection signal, and the NMOS tube on the secondary side is controlled to be disconnected by outputting a second protection signal, so that the NMOS tube on the secondary side is protected from being damaged, and the reliability of the charging circuit is improved.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the principles and spirit of the invention, but such changes and modifications fall within the scope of the invention.
Claims (10)
1. A charging management circuit, wherein the charging management circuit is connected with a flyback circuit, the flyback circuit is used for charging a load, a primary side of a transformer comprises a first switching device connected with a primary coil in series, and a secondary side of the transformer comprises an NMOS tube;
the charging management circuit is used for detecting a first voltage between the drain electrode and the source electrode of the NMOS tube and a second voltage between the grid electrode and the source electrode of the NMOS tube, and outputting a first protection signal and a second protection signal when the first voltage is larger than a first threshold value and the second voltage is larger than a second threshold value, wherein the first protection signal is used for indicating that the first switching device is disconnected, and the second protection signal is used for indicating that the NMOS tube is disconnected;
the first threshold is determined based on the voltage of the primary side when the NMOS tube is disconnected, the transformation ratio of the transformer and the output voltage of the flyback circuit, and the second threshold is determined based on the starting voltage of the NMOS tube.
2. The charge management circuit of claim 1, wherein the flyback circuit is operable in particular to charge the load through a second switching device;
the charge management circuit is further configured to control the second switching device to open if the first voltage is greater than a first threshold and the second voltage is greater than a second threshold.
3. The charge management circuit of claim 1, wherein the charge management circuit is coupled to the load for controlling the power output by the flyback circuit to the load and reducing the power output to the load if the first voltage is less than a third threshold and the second voltage is less than a fourth threshold; the third threshold is determined based on the conduction voltage drop of the built-in diode of the NMOS tube, and the fourth threshold is determined based on the starting voltage of the NMOS tube.
4. The charge management circuit of claim 1, wherein the secondary side of the flyback circuit further comprises an SR control chip;
the charge management circuit comprises a PD protocol control chip, a first protection signal and a second protection signal, wherein the PD protocol control chip is used for detecting a first voltage between a drain electrode and a source electrode of the NMOS tube and a second voltage between a grid electrode and the source electrode, and outputting the second protection signal to the SR control chip under the condition that the first voltage is larger than a first threshold value and the second voltage is larger than a second threshold value;
the SR control chip is used for sending a control signal to the grid electrode of the NMOS tube and controlling the NMOS tube to be disconnected under the condition that the second protection signal is received.
5. The charge management circuit of claim 1, wherein the charge management circuit comprises a PD protocol control chip to send control signals to the gate of the NMOS transistor and to detect a first voltage between the drain and the source and a second voltage between the gate and the source of the NMOS transistor.
6. The charge management circuit of claim 4 or 5, wherein the PD protocol control chip is further configured to broadcast information indicating an abnormality in charging and/or a cause of the abnormality in charging if the first voltage is greater than a first threshold and the second voltage is greater than a second threshold.
7. The charge management circuit of claim 4 or 5, wherein the PD protocol control chip includes a control unit, a first comparator, a second comparator, an and gate, a switch;
the non-inverting input end of the first comparator is connected with the first voltage and one end of the switch respectively, the inverting input end of the first comparator is connected with the voltage of the first threshold value, and the output end of the first comparator is connected with the first input end of the AND gate; the other end of the switch is grounded;
the non-inverting input end of the second comparator is connected with the second voltage, the inverting input end of the second comparator is connected with the voltage of the second threshold value, and the output end of the second comparator is connected with the second input end of the AND gate;
the control unit is connected with the output end of the AND gate, and controls the switch to be closed under the condition that the AND gate outputs a high-level signal is detected, so that the NMOS tube is opened; and outputting the first protection signal.
8. A charging circuit comprising a flyback circuit and a charge management circuit according to any one of claims 1 to 7, the flyback circuit being connected to the charge management circuit.
9. The charging circuit of claim 8, wherein in the secondary side of the flyback circuit, one end of a capacitor is connected with a drain electrode of an NMOS tube, a source electrode of the NMOS tube is connected with one end of a secondary coil, and the other end of the secondary coil is grounded with the other end of the capacitor; one end of the secondary coil and one end of the primary coil connected with the first switching device are the same-name ends.
10. The charging circuit of claim 8, wherein in the secondary side of the flyback circuit, one end of a capacitor is connected with one end of a secondary coil, the other end of the secondary coil is connected with a drain electrode of an NMOS tube, and both a source electrode of the NMOS tube and the other end of the capacitor are grounded; the other end of the secondary coil and one end of the primary coil connected with the first switching device are the same-name ends.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210064044.5A CN114421566B (en) | 2022-01-20 | 2022-01-20 | Charging management circuit and charging circuit comprising same |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210064044.5A CN114421566B (en) | 2022-01-20 | 2022-01-20 | Charging management circuit and charging circuit comprising same |
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| CN114421566A CN114421566A (en) | 2022-04-29 |
| CN114421566B true CN114421566B (en) | 2023-06-20 |
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