CN114420675A

CN114420675A - Semiconductor package structure and manufacturing method thereof

Info

Publication number: CN114420675A
Application number: CN202210032182.5A
Authority: CN
Inventors: 黄煜哲; 赖律名
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2022-01-12
Filing date: 2022-01-12
Publication date: 2022-04-29

Abstract

According to the semiconductor packaging structure and the manufacturing method thereof, the design that the organic material cover body is matched with the metal shielding layer is utilized, and compared with the metal cover body, the density and the volume of the cover body can be effectively reduced, and the miniaturization of the product structure is facilitated. In addition, the first electronic component is coated by the barrier layer, so that ultrasonic waves emitted to the substrate by the first electronic component can be prevented from being reflected to the first electronic component, and the interference of signals received by the first electronic component can be avoided.

Description

Semiconductor package structure and manufacturing method thereof

Technical Field

The disclosure relates to the technical field of semiconductors, and particularly relates to a semiconductor packaging structure and a manufacturing method thereof.

Background

Piezoelectric ceramics are information functional ceramic materials capable of mutually converting mechanical energy and electric energy, namely, piezoelectric effect, and have dielectricity, elasticity and the like in addition to piezoelectricity, and are widely applied to medical imaging, acoustic sensors, acoustic transducers, ultrasonic motors and the like. The piezoelectric ceramic is manufactured by utilizing the piezoelectric effect that the material causes the relative displacement of the centers of positive and negative charges in the material under the action of mechanical stress to generate polarization, so that bound charges with opposite signs appear on the surfaces of two ends of the material, and the piezoelectric ceramic has sensitive characteristics.

In some cases, the package structure of the piezoelectric ceramic element is mainly formed by covering the piezoelectric ceramic element with a metal top cover, a printed circuit board and a connector. The package design is limited by the size and shape design of the metal top cover, which not only hinders the miniaturization of the product, but also cannot effectively isolate the influence of vibration or package structure stress, thereby failing to reduce the interference of ultrasonic frequency.

Disclosure of Invention

The present disclosure provides a semiconductor package structure and a method of manufacturing the same.

In a first aspect, the present disclosure provides a semiconductor package structure, including:

a substrate;

the cover body is arranged on the substrate;

the metal shielding layer and the first electronic component are arranged on the inner surface of the cover body, the first electronic component is electrically connected with the metal shielding layer through a first electric connecting piece, and the metal shielding layer is electrically connected with the substrate through a second electric connecting piece;

and the barrier layer coats the first electronic component.

In some alternative embodiments, the first electronic component is a piezoelectric component having two electrodes electrically connected to the metallic shield layer by the first electrical connections, the first electrical connections being separated by a non-conductive layer.

In some alternative embodiments, the first electrical connector is a conductive glue and the non-conductive layer is a non-conductive glue.

In some optional embodiments, the second electrical connection is a conductive adhesive or a combination of a conductive adhesive and a conductive wire, and the second electrical connection is for providing a vertical conductive path between the metal shielding layer and the substrate.

In some optional embodiments, further comprising:

and the bonding layer is used for bonding the substrate and the cover body.

In some alternative embodiments, the adhesive layer is a non-conductive glue.

In some alternative embodiments, the conductive paste and the non-conductive paste have a low elastic modulus to prevent vibration interference of the piezoelectric assembly from being transferred to the substrate.

In some alternative embodiments, the conductive paste has a low elastic modulus to prevent vibration interference of the piezoelectric assembly from being transferred to the substrate.

In some optional embodiments, the blocking layer is an elastomer material, and the blocking layer is used for blocking the ultrasonic waves emitted by the piezoelectric component to the substrate from being reflected to the piezoelectric component.

In some optional embodiments, further comprising:

the second electronic assembly is arranged on the substrate and is electrically connected with the first electronic assembly through the substrate and the first electric connector.

In some alternative embodiments, the substrate has through holes for avoiding the popcorn effect.

In some optional embodiments, further comprising:

and the electromagnetic shielding layer is arranged on the outer surface of the cover body.

In some alternative embodiments, the cover is an organic material.

In a second aspect, the present disclosure provides a method for manufacturing a semiconductor package structure, including:

forming a metal shielding layer on the inner surface of the cover body;

sequentially forming a first electric connector and a first electronic component on the metal shielding layer so that the first electronic component is electrically connected with the metal shielding layer through the first electric connector;

and forming a second electric connecting piece, and arranging the cover body on the substrate so that the metal shielding layer is electrically connected with the substrate through the second electric connecting piece.

In some optional embodiments, after the sequentially forming the first electrical connector and the first electronic component on the metal shielding layer, further comprising:

forming a barrier layer covering the first electronic component.

In some optional embodiments, before the disposing the cover on the substrate, further comprising:

arranging an adhesive layer on the substrate or the cover body; and

the lid is arranged on the substrate, and the method comprises the following steps:

and adhering the cover body to the substrate by using the adhesive layer.

In some alternative embodiments, the adhesive layer is a non-conductive glue.

In some optional embodiments, further comprising:

an electromagnetic shielding layer is formed on an outer surface of the cover.

Drawings

Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

fig. 1 is a first structural schematic diagram of a semiconductor package structure according to an embodiment of the present disclosure;

fig. 2 is a second schematic structural diagram of a semiconductor package structure according to an embodiment of the present disclosure;

fig. 3 to 11 are schematic structural views in the manufacturing process of the semiconductor package structure according to the embodiment of the present disclosure.

Description of the symbols:

1-substrate, 101-through hole, 2-cover, 3-metal shielding layer, 4-first electronic component, 41-electrode, 5-first electric connecting piece, 6-second electric connecting piece, 61-conductive adhesive, 62-conducting wire, 7-barrier layer, 8-non-conductive layer, 9-second electronic component, 10-adhesive layer, 11-electromagnetic shielding layer, 12-first carrier, and 13-second carrier.

Detailed Description

The following description of the embodiments of the present disclosure will be provided in conjunction with the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems and effects of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.

It should be noted that the structures, proportions, and dimensions shown in the drawings and described in the specification are for the understanding and reading of the present disclosure, and are not intended to limit the conditions under which the present disclosure can be implemented, so they are not technically significant, and any modifications of the structures, changes in the proportions and adjustments of the dimensions should be made without affecting the efficacy and attainment of the same. In addition, the terms "above", "first", "second" and "a" as used herein are for the sake of clarity only, and are not intended to limit the scope of the present disclosure, and changes or modifications of the relative relationship may be made without substantial changes in the technical content.

It should be readily understood that the meaning of "in.. on," "over,", and "above" in this disclosure should be interpreted in the broadest sense such that "in.. on" not only means "directly on something," but also means "on something" including an intermediate member or layer between the two.

Furthermore, spatially relative terms, such as "below," "lower," "over," "upper," and the like, may be used in this disclosure to describe one element or component's relationship to another element or component as illustrated in the figures for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 ° or at other orientations) and the spatially relative descriptors used in this disclosure interpreted accordingly as such.

In addition, the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Fig. 1 is a first structural schematic diagram of a semiconductor package structure according to an embodiment of the present disclosure. As shown in fig. 1, the semiconductor package structure includes a substrate 1, a lid 2, a metal shielding layer 3, a first electronic component 4, and a barrier layer 7. The lid 2 is provided on the substrate 1. The metallic shield layer 3 and the first electronic component 4 are provided on the inner surface of the lid body 2. The first electronic component 4 is electrically connected to the metal shielding layer 3 via a first electrical connector 5. The metal shielding layer 3 is electrically connected to the substrate 1 via a second electrical connection 6.

In the present embodiment, the metal shielding layer 3 may be a conductive material of a metal or a metal alloy, and the metal may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof. The metal shielding layer 3 may be used not only to provide an electrical connection path between the first electronic component 4 and the substrate 1, but also for electromagnetic shielding.

In one embodiment, the cover 2 may be an organic material, and may be a resin material such as ABF resin, BT (Bismaleimide Triazine) resin, glass cloth based Epoxy resin (FR4, FR5), PI resin, liquid crystal polymer resin (LCP), or Epoxy resin (Epoxy). Therefore, the cover body 2 made of organic materials can be used together with the metal shielding layer 3 to replace the metal cover body 2, and the density and the volume of the cover body 2 can be effectively reduced. And the size and shape design of the sleeve limited by the metal cover body 2 can be avoided, and the size miniaturization can be realized conveniently.

In the present embodiment, the first electronic component 4 may be an active component and a passive component. The active elements may be, for example, various chips (application specific integrated circuit chips, high bandwidth memory chips, power management chips, logic function chips, memory chips, communication chips, microprocessor chips, graphics chips). The passive elements may be, for example, capacitors, resistors, inductors, and the like.

In one embodiment, the first electronic component 4 may be a piezoelectric component. The piezoelectric assembly may have two electrodes 41. The piezoelectric assembly may be used for transmission and reception of ultrasonic and infrasonic signals. Ultrasonic signals emitted by the piezoelectric component can penetrate through the cover body 2, are reflected after encountering an obstacle and then are received by the piezoelectric component, and then obstacle information can be calculated according to the reflected signals, so that the piezoelectric component is suitable for a space obstacle detection scene.

In this embodiment, the barrier layer 7 may be a damping material, which may be used for vibration and noise control. In yet another embodiment, the barrier layer 7 may be an elastomeric material, which may be, for example, rubber, silicone, or the like. The barrier layer 7 may have vibration-absorbing properties for blocking the ultrasonic waves emitted from the piezoelectric element to the substrate 1 from being reflected to the piezoelectric element. Therefore, the ultrasonic waves emitted downwards by the piezoelectric component can be reduced from hitting the substrate 1 for reflection, and the interference of the piezoelectric component for receiving signals can be avoided.

In one embodiment, the two electrodes 41 of the piezoelectric assembly may be electrically connected to the metallic shielding layer 3 by a first electrical connection 5. The first electrical connection members 5 may be solder balls, Ball Grid Array (BGA) balls, controlled collapse chip connection (C4) bumps, or micro bumps. In yet another embodiment, the first electrical connector 5 may be a conductive paste, which may have a conductive material such as silver powder. The conductive glue on the two electrodes 41 may be separated by a non-conductive layer 8. The non-conductive layer 8 may be a non-conductive glue. Here, the conductive adhesive may not only serve as an electrical connection path between the first electronic component 4 and the metal shielding layer 3, but also may bond and fix the first electronic component 4 to the inner surface of the cover 2. The non-conductive adhesive can be used to electrically isolate the first electrical connector 5, and can also be used to adhesively fix the first electronic component 4 to the surface of the cover 2.

In one embodiment, the substrate 1 may have a through hole 101. The through-holes 101 may be used to avoid the popcorn effect and prevent cracks from occurring inside the substrate 1.

In one embodiment, the semiconductor package structure may further include an electromagnetic shielding layer 11. The electromagnetic shield layer 11 may be provided on the outer surface of the lid body 2.

In one embodiment, the semiconductor package structure may further include a second electronic component 9. The second electronic component 9 may be provided on the substrate 1. The second electronic component 9 may be electrically connected to the first electronic component 4 via the substrate 1, the first electrical connector 5, the metallic shielding layer 3 and the first electrical connector 5. The second electronic component 9 may be an active component and a passive component.

In the present embodiment, the second electrical connector 6 may be for providing a vertical conductive path between the metallic shield layer 3 and the substrate 1. The second electrical connections 6 may be solder balls, Ball Grid Array (BGA) balls, controlled collapse chip connection (C4) bumps, or micro bumps. In one embodiment, as shown in fig. 1, the second electrical connection 6 may be a conductive glue. The conductive paste may have a low elastic modulus, and may serve as a buffer to absorb vibration and stress, thereby preventing vibration interference of the piezoelectric element from being transmitted to the substrate 1. The influence of vibration on the semiconductor packaging structure can be improved, the influence of packaging stress can be reduced, ultrasonic interference can be avoided, and ultrasonic sensing characteristics and signal quality can be improved. In yet another embodiment, as shown in fig. 2, the second electrical connector 6 may be a combination of a conductive glue 61 and a wire 62. Specifically, the metal shielding layer 3 and the substrate 1 can be electrically connected by using the vertical wire 62 and a small amount of conductive adhesive 61, and since the diameter of the vertical wire 62 can be selected and has a small size, the contact area with the substrate 1 is small, and thus the influence of vibration can be isolated as much as possible.

In one embodiment, the semiconductor package structure may further include an adhesive layer 10. The adhesive layer 10 may bond the substrate 1 and the cover 2 to complete the seal of the unitary structure. In yet another embodiment, the adhesive layer 10 may employ a non-conductive adhesive. The non-conductive adhesive may have a low elastic modulus, and may serve as a buffer to absorb vibration and stress, thereby preventing vibration interference of the piezoelectric element from being transmitted to the substrate 1. The influence of vibration on the semiconductor packaging structure can be improved, the influence of packaging stress can be reduced, ultrasonic interference can be avoided, and ultrasonic sensing characteristics and signal quality can be improved.

The semiconductor packaging structure provided by the disclosure utilizes the design of the organic material cover body 2 matched with the metal shielding layer 3, and compared with a metal cover body, the density and the volume of the cover body can be effectively reduced, thereby being beneficial to the miniaturization of the product structure. In addition, the barrier layer 7 is used to cover the first electronic component 4, so that the ultrasonic waves emitted from the first electronic component 4 to the substrate 1 can be prevented from being reflected to the first electronic component 4, and the interference of the first electronic component 4 in receiving signals can be avoided.

As shown in fig. 3, the cover 2 is first placed on the first carrier 12, and then the metal shielding layer 3 is formed on the inner surface of the cover 2. In one embodiment, an electromagnetic shielding layer 11 may be further formed on the outer surface of the cover 2. The metal shield layer 3 and the electromagnetic shield layer 11 may be formed by, for example, plating or the like.

As shown in fig. 4, a first electrical connection 5 is formed on the metallic shield layer 3.

As shown in fig. 5, the first electronic component 4 is placed on the first electrical connector 5, so that the first electronic component 4 is electrically connected with the metal shielding layer 3 through the first electrical connector 5. In one embodiment, the first electronic component 4 may be a piezoelectric component. The piezoelectric assembly may have two electrodes 41. The two electrodes 41 may be electrically connected to the metallic shield layer 3 by a first electrical connection 5. A non-conductive layer 8 separation may be formed between the first electrical connections 5 on the two electrodes 41. In yet another embodiment, the non-conductive layer 8 may be a non-conductive glue. In another embodiment, the first electrical connector 5 may be a conductive adhesive, which not only serves as an electrical connection path between the first electronic component 4 and the metal shielding layer 3, but also fixes the first electronic component 4 in the cover 2, and further can be used for electromagnetic shielding.

As shown in fig. 6, a barrier layer 7 is formed which encapsulates the first electronic component 4.

As shown in fig. 7, the substrate 1 is placed on the second carrier 13. A second electronic component 9 is placed on the substrate 1. An adhesive layer 10 and a second electrical connector 6 (conductive paste) are formed on the substrate 1. Alternatively, the adhesive layer 10 may be formed on the lid body 2. A second electrical connection 6 (conductive glue) is formed on the metallic shield layer 3. In one embodiment, a through hole 101 may also be formed on the substrate 1.

As shown in fig. 8, the lid 2 is provided on the substrate 1, and the lid 2 is bonded to the substrate 1 with the adhesive layer 10. The metallic shield layer 3 may be electrically connected to the substrate 1 by a second electrical connection 6 (conductive glue). And obtaining the semiconductor packaging structure.

As shown in fig. 9, an adhesive layer 10 is formed on the lid body 2. A conductive paste 61 is formed on the metal shield layer 3. In one embodiment, the adhesive layer 10 may be a non-conductive adhesive. In yet another embodiment, the conductive glue 61 and the non-conductive glue have a low elastic modulus to avoid that vibrational disturbances of the piezoelectric assembly are transferred to the substrate 1.

As shown in fig. 10, the substrate 1 is placed on the second carrier 13. A second electronic component 9 is placed on the substrate 1. The wires 62 are punched onto the substrate 1. In one embodiment, a through hole 101 may also be formed on the substrate 1.

As shown in fig. 11, the lid 2 is provided on the substrate 1, and the lid 2 is bonded to the substrate 1 with the adhesive layer 10. The wires 62 are connected with the conductive glue 61 to form the second electrical connection 6. The metallic shield layer 3 may be electrically connected to the substrate 1 by a second electrical connection 6. And obtaining the semiconductor packaging structure.

The method for manufacturing the semiconductor package structure in this embodiment can achieve similar technical effects to the semiconductor structure described above, and will not be described herein again. In addition, the standardization and automation of the packaging process of the piezoelectric component are realized by using basic packaging processes (such as dispensing, routing, die bonding and the like), which is beneficial to reducing the production cost.

While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction in the present disclosure and the actual device due to variables in the manufacturing process and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed in this disclosure have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated in the present disclosure, the order and grouping of the operations is not a limitation of the present disclosure.

Claims

1. A semiconductor package structure, comprising:

a substrate;

the cover body is arranged on the substrate;

and the barrier layer coats the first electronic component.

2. The semiconductor package structure of claim 1, wherein the first electronic component is a piezoelectric component having two electrodes electrically connected to the metallic shield layer by the first electrical connections separated by a non-conductive layer.

3. The semiconductor package structure of claim 2, wherein the first electrical connection is a conductive glue and the non-conductive layer is a non-conductive glue.

4. The semiconductor package structure of claim 2, wherein the second electrical connection is a conductive paste or a combination of a conductive paste and a conductive wire, the second electrical connection being for providing a vertical conductive path between the metal shielding layer and the substrate.

5. The semiconductor package structure of claim 4, further comprising:

and the bonding layer is used for bonding the substrate and the cover body.

6. The semiconductor package structure of claim 5, wherein the adhesive layer is a non-conductive glue, the conductive glue and the non-conductive glue having a low elastic modulus to avoid vibration interference of the piezoelectric component from being transferred to the substrate.

7. The semiconductor package according to claim 2, wherein the blocking layer is an elastomer material, and the blocking layer is used for blocking ultrasonic waves emitted from the piezoelectric element to the substrate from being reflected to the piezoelectric element.

8. The semiconductor package structure of claim 1, further comprising:

9. The semiconductor package structure of claim 1, wherein the substrate has a through hole for avoiding a popcorn effect.

10. The semiconductor package structure of claim 1, further comprising: