CN114420634A - Preparation method of semiconductor device - Google Patents
Preparation method of semiconductor device Download PDFInfo
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- CN114420634A CN114420634A CN202111545321.6A CN202111545321A CN114420634A CN 114420634 A CN114420634 A CN 114420634A CN 202111545321 A CN202111545321 A CN 202111545321A CN 114420634 A CN114420634 A CN 114420634A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 90
- 238000000034 method Methods 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 238000005530 etching Methods 0.000 claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 6
- 238000005137 deposition process Methods 0.000 abstract description 2
- 238000000151 deposition Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000007517 polishing process Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000000427 thin-film deposition Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a preparation method of a semiconductor device, which comprises the following steps: providing a substrate, wherein a grid structure is formed on the substrate, and an active region and a drain region are formed in the substrate on two sides of the grid structure; forming a first dielectric layer on the substrate, wherein the first dielectric layer covers the substrate and the grid structure; forming a top metal layer on the first dielectric layer, wherein the top metal layer is electrically connected with the gate structure, the source region and the drain region; forming a second dielectric layer on the first dielectric layer and the top metal layer in a conformal manner; and etching part of the thickness of the second dielectric layer above the top metal layer, performing a planarization process on the second dielectric layer, and homogenizing the shape of the second dielectric layer through the etching process so as to grind the second dielectric layer at a high speed, thereby avoiding plasma damage and electric leakage caused by the collection of free charges generated in the plasma deposition process by the top metal layer.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a preparation method of a semiconductor device.
Background
In the fabrication of semiconductor devices, it is usually necessary to deposit a thin film on a substrate to form a desired device, such as depositing a metal thin film as a metal layer on the substrate, depositing a dielectric layer on the substrate, etc., in order to improve the structural compactness of the deposited thin film, a plasma process and a chemical vapor deposition process are usually combined, such as Plasma Enhanced Chemical Vapor Deposition (PECVD) or High Density Plasma Chemical Vapor Deposition (HDPCVD) for thin film deposition.
The existing thin film deposition technology comprises the following steps: placing a substrate on an electrostatic chuck in a deposition chamber; introducing gas to be reacted into the deposition chamber, starting a radio frequency source, and heating the gas to be reacted by adopting low radio frequency power; and finally, ionizing the gas to be reacted by adopting high radio frequency power to form plasma, and depositing on the substrate to form a film.
Theoretically, the plasma is totally electrically neutral to the outside, that is, positive ions and negative ions in the plasma are equal, but actually, positive ions and negative ions entering the substrate are not equal in a local area, and a large amount of free charges are generated on the surface of the substrate. When the metal layer is formed, the metal layer can collect free charges on the substrate and transfer a large amount of charges to the grid structure, leakage current is formed in the grid oxide layer below the grid structure, and when the accumulated charges reach a certain amount, the leakage current can be discharged in the grid oxide layer to generate plasma damage to the grid oxide layer, so that the breakdown resistance of the semiconductor device is reduced. With the continuous reduction of the feature size of semiconductor devices in recent years, the thickness of a gate oxide layer is also continuously reduced, the electric leakage phenomenon caused by plasma damage is more serious, and even the devices are scrapped.
Disclosure of Invention
The invention aims to provide a preparation method of a semiconductor device, which can reduce plasma damage and electric leakage of the semiconductor device.
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising:
providing a substrate, wherein a grid structure is formed on the substrate, and an active region and a drain region are formed in the substrate on two sides of the grid structure;
forming a first dielectric layer on the substrate, wherein the first dielectric layer covers the substrate and the grid structure;
forming a top metal layer on the first dielectric layer, wherein the top metal layer is electrically connected with the gate structure, the source region and the drain region;
forming a second dielectric layer on the first dielectric layer and the top metal layer in a conformal manner;
etching part of the thickness of the second dielectric layer above the top metal layer;
and carrying out a planarization process on the second dielectric layer to thin the second dielectric layer above the top metal layer.
Optionally, after the second dielectric layer is subjected to the planarization process, the thickness of the second dielectric layer above the top metal layer is 1 μm to 1.3 μm.
Optionally, a portion of the width of the second dielectric layer above the top metal layer is etched, and at least one protrusion is formed in the second dielectric layer above the top metal layer.
Optionally, the second dielectric layer is planarized until the protrusion is removed.
Optionally, after removing the protruding portion, a planarization process is continuously performed on the second dielectric layer to remove a portion of the thickness of the second dielectric layer remaining above the top metal layer.
Optionally, etching is performed to remove the entire width of the second dielectric layer above the top metal layer.
Optionally, the thickness of the second dielectric layer is greater than that of the top metal layer.
Optionally, the thickness difference between the second dielectric layer and the top metal layer is greater than 1 μm.
Optionally, after the planarization process is performed, the height of the top surface of the second dielectric layer on the top metal layer is greater than or equal to the height of the top surface of the second dielectric layer on the first dielectric layer.
Optionally, the second dielectric layer is formed by a plasma enhanced chemical vapor deposition process or a high density plasma chemical vapor deposition process.
The invention provides a preparation method of a semiconductor device, which comprises the following steps: providing a substrate, wherein a grid structure is formed on the substrate, and an active region and a drain region are formed in the substrate on two sides of the grid structure; forming a first dielectric layer on the substrate, wherein the first dielectric layer covers the substrate and the grid structure; forming a top metal layer on the first dielectric layer, wherein the top metal layer is electrically connected with the gate structure, the source region and the drain region; forming a second dielectric layer on the first dielectric layer and the top metal layer in a conformal manner; etching part of the thickness of the second medium layer above the top metal layer, and carrying out a planarization process on the second medium layer to thin the second medium layer above the top metal layer, wherein the shape of the second medium layer is uniform through the etching process, the planarization speed of the second medium layer is uniform, and the problems of plasma damage and electric leakage caused by the fact that the top metal layer collects the free charges on the substrate are avoided.
Drawings
FIGS. 1 to 3 are schematic structural diagrams corresponding to respective steps of a method for manufacturing a semiconductor device;
FIG. 4 is a flow chart of a method for fabricating a semiconductor device according to the present invention;
fig. 5 to 9 are schematic structural diagrams corresponding to respective steps of a method for manufacturing a semiconductor device according to the present invention;
wherein the drawings are described as follows:
100. 200-a substrate; 102. 202-a transistor structure; 103a, 203 a-source; 103b, 203 b-drain; 104. 204-metal interconnect layer; 105-a first dielectric layer; 106, 206-top metal layer; 108, 208-a second dielectric layer; 210-boss.
Detailed Description
Fig. 1 to 3 are schematic structural diagrams corresponding to respective steps of a manufacturing method of a semiconductor device, and as shown in fig. 1, a substrate 100 is provided, a plurality of gate structures 102 arranged in an array are formed on the substrate 100, and an active region 103a and a drain region 103b are formed in the substrate 100 on two sides of the gate structures 102; forming a first dielectric layer 105 on the substrate 100, wherein the first dielectric layer 105 covers the substrate 100 and the gate structures 102, a plurality of metal interconnection layers 104 are stacked in the first dielectric layer 105, and the metal interconnection layers 104 are electrically connected with at least one of the gate structures 102, the source region 103a or the drain region 103 b.
As shown in fig. 2, a patterned top metal layer 106 is formed on the first dielectric layer 105, and the top metal layer 106 is electrically connected to the gate structure 102, the source region 103a and the drain region 103b through the metal interconnection layer 104; a second dielectric layer 108 is formed on the top metal layer 106 in a conformal manner, and the surface of the second dielectric layer 108 formed in a conformal manner is fluctuated due to the pattern of the top metal layer 106.
As shown in fig. 3, a planarization process, which may be a chemical mechanical polishing process, is performed on the second dielectric layer 108 to thin the second dielectric layer 108 above the top metal layer 106. When the planarization process is performed on the second dielectric layer 108, the planarization speed is not uniform at all positions of the surface of the second dielectric layer 108 due to the undulation of the surface of the second dielectric layer 108. When the thickness of some regions of the second dielectric layer 108 reaches H1, the thickness of other regions of the second dielectric layer 108 may reach H2, and the thickness H2 is greater than the thickness H1, and typically when the thickness H1 is 1.4 μm, the thickness H2 is 2.7 μm. If the second dielectric layer 108 is chemically and mechanically polished until the thickness of the region with the thickness H2 of the second dielectric layer 108 is reduced to H1, the region with the thickness H1 of the second dielectric layer 108 is continuously thinned to a thickness lower than H1 during the polishing process, and even the top metal layer 106 is exposed. In the deposition process of the first dielectric layer 105 and the second dielectric layer 108, a large amount of free charges are formed on the surface of the device, if the second dielectric layer 108 on the top metal layer 106 is too thin, the top metal layer 108 will collect a large amount of free charges and gather the free charges in the gate structure 102, and leakage current is formed, and when the accumulated free charges reach a certain amount, the leakage current will generate discharge to generate plasma damage to the gate structure 102 and the first dielectric layer 105, thereby affecting the performance of the whole semiconductor device.
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the following, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances. Similarly, if the method described herein comprises a series of steps, and the steps presented herein are not necessarily the only order in which the steps may be performed, some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
Fig. 4 is a flowchart of a method for manufacturing a semiconductor device according to this embodiment, and as shown in fig. 4, the present invention provides a method for manufacturing a semiconductor device, including:
step S1: providing a substrate, wherein a grid structure is formed on the substrate, and an active region and a drain region are formed in the substrate on two sides of the grid structure;
step S2: forming a first dielectric layer on the substrate, wherein the first dielectric layer covers the substrate and the grid structure;
step S3: forming a top metal layer on the first dielectric layer, wherein the top metal layer is electrically connected with the gate structure, the source region and the drain region;
step S4: forming a second dielectric layer on the first dielectric layer and the top metal layer in a conformal manner;
step S5: etching part of the thickness of the second dielectric layer above the top metal layer;
step S6: and carrying out a planarization process on the second dielectric layer to thin the second dielectric layer above the top metal layer.
Fig. 5 to 9 are schematic structural diagrams corresponding to respective steps of a method for manufacturing a semiconductor device according to the present invention, and the method for manufacturing a semiconductor device according to the present embodiment is described in more detail below with reference to fig. 5 to 9, in which an alternative embodiment of the present invention is illustrated.
As shown in fig. 5, a substrate 200 is provided, a plurality of gate structures 202 are formed on the substrate 200 in an array, and an ion implantation process is performed on two sides of the substrate 200 to form a source region 203a and a drain region 203b on two sides of the substrate 200.
Further, a first dielectric layer 205 is formed on the substrate 200, the first dielectric layer 205 covers the substrate 200 and the gate structures 202, a plurality of metal interconnection layers 204 are stacked in the first dielectric layer 205, and the metal interconnection layers 204 are electrically connected to at least one of the gate structures 202, the source region 203a, or the drain region 203 b. For ease of illustration, the metal interconnect layer 204 is not shown in the following figures.
The first dielectric layer 205 may be silicon oxide or silicon nitride, and the first dielectric layer 205 is formed by a plasma enhanced chemical vapor deposition process or a high density plasma chemical vapor deposition process.
As shown in fig. 6, a metal layer is formed on the first dielectric layer 205, and the metal layer is etched to form a patterned top metal layer 206, wherein the top metal layer 206 is electrically connected to the gate structure 202, the source region 203a, and the drain region 203 b.
As shown in fig. 7, a second dielectric layer 208 is formed on the top metal layer 206 in a conformal manner, and the surface of the second dielectric layer 208 formed in a conformal manner has an undulation due to the difference in the pattern of the top metal layer 206.
The second dielectric layer 208 completely covers the top surface and the sidewall of the top metal layer 206, the thickness of the second dielectric layer 208 is greater than the thickness of the top metal layer 208, and the height of the top surface of the second dielectric layer 208 above the first dielectric layer 205 is lower than the height of the top surface of the top metal layer 206, so as to prevent the top metal layer 206 from being exposed.
In this embodiment, the thickness of the top metal layer 206 is 3.5 μm to 4.5 μm, the thickness of the second dielectric layer 208 is 4.5 μm to 5.5 μm, and the thickness difference between the second dielectric layer 208 and the top metal layer 206 is greater than 1 μm.
The second dielectric layer 208 may be silicon oxide or silicon nitride, and the second dielectric layer 208 is formed by a plasma enhanced chemical vapor deposition process or a high density plasma chemical vapor deposition process.
As shown in fig. 8, a photoresist layer is spin-coated on the second dielectric layer 208, the second dielectric layer 208 is etched by using the patterned photoresist layer as a mask, the patterned photoresist layer covers the second dielectric layer 208 above the first dielectric layer 205 and extends to cover a part of the second dielectric layer 208 above the top metal layer 206, a part of the width of the second dielectric layer 208 above the top metal layer 206 is etched, and at least one protrusion 210 is formed on the second dielectric layer 208 above the top metal layer 206.
In the embodiment, the protruding portions 210 are formed on both sides of the pattern of the second dielectric layer 208 above the top metal layer 206, but the number of the protruding portions 210 is not limited in the present invention, but the shapes of the protruding portions 210 are ensured to be the same, so as to ensure that the polishing speed is the same when the planarization process is performed on the protruding portions 210 subsequently.
The thickness H3 of the second dielectric layer 208 above the etched top metal layer 206 is 1.3 μm to 1.5 μm.
And finally ashing to remove the photoresist layer.
As shown in fig. 9, a planarization process is performed on the second dielectric layer 208 until the protrusion 210 is removed, and the planarization process is continued to be performed on the second dielectric layer 208 to remove a portion of the thickness of the second dielectric layer 208 above the top metal layer 206, wherein the planarization process may be a chemical mechanical polishing process.
After the second dielectric layer 208 is subjected to the planarization process, the thickness H4 of the second dielectric layer 208 is 1 μm to 1.3 μm. At this time, the thicknesses of the second dielectric layers 208 are all H4, and the second dielectric layers 208 completely cover the top metal layer 206, so as to prevent the top metal layer 206 from collecting the free charges generated during the pecvd or hdp cvd process.
With continued reference to fig. 8 and 9, in an alternative embodiment, the second dielectric layer 208 may be etched to remove the entire width of the second dielectric layer 208 over the top metal layer 206, and then the second dielectric layer 208 may be planarized to achieve the thickness H4 of the second dielectric layer 208 over the top metal layer 206.
In summary, the present invention provides a method for manufacturing a semiconductor device, including: providing a substrate 200, wherein a gate structure 202 is formed on the substrate 200, and an active region 203a and a drain region 203b are formed in the substrate 200 at two sides of the gate structure 202; forming a first dielectric layer 205 on the substrate 200, wherein the first dielectric layer 205 covers the substrate 200 and the gate structure 2022; forming a top metal layer 206 on the first dielectric 205 layer, wherein the top metal layer 206 is electrically connected to the gate structure 202, the source region 203a and the drain region 203 b; forming a second dielectric layer 208 on the first dielectric layer 205 and the top metal layer 206; etching part of the thickness of the second dielectric layer 208 above the top metal layer 206, performing a planarization process on the second dielectric layer 208 to thin the second dielectric layer 208 above the top metal layer 206, and homogenizing the shape of the second dielectric layer 208 through the etching process, thereby homogenizing the planarization speed of the second dielectric layer 208 and avoiding plasma damage and electric leakage problems caused by the collection of the top metal layer 206 on the substrate 200 by the free charges.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate, wherein a grid structure is formed on the substrate, and an active region and a drain region are formed in the substrate on two sides of the grid structure;
forming a first dielectric layer on the substrate, wherein the first dielectric layer covers the substrate and the grid structure;
forming a top metal layer on the first dielectric layer, wherein the top metal layer is electrically connected with the gate structure, the source region and the drain region;
forming a second dielectric layer on the first dielectric layer and the top metal layer in a conformal manner;
etching part of the thickness of the second dielectric layer above the top metal layer;
and carrying out a planarization process on the second dielectric layer to thin the second dielectric layer above the top metal layer.
2. The method of claim 1, wherein the second dielectric layer over the top metal layer has a thickness of 1 μm to 1.3 μm after the planarization process is performed on the second dielectric layer.
3. The method of claim 1, wherein a portion of the width of the second dielectric layer over the top metal layer is etched to form at least one protrusion in the second dielectric layer over the top metal layer.
4. The method of claim 3, wherein the second dielectric layer is planarized until the raised portions are removed.
5. The method of claim 4, wherein after removing the protrusion, the planarization process is continued on the second dielectric layer to remove a portion of the thickness of the second dielectric layer remaining above the top metal layer.
6. The method of claim 1, wherein etching removes the entire width of the second dielectric layer over the top metal layer.
7. The method of claim 1, wherein a thickness of the second dielectric layer is greater than a thickness of the top metal layer.
8. The method of claim 7, wherein a difference in thickness between the second dielectric layer and the top metal layer is greater than 1 μm.
9. The method of claim 7, wherein after the planarization process is performed, a height of a top surface of the second dielectric layer above the top metal layer is greater than or equal to a height of a top surface of the second dielectric layer above the first dielectric layer.
10. The method of claim 1, wherein the second dielectric layer is formed by a plasma enhanced chemical vapor deposition process or a high density plasma chemical vapor deposition process.
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| CN202111545321.6A CN114420634A (en) | 2021-12-16 | 2021-12-16 | Preparation method of semiconductor device |
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| CN202111545321.6A CN114420634A (en) | 2021-12-16 | 2021-12-16 | Preparation method of semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114743931A (en) * | 2022-06-14 | 2022-07-12 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor integrated device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114743931A (en) * | 2022-06-14 | 2022-07-12 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor integrated device |
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