CN114416618B - Three-dimensional chip and inter-chip communication method thereof - Google Patents
Three-dimensional chip and inter-chip communication method thereof Download PDFInfo
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- CN114416618B CN114416618B CN202111553453.3A CN202111553453A CN114416618B CN 114416618 B CN114416618 B CN 114416618B CN 202111553453 A CN202111553453 A CN 202111553453A CN 114416618 B CN114416618 B CN 114416618B
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- 238000004891 communication Methods 0.000 title claims abstract description 64
- 238000000034 method Methods 0.000 title claims abstract description 20
- 239000011229 interlayer Substances 0.000 claims abstract description 31
- 239000010410 layer Substances 0.000 claims abstract description 29
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 5
- 239000010703 silicon Substances 0.000 claims abstract description 5
- 230000003993 interaction Effects 0.000 claims description 22
- 230000015654 memory Effects 0.000 claims description 17
- 230000005540 biological transmission Effects 0.000 claims description 12
- 230000001360 synchronised effect Effects 0.000 claims description 8
- 230000008569 process Effects 0.000 claims description 4
- 230000008901 benefit Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/4031—Coupling between buses using bus bridges with arbitration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4286—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a handshaking protocol, e.g. RS232C link
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention proposes a three-dimensional chip comprising: a plurality of stacked chip layers, each of the chip layers including at least one chip; an interlayer communication module; the chip is in communication connection with the interlayer communication module through a through silicon via; the transmitting chip of the first chip layer transmits data information to the receiving chip of the second chip layer through the interlayer communication module. Also provided is an inter-chip communication method of a three-dimensional chip, comprising: when a transmitting chip of a first chip layer is to transmit data information to a receiving chip of a second chip layer, the transmitting chip transmits handshake information to an interlayer communication module, wherein the handshake information comprises a chip address of the receiving chip; carrying out handshake operation between the sending chip and the receiving chip by the handshake information according to the chip address by the interlayer communication module; and according to the handshake result, the interlayer communication module receives the data information and transmits the data information to the receiving chip.
Description
Technical Field
The present disclosure relates to the field of integrated circuit design, and in particular, to a method and apparatus for communication between multiple chips of a three-dimensional chip.
Background
Currently, in the post-molar age, as TSV (through silicon via) technology matures, three-dimensional chips become one solution that continues moore's law and are attracting attention. The design of the three-dimensional memory chip is realized, and the capacity, the performance and the like are greatly improved. If a three-dimensional design can be implemented on a logic chip, this means that there is a great advantage in terms of at least the area of the chip, the performance.
In solving the logic chip stacking problem, a plurality of advanced 3D packaging technologies are developed to solve heterogeneous stacking. Currently, communication among multiple chips in the market is two-dimensional and communication among chips with different functions. With respect to the three-dimensional design of homogeneous logic chips, flexible, efficient communication between chips becomes an important part of the overall design.
Disclosure of Invention
In view of the above problems, the present invention proposes a three-dimensional chip comprising: a plurality of stacked chip layers, each of the chip layers including at least one chip; an interlayer communication module; the chip is in communication connection with the interlayer communication module through a through silicon via; the transmitting chip of the first chip layer transmits data information to the receiving chip of the second chip layer through the interlayer communication module.
The three-dimensional chip of the invention, wherein the interlayer communication module comprises: an arbitration sub-module, configured to construct a handshake path between the sending chip and the receiving chip and complete handshake operation; and controlling the interaction submodule to receive, temporarily store and transmit the data information; and the interaction sub-module is used for receiving the data information from the sending chip, sending the data information to the receiving chip and temporarily storing the data information in the process of forwarding the data information.
The three-dimensional chip of the invention, wherein the interaction sub-module comprises: a reception selector for selecting a transmission chip to receive the data information; a transmission selector for selecting a receiving chip to transmit the data information; and the intermediate memory is used for temporarily storing the data information in the process of forwarding the data information.
The three-dimensional chip of the invention, wherein the intermediate memory comprises: the first register is used for temporarily storing data information in the same clock domain as the receiving chip; and the second register is used for temporarily storing data information crossing clock domains with the receiving chip and adjusting the data information and the same clock domain of the receiving chip.
The three-dimensional chip of the invention, wherein the first register is a synchronous FIFO memory, and the second register is an asynchronous FIFO memory.
The three-dimensional chip of the invention is characterized in that a direct communication path is arranged between the receiving selector and the transmitting selector.
The invention also provides a chip-to-chip communication method of the three-dimensional chip, which comprises the following steps: when a transmitting chip of a first chip layer is to transmit data information to a receiving chip of a second chip layer, the transmitting chip transmits handshake information to an interlayer communication module, wherein the handshake information comprises a chip address of the receiving chip; carrying out handshake operation between the sending chip and the receiving chip by the handshake information according to the chip address by the interlayer communication module; and according to the handshake result, the interlayer communication module receives the data information and transmits the data information to the receiving chip.
The inter-chip communication method is characterized in that an arbitration sub-module of the inter-layer communication module receives the handshake information and completes handshake operation between the sending chip and the receiving chip; receiving and transmitting the data information by an interaction sub-module of the interlayer communication module; and controlling the interaction submodule to forward the data information by the arbitration submodule according to the handshake result.
The inter-chip communication method of the invention, wherein after the handshake between the transmitting chip and the receiving chip is successful: when the sending chip and the receiving chip are in the same clock domain, if the receiving chip can receive the data information, the data information is directly transmitted to the receiving chip; otherwise, the data information is temporarily stored in a first temporary storage of the interaction sub-module, and the data information is directly transmitted to the receiving chip until the receiving chip can receive the data information; when the transmitting chip and the receiving chip are in a cross-clock domain, the data information is temporarily stored in a second register of the interaction sub-module so as to adjust the data information to the clock domain of the receiving chip, and when the receiving chip can receive the data information, the data information after adjusting the clock domain is transmitted to the receiving chip.
The invention relates to a communication method between chips, wherein the first register is a synchronous FIFO memory and the second register is an asynchronous FIFO memory.
Drawings
Fig. 1 is a schematic view of a three-dimensional chip vertical stack structure according to the present invention.
Fig. 2 is a flow chart of a method of inter-chip communication across three-dimensional chips of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the detailed description and specific examples, while indicating the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.
The invention aims to realize communication among multiple chips on a three-dimensional chip design so as to facilitate the realization of the three-dimensional chip design. In order to solve the above problems, the present invention provides a three-dimensional chip and an inter-chip communication method of the three-dimensional chip.
The three-dimensional chip comprises a plurality of chip layers, each chip layer comprises at least one logic chip, and when data transmission is carried out among the logic chips, particularly among the logic chips of different chip layers, data transmission operation is carried out through an interlayer communication module, and the interlayer communication module comprises an arbitration sub-module and an interaction sub-module. The interaction sub-module is composed of two multiplexers, a synchronous FIFO (First Input First Output, first-in first-out) memory and an asynchronous FIFO memory, and the interaction sub-module completes the transmission of data information from a transmitting end (transmitting chip) to a receiving end (receiving chip) under the control of the arbitration sub-module, so that the data interaction among chips of different chip layers of the three-dimensional chip is realized.
Fig. 1 is a schematic view of a three-dimensional chip vertical stack structure according to the present invention. As shown in fig. 1, the three-dimensional chip 100 includes a logic chip layer 110, an interlayer communication module 120, and a logic chip layer 130, and the logic chip layer 110 and the interlayer communication module 120, and the interlayer communication module 120 and the logic chip layer 130 are communicatively connected by a through silicon via 111. The interlayer communication module 120 includes an arbitration sub-module 140 and an interaction sub-module 190, where the interaction sub-module 190 needs to perform forwarding operation of data information under the control of the arbitration sub-module 140, that is, which manner the data information is to be transmitted is determined by the arbitration sub-module 140 according to the actual handshake situation of the sending chip and the receiving chip. When forwarding data information, the arbitration sub-module 140 receives a data transmission request (handshake information) of the transmitting chip, and performs handshake between the transmitting chip and the receiving chip according to the chip address of the receiving chip included in the handshake information.
The interaction submodule 190 is composed of a receiving selector 150, a transmitting selector 160, a first temporary storage 170 and a second temporary storage 180, wherein three communication paths are arranged between the receiving selector 150 and the transmitting selector 160, the first communication path is a synchronous path, and the first temporary storage 170 is arranged on the first communication path and is used for temporarily storing data information to be forwarded when a transmitting chip and a receiving chip are in the same clock domain, but the receiving chip is in the condition that the data information cannot be received; the second communication path is an asynchronous path, and the second temporary storage 180 is arranged on the second communication path and is used for temporarily storing data information to be forwarded when the sending chip and the receiving chip are in a clock domain crossing state, and adjusting the data information to be forwarded and the receiving chip to be in a clock domain; the third communication path is a direct communication path, and is used for directly transmitting the data information received by the receiving selector 150 to the transmitting selector 160 when the transmitting chip and the receiving chip are in the same clock domain and the receiving chip is in the condition of being capable of receiving the data information, so as to directly forward the data information; in the embodiment of the present invention, the first register 170 is a synchronous FIFO memory, the second register 180 is an asynchronous FIFO memory, and the first register 170 and the second register 180 may be other memories, for example, the first register 170 may be a RAM, an SDRAM, the second register 180 may be an asynchronous dual-port RAM, etc., which is not limited to this embodiment.
In the embodiment of the present invention, the receiving selector 150 and the transmitting selector 160 both use multiple input and output selectors, for example, when there are only two logic chip layers, the receiving selector 150 may be a two-out-of-one input selector, and when there are three logic chip layers, the receiving selector 150 may be a three-out-of-one input selector, and for the number of logic chip layers, the corresponding selector may be adopted, which is not limited in the present invention; meanwhile, since the interactive sub-module 190 has three communication paths therein, the reception selector 150 is a one-out-of-three selector; correspondingly, the transmission selector 160 is a three-in-one-out-of-one selector, and is also a multi-out-of-one-out selector used in setting according to the three-dimensional chip structure. The inputs and outputs of the receive selector 150 and the transmit selector 160 are selected by the arbitration sub-module 140 based on the handshake condition.
Fig. 2 is a flow chart of a method of inter-chip communication across three-dimensional chips of the present invention. As shown in fig. 2, the inter-chip communication method of the three-dimensional chip of the present invention specifically includes:
step S1, when a sending chip needs to send data information, a handshake request is sent to an arbitration sub-module, wherein the handshake information comprises a chip address of the sending chip and a chip address of a target chip, and the arbitration module enables the sending chip and the receiving chip to perform handshake operation according to the chip address of the receiving chip;
step S2, if the handshake is successful, the step S3 is entered, if the handshake is unsuccessful, the handshake operation is carried out again until the handshake is successful, or the sending chip cancels the sending task, or the handshake operation cancels the sending task after reaching the canceling operation condition; the cancellation operation condition is, for example, that the number of times of handshake failure reaches a number threshold, the time of handshake operation exceeds a time threshold, or an instruction for canceling a transmission task is received, which is not limited in the invention;
step S3, after the handshake between the transmitting end and the receiving end is successful, the arbitration sub-module controls the receiving selector to open a corresponding passage according to the chip address of the transmitting chip, so that the receiving selector receives the data information to be transmitted;
step S4, judging the clock domains of the receiving and transmitting sides, and determining that the sending end and the receiving end are the same clock domain or cross-clock domain; if the clock domain is the same clock domain, the step S5 is entered, and if the clock domain is the cross-clock domain, the step S7 is entered;
step S5, judging the receiving state of the receiving chip, and if the receiving chip is in a state capable of receiving data information, entering step S9; if the receiving chip is in a state of not receiving the data information, for example, the receiving chip is in other working states without the resource receiving the data information, the step S6 is entered;
step S6, the data information is temporarily stored by a first temporary storage device (synchronous FIFO temporary storage device) and a receiving chip is waited to receive the data information;
step S7, if the transmitting end and the receiving end are in a cross-clock domain, temporarily storing the data information into a second register (asynchronous FIFO register), and adjusting the data information and the receiving end to be in a same clock domain;
step S8, judging the receiving state of the receiving chip, and if the receiving chip is in a state capable of receiving data information, entering step S9; otherwise, the second register is continued to store data information temporarily;
and S9, controlling the transmission selector to open a corresponding passage by the arbitration submodule according to the chip address of the transmission chip, and forwarding the data information to the receiving end.
The above embodiments are only for illustrating the present invention, not for limiting the present invention, and various changes and modifications may be made by one of ordinary skill in the relevant art without departing from the spirit and scope of the present invention, and therefore, all equivalent technical solutions are also within the scope of the present invention, and the scope of the present invention is defined by the claims.
Claims (9)
1. A three-dimensional chip, comprising:
a plurality of stacked chip layers, each of the chip layers including at least one chip;
an interlayer communication module; the chip is in communication connection with the interlayer communication module through a through silicon via;
the transmitting chip of the first chip layer transmits data information to the receiving chip of the second chip layer through the interlayer communication module;
the interlayer communication module comprises an interaction sub-module which is used for receiving the data information from the sending chip, sending the data information to the receiving chip and temporarily storing the data information in the process of forwarding the data information; the interaction sub-module comprises an intermediate memory for temporarily storing the data information in the process of forwarding the data information; the intermediate memory comprises a first register and a second register, wherein the first register is used for temporarily storing data information in the same clock domain as the receiving chip; the second register is used for temporarily storing data information crossing clock domains with the receiving chip and adjusting the data information and the same clock domain of the receiving chip.
2. The three-dimensional chip of claim 1, wherein the interlayer communication module further comprises:
an arbitration sub-module, configured to construct a handshake path between the sending chip and the receiving chip and complete handshake operation; and controlling the interaction sub-module to receive, temporarily store and transmit the data information.
3. The three-dimensional chip of claim 1, wherein the interaction sub-module further comprises:
a reception selector for selecting a transmission chip to receive the data information;
and a transmission selector for selecting the receiving chip to transmit the data information.
4. The three-dimensional chip of claim 1, wherein the first register is a synchronous FIFO memory and the second register is an asynchronous FIFO memory.
5. The three-dimensional chip of claim 3, wherein the receive selector and the transmit selector further have a direct communication path therebetween.
6. An inter-chip communication method of a three-dimensional chip for realizing inter-chip communication of the three-dimensional chip according to any one of claims 1 to 5, comprising:
when a transmitting chip of a first chip layer is to transmit data information to a receiving chip of a second chip layer, the transmitting chip transmits handshake information to an interlayer communication module, wherein the handshake information comprises a chip address of the receiving chip;
carrying out handshake operation between the sending chip and the receiving chip by the handshake information according to the chip address by the interlayer communication module;
and according to the handshake result, the interlayer communication module receives the data information and transmits the data information to the receiving chip.
7. The method of inter-chip communication according to claim 6, wherein the handshake information is received by an arbitration sub-module of the inter-layer communication module and a handshake operation between the transmitting chip and the receiving chip is completed; receiving and transmitting the data information by an interaction sub-module of the interlayer communication module;
and controlling the interaction submodule to forward the data information by the arbitration submodule according to the handshake result.
8. The method of inter-chip communication according to claim 7, wherein after the handshake between the transmitting chip and the receiving chip is successful:
when the sending chip and the receiving chip are in the same clock domain, if the receiving chip can receive the data information, the data information is directly transmitted to the receiving chip; otherwise, the data information is temporarily stored in a first temporary storage of the interaction sub-module, and the data information is directly transmitted to the receiving chip until the receiving chip can receive the data information;
when the transmitting chip and the receiving chip are in a cross-clock domain, the data information is temporarily stored in a second register of the interaction sub-module so as to adjust the data information to the clock domain of the receiving chip, and when the receiving chip can receive the data information, the data information after adjusting the clock domain is transmitted to the receiving chip.
9. The method of claim 8, wherein the first register is a synchronous FIFO memory and the second register is an asynchronous FIFO memory.
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| CN202111553453.3A CN114416618B (en) | 2021-12-17 | 2021-12-17 | Three-dimensional chip and inter-chip communication method thereof |
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| CN202111553453.3A CN114416618B (en) | 2021-12-17 | 2021-12-17 | Three-dimensional chip and inter-chip communication method thereof |
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| CN114416618A CN114416618A (en) | 2022-04-29 |
| CN114416618B true CN114416618B (en) | 2024-03-12 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101931700A (en) * | 2010-08-20 | 2010-12-29 | 北京天碁科技有限公司 | Method for realizing communication between smart mobile phone chips and smart mobile phone |
| CN102624446A (en) * | 2012-03-06 | 2012-08-01 | 华中科技大学 | Structure for infrared communication between three-dimensional stacked silicon chip layers |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR102047938B1 (en) * | 2013-05-28 | 2019-11-22 | 에스케이하이닉스 주식회사 | Memory chip and semiconductor package including the same |
| KR102031074B1 (en) * | 2013-05-28 | 2019-10-15 | 에스케이하이닉스 주식회사 | Integrated circuit chip and multi chip system including the same |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101931700A (en) * | 2010-08-20 | 2010-12-29 | 北京天碁科技有限公司 | Method for realizing communication between smart mobile phone chips and smart mobile phone |
| CN102624446A (en) * | 2012-03-06 | 2012-08-01 | 华中科技大学 | Structure for infrared communication between three-dimensional stacked silicon chip layers |
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