CN114416010A - Image display method and device, electronic equipment and storage medium - Google Patents
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Abstract
The application provides a method and a device for displaying images, electronic equipment and a storage medium, wherein the method comprises the following steps: receiving and storing image data transmitted from high to low according to the bit of a pixel; when receiving part of high-bit image data, sequentially starting to display sub-frames; wherein the whole frame of image data is dispersed into a plurality of sub-frames, and the image data of low bit is placed in a designated sub-frame; after the appointed sub-frame is displayed, part of the image data with low bits is deleted successively, and the storage space is released for storing the bits of the next frame of image. The scheme saves the storage space to the maximum extent.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a method and an apparatus for displaying an image, an electronic device, and a non-transitory readable storage medium for an electronic device.
Background
In a traditional PWM chip, the data transmitted by the bus is a whole gray scale value (usually 16-bit gray scale value); in the traditional single/double-locking chip, the gray value is integrally divided into a plurality of bits, and different bits are sent in different time periods. In the middle and high-order display screens, constant current source driving chips capable of outputting high-refresh PWM are generally adopted, and such chips generally receive and store gray data and generate PWM driving signals by using a PWM generating unit.
Storing and displaying all received images continuously usually requires twice the frame image storage space, which increases the cost of the chip.
Disclosure of Invention
The embodiment of the application provides an image display method which is used for reducing data storage space as much as possible.
The embodiment of the application provides a method for displaying an image, which comprises the following steps:
receiving and storing image data transmitted from high to low according to the bit of a pixel;
when receiving part of high-bit image data, sequentially starting to display sub-frames; wherein the whole frame of image data is dispersed into a plurality of sub-frames, and the image data of low bit is placed in a designated sub-frame;
after the appointed sub-frame is displayed, part of the image data with low bits is deleted successively, and the storage space is released for storing the bits of the next frame of image.
In one embodiment, the gray scale value displayed for each sub-frame is the sum of the sub-frame integer gray scale and the sub-frame remainder gray scale.
In an embodiment, the sequentially starting the displaying of the sub-frames after receiving the image data of the partial high-order bits includes:
when receiving image data of a first bit and a subsequent bit corresponding to a subframe integer, calculating to obtain a subframe integer gray scale and a subframe remainder gray scale of a first subframe;
and starting the display of the first subframe according to the subframe integer gray scale and the subframe remainder gray scale of the first subframe.
In one embodiment, the sub-frame integer gray scale is a product of a value of a first bit corresponding to the sub-frame integer and a predetermined non-scattering period.
In an embodiment, the first bit corresponding to the sub-frame integer is determined according to the frame gray scale value, a preset non-scattering period and a preset sub-frame total number.
In an embodiment, the method further comprises:
uniformly dispersing the weight of the second bit to a plurality of subframes according to the second bit corresponding to the number of the subframes not to be scattered and a preset period not to be scattered;
and obtaining the subframe remainder gray scale of each subframe according to the image data of the second bit and a preset non-scattering period.
In an embodiment, the method further comprises:
and displaying the image data of the third bit in a designated subframe according to the third bit corresponding to the non-scattering remainder.
An embodiment of the present application further provides a display device for an image, the device including:
the data receiving module is used for receiving and storing the image data transmitted from high to low according to the bit positions of the pixels;
the sub-frame display module is used for sequentially starting the display of sub-frames when receiving part of high-bit image data; wherein the whole frame of image data is dispersed into a plurality of sub-frames, and the image data of low bit is placed in a designated sub-frame;
and the data deleting module is used for sequentially deleting part of the image data with low bits after the appointed subframe is displayed, and releasing the storage space for storing the bits of the next frame of image.
An embodiment of the present application further provides an electronic device, including:
a memory to store a computer program;
a processor for executing the computer program to implement the above method.
An embodiment of the present application further provides a non-transitory electronic device readable storage medium, including: program which, when run by an electronic device, causes the electronic device to carry out the above-mentioned method.
The embodiment of the application provides a technical scheme, image data transmitted from high to low according to the bit of a pixel is received and stored; when receiving part of high-bit image data, sequentially starting to display sub-frames; wherein the whole frame of image data is dispersed into a plurality of sub-frames, and the image data of low bit is placed in a designated sub-frame; after the appointed sub-frame is displayed, part of the image data with low bits is deleted successively, and the storage space is released for storing the bits of the next frame of image. Thereby saving the storage space to the utmost extent.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be briefly described below.
Fig. 1 is a schematic view of an application scenario of a display method of an image according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;
fig. 3 is a schematic flowchart of a method for displaying an image according to an embodiment of the present application;
fig. 4 is a timing diagram of a method for displaying an image according to an embodiment of the present disclosure;
fig. 5 is a block diagram of an image display device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
Like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
Fig. 1 is a schematic view of an application scenario of an image display method according to an embodiment of the present application. As shown in fig. 1, the application scenario includes a data transmitting device 110 and a data receiving device 120, and the data transmitting device 110 and the data receiving device 12 are connected through a bus. The data receiving means 12 may be a driving display chip. The data transmission device 110 may transmit the image data of the high bit of the entire frame image to the data reception device 12 first and then transmit the image data of the low bit, according to the bit of the pixel. The data receiving means 12 may buffer the received image data, and the data transmitting means 110 may transmit a frame synchronization signal to the data receiving means 12 via the bus after transmitting a portion of the high-order image data, instructing the data receiving means 12 to start displaying the sub-frame. If necessary, the data receiving apparatus 12 may internally generate a frame synchronization signal after receiving the partial high-order image data, and automatically start displaying the sub-frame without waiting for the data transmitting apparatus 110 to transmit the frame synchronization signal.
For example, assuming that the image data of the whole frame is 16 bits, the most significant bit of all pixels is transmitted first, named as g 15 (g [ n ] represents the n +1 th bit of all pixels), the next most significant bit of all pixels is transmitted, i.e., g [14], and so on, and g [0] is transmitted finally. After g 15:8 is transmitted and g 7 is transmitted, the frame synchronization signal can be initiated, and after the data receiving device 12 receives the frame synchronization signal, the current frame content can be immediately initiated and displayed.
Since the content of the current frame is not completely received, the embodiment of the present application disperses the image data of the whole frame to a plurality of subframes, so that the display of the first subframe is started at first. Taking 16 sub-frame display as an example, after receiving g 7 bits, the sub-frame display is started, and then the rest sub-frames are displayed while receiving lower bits.
Since the lower-order image data can be displayed in one of the designated subframes as soon as possible after being received, the data receiving apparatus 12 can delete part of the lower-order image data after the designated subframe is displayed, and release the storage space for storing the bits of the next frame of image data.
Fig. 2 is a schematic structural diagram of an electronic device provided in an embodiment of the present application. The electronic device may be used as the data receiving device 120, and the electronic device 200 may be used to execute the image displaying method provided in the embodiment of the present application. As shown in fig. 2, the electronic device 200 includes: one or more processors 202, and one or more memories 204 storing processor-executable instructions. Wherein the processor 202 is configured to execute a display method of an image provided by the following embodiments of the present application.
The processor 202 may be a device containing a Central Processing Unit (CPU), a Graphics Processing Unit (GPU) or other form of processing unit having data processing and/or instruction execution capabilities, may process data for other components in the electronic device 200, and may control other components in the electronic device 200 to perform desired functions.
The memory 204 may include one or more computer program products that may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. The volatile memory may include, for example, Random Access Memory (RAM), cache memory (cache), and/or the like. The non-volatile memory may include, for example, Read Only Memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium and executed by processor 202 to implement the method of displaying images described below. Various applications and various data, such as various data used and/or generated by the applications, may also be stored in the computer-readable storage medium.
In one embodiment, the electronic device 200 shown in FIG. 2 may also include an input device 206, an output device 208, and a data acquisition device 210, which may be interconnected via a bus system 212 and/or other form of connection mechanism (not shown). It should be noted that the components and configuration of the electronic device 200 shown in FIG. 2 are exemplary only, and not limiting, and the electronic device 200 may have other components and configurations as desired.
The input device 206 may be a device used by a user to input instructions and may include one or more of a keyboard, a mouse, a microphone, a touch screen, and the like. The output device 208 may output various information (e.g., images or sounds) to the outside (e.g., a user), and may include one or more of a display, a speaker, and the like. The data acquisition device 210 may acquire an image of a subject and store the acquired image in the memory 204 for use by other components. Illustratively, the data acquisition device 210 may be a camera.
In an embodiment, the devices in the example electronic device 100 for implementing the image display method of the embodiment of the present application may be integrally disposed, or may be disposed separately, such as the processor 202, the memory 204, the input device 206, and the output device 208 are integrally disposed, and the data acquisition device 210 is disposed separately.
In an embodiment, the example electronic device 200 for implementing the display method of the image according to the embodiment of the present application may be implemented as a smart device having a display function, such as a smart phone, a notebook computer, or the like.
Fig. 3 is a schematic flowchart of an image display method according to an embodiment of the present application. The method may be performed by the data receiving apparatus 12, as shown in fig. 3, and includes the following steps S310 to S330.
Step S310: image data transmitted from high to low in terms of the bits of the pixels is received and stored.
The gray level value of each pixel point may be represented in binary, e.g., 11111010, with bits from high to low from left to right. Assuming that each pixel is 16 bits, named g 15 g 14 g … … g 1 g 0, g 15 is the highest bit, g 0 is the lowest bit, so g 15 bits of all pixels are received and stored first, then g 14 bits of all pixels are received, and so on.
Step S320: when receiving part of high-bit image data, sequentially starting to display sub-frames; wherein the whole frame of image data is dispersed into a plurality of sub-frames, and the image data of low bit is placed in a designated sub-frame.
The embodiment of the application disperses the gray data of the whole frame to a plurality of sub-frames, and the accumulative display gray scale of the sub-frames is equal to the gray scale value of the frame. That is, for any pixel, the sum of the gray scale values of the pixel in each sub-frame is equal to the gray scale value of the pixel in the original image frame. The present embodiment represents the total gray level (e.g., 256 gray levels) of the original image frame by the frame gray level value. The high bit in step S320 may be the first bit plus one bit corresponding to the sub-frame integer i. The lower bits may be the bits corresponding to the non-scatter remainder r plus one bit. The specific principle is described in detail below.
Step S330: after the appointed sub-frame is displayed, part of the image data with low bits is deleted successively, and the storage space is released for storing the bits of the next frame of image.
Because the low bit position is already displayed in the appointed sub-frame, the image data of the low bit position can be deleted firstly, and the bit position of the next frame image stored in the space is released. Therefore, the storage space of two frames is not needed, the storage space is saved, and the chip cost is reduced.
The following provides a detailed description of the embodiments of the present application. First, some terms are explained, assuming that the frame gray scale value is g, the total number of the sub-frames is M, the S-PWM technique disperses the display of the whole frame gray scale data to a plurality of sub-frames, and the cumulative display gray scale of the sub-frames is equal to the frame gray scale value. In order to avoid flicker, the frame gray scale value is scattered into a subframe for display, in order to avoid inconsistent brightness of a driving lamp bead caused by too low gray scale, the minimum display unit K is set into a plurality of clock cycles, the subframe displays at least one minimum display unit K, the K is generally a power of 2, and the K is defined as a non-scattering cycle.
A subframe integer i is defined, i being equal to g divided by M multiplied by K, i.e. g/(M × K).
For uniform display, each sub-frame needs to display at least a gray level I, I is equal to I multiplied by K, I is I × K, I is defined as a sub-frame integer gray level.
Define Fr as the frame gray remainder, Fr equals the remainder of g divided by M multiplied by K, i.e., Fr equals g% (M × K).
D is defined as the number of subframes that are not scattered, and is equal to Fr divided by K, i.e., d ═ Fr/K.
The remainder r is defined not to be scattered, and r is equal to Fr to K, i.e., r is Fr% K, and is displayed in a designated subframe.
For example, the non-scattering period K is 16, the total number of sub-frames M is 16, and the frame gray level g [15:0] is 16 bits.
r ═ g [15:0 ]% 16 ═ g [3:0], i.e., the lower 4 bits of the remainder are the frame gray scale values without scattering.
d ═ g [15:0 ]% (16 × 16))/16 ═ g [7:4], i.e., the number of unbroken subframes is the 5 th bit to the 8 th bit of the gray scale value of the entire frame.
i ═ g [15:0]/(16 × 16)) ═ g [15:8], i.e., the subframe integer is the upper 8 bits of the frame grayscale value.
I ═ g [15:0]/(16 × 16)) × 16 ═ g [15:8] × 16, i.e., the sub-frame integer gray scale is the upper 8 bits of the frame gray scale value multiplied by K.
In one embodiment, when image data of a first bit and a subsequent bit corresponding to a subframe integer is received, calculating to obtain a subframe integer gray scale and a subframe remainder gray scale of the first subframe; and starting the display of the first subframe according to the subframe integer gray scale and the subframe remainder gray scale of the first subframe.
The gray scale value displayed by each subframe is the sum of the integer gray scale I of the subframe and the remainder gray scale of the subframe. The sub-frame integer gray level I refers to a gray level value displayed for each sub-frame. The sub-frame integer i refers to the sub-frame number of the sub-frame integer gray scale display. The subframe remainder gray refers to a gray level value at which the frame gray remainder Fr is scattered in each subframe. The sum of the subframe remainder gray scales of all the subframes is equal to the frame gray scale remainder Fr.
The sub-frame integer gray scale I is the product of the numerical value of the first bit corresponding to the sub-frame integer I and the preset non-scattering period K. The first bit corresponding to the sub-frame integer i is determined according to the frame gray scale value, the preset non-scattering period K and the preset sub-frame total number M.
For example, the non-scattering period K is 16, the total number of sub-frames M is 16, and the frame gray level g [15:0] is 16 bits. The sub-frame integer i is eight upper bits g [15:8], i.e., the first bit is eight upper bits, so that when the first bit g [15:8] and the next bit g [7] corresponding to the sub-frame integer are received, the display of the first sub-frame is started. Since the sub-frame integer gray level I is the product of the first bit g [15:8] corresponding to the sub-frame integer I and the non-scattering period K, i.e., I ═ (g [15:0]/(16 × 16)) × 16 ═ g [15:8] × 16, i.e., the sub-frame integer gray level is the upper 8 bits of the frame gray level value multiplied by K.
In an embodiment, the weight of the second bit may be uniformly dispersed to a plurality of subframes according to the second bit corresponding to the number of non-scattering subframes and a preset non-scattering period; and obtaining the subframe remainder gray scale of each subframe according to the image data of the second bit and a preset non-scattering period.
For example, K equals 16, M equals 16, and the frame gray level g [15:0] is 16 bits. As can be seen from the above formula, the number of non-scattering subframes d is the 5 th bit to the 8 th bit g [7:4] of the gray scale value of the whole frame, i.e., the second bit is g [7:4 ]. Because the data is stored and read according to bits and can not be read and operated, the embodiment of the application requires that the total number M of the subframes is a power of 2, so that the number of the subframes d corresponding to the middle bits of the total gray scale g can not be scattered, and the condition that the subframes can not be divided completely can not occur. Since the weight of the total gray scale bit g [7] is 128, the non-scattering period K is 16, the total gray scale bit is uniformly divided into subframes, K periods are displayed every 2 subframes, and the cumulative gray scale bit is (M/2) × K ═ 16/2) × 16 ═ 128, which is equal to the weight of g [7], the weight of g [7] can be divided into subframes with several ordinal numbers 0/2/4/6/9/11/13/15. 0/2/4/6/9/11/13/15 the remainder gray scale of the sub-frame with several sequence numbers is g [7] K.
Similarly, the total gray level bit g [6] is weighted to 64, and is uniformly divided into subframes, K periods are displayed every 4 subframes, and the cumulative gray level is (M/4) × K ═ 16 ═ 64, which is equal to the weight of g [6 ]. The weight of g 6 can be distributed to 1/5/10/14 subframes with several sequence numbers. 1/5/10/14 the remainder gray scale of the sub-frame with several serial numbers is g [6] K.
Similarly, the weight of the total gray level bit g [5] is 32, which is evenly divided into subframes, K periods are displayed every 8 subframes, and the cumulative gray level is (M/8) × K ═ 16 ═ 32, which is equal to the weight of g [5 ]. The weight of g 5 can be distributed to 3/12 subframes with two sequence numbers. 3/12 the remainder gray scale of the two sequence numbers is g [5] K.
Similarly, the total gray level bit g [4] is weighted to 16, and is evenly divided into subframes, and K periods are displayed every 16 subframes, and the cumulative gray level is (M/16) × K ═ 16 ═ 16/16, and is weighted to g [4 ]. So the weight of g 4 can be distributed to the 7 th sub-frame. The remainder gray scale of the sub-frame with the number 7 is g [4 ]. multidot.K.
In an embodiment, according to a third bit corresponding to a non-scattering remainder, displaying image data of the third bit in a designated subframe.
Again, taking K equal to 16, M equal to 16, and the frame gray level g [15:0] as 16 bits for example. The remainder r, which in this example is equal to g [3:0], is not scattered, i.e., the third bit is the lower four bits. The remainder r is not scattered, and can be displayed in any subframe after the bus receiving is finished, and the earlier the display is, the earlier the storage space is released.
To sum up, taking K equal to 16, M equal to 16 groups, and the frame gray level g [15:0] is 16 bits as an example, this embodiment uses binary-like method to display the remainder gray level of the sub-frame for receiving.
Subframe number 0/2/4/6/9/11/13/15, display gray scale: i + g [7] × K ═ g [15:8] × 16+ g [7] × 16;
sub-frame number 1/5/10/14/, display gray scale: i + g [6] × K ═ g [15:8] × 16+ g [6] × 16;
subframe number 3/12, display gray scale: i + g [5] × K ═ g [15:8] × 16+ g [5] × 16;
subframe number 7, display gray scale: i + g [4] × K ═ g [15:8] × 16+ g [4] × 16;
subframe number 8, display gray scale: i + r ═ g [15:8 ]. 16+ g [3:0 ].
As shown in fig. 4, the image frame synchronization signal (Video _ Vsync), the image data (Video), the Display frame synchronization signal (Display _ Vsync), and the sub-frame Display order (Display _ Group) are sequentially from top to bottom. And starting to send next frame data after the image frame synchronization signal. The image frame synchronization is a signal inside the transmitting device, and the bus protocol can also transmit. g [ n ]]N bits (i.e., the (n + 1) th bit) representing all pixels of the display area; gnRepresenting the gray scale value of the n-numbered sub-frames.
As can be seen from fig. 4, the data transmission device sequentially transmits image data from the upper bits g [15], and the 0-numbered sub-frame needs to display I + g [7] × K ═ g [15:8] + g [7]) × K, so that the g [15:7] gray scale bits are immediately displayed when received on the bus. As shown in FIG. 4, when the data receiving apparatus receives g [7] bits, the display frame synchronization signal goes high, and the display of 0-th sub-frame starts.
When displaying the sub-frame with 0 sequence number, it needs 1/16 frames, and can receive the next frame bit g 6, so when displaying the sub-frame with 1 sequence number, the needed frame bits g 15:8 and g 6 are already received, and it can ensure continuous display.
On the premise that the bit of the whole frame must be transmitted and continuously transmitted in each frame time, g 5 is already received when the subframe with 3 sequence number is displayed, g 4 is already received when the subframe with 7 sequence number is displayed, and g 3:0 is already received when the subframe with 8 sequence number is displayed, so that the subframe display does not need to receive each bit first, and the display of the first subframe can be started after the image data of partial high bit is received.
Because the image data of g 3:0 bit is not needed to be used after displaying 8 sequence number sub-frame, the image data of g 4 bit is needed to be used after displaying 7 sequence number sub-frame. Therefore, in order to release the storage space as early as possible and facilitate the storage of the bit of the next frame image to be started in advance, after the 8-sequence-number subframe is displayed, the g [4] bit and the g [3:0] bit of the current frame are not needed any more, and the bit for storing the next frame image can be released.
Similarly, after displaying 12 sequence number sub-frame, it can release g 5 bit of current frame.
After displaying the 14-sequence number sub-frame, the g 6 frame bit of the current frame can be released.
After the 15-sequence-number subframe is displayed, all bits of the current frame can be released.
Since a previous frame has released some bits (e.g., g 4:0 was released first) when a new frame is started to be stored, the storage space does not require two full frames of space. And since the display is started without the need of the whole frame bit (for example, the display can be started after receiving g 15: 7), the current frame bit is released after the time of the middle display end (in this embodiment, the 8-sequence subframe), so that the storage space can be saved to the maximum extent.
The following are embodiments of the apparatus of the present application that can be used to perform the embodiments of the method for displaying the above-mentioned images of the present application. For details not disclosed in the embodiments of the apparatus of the present application, please refer to the embodiments of the method for displaying images of the present application.
Fig. 5 is a block diagram of an image display device according to an embodiment of the present application. As shown in fig. 5, the apparatus includes: a data receiving module 510, a subframe display module 520, and a data deleting module 530.
A data receiving module 510, configured to receive and store image data transmitted from high to low according to bits of a pixel;
a sub-frame display module 520, configured to start displaying sub-frames in sequence after receiving part of the high-bit image data; wherein the whole frame of image data is dispersed into a plurality of sub-frames, and the image data of low bit is placed in a designated sub-frame;
and a data deleting module 530, configured to delete part of the lower-order image data after the designated subframe is displayed, and release the storage space for storing the bits of the next frame image.
The implementation processes of the functions and actions of the modules in the device are specifically detailed in the implementation processes of the corresponding steps in the image display method, and are not described again here.
In the embodiments provided in the present application, the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
Claims (10)
1. A method for displaying an image, the method comprising:
receiving and storing image data transmitted from high to low according to the bit of a pixel;
when receiving part of high-bit image data, sequentially starting to display sub-frames; wherein the whole frame of image data is dispersed into a plurality of sub-frames, and the image data of low bit is placed in a designated sub-frame;
after the appointed sub-frame is displayed, part of the image data with low bits is deleted successively, and the storage space is released for storing the bits of the next frame of image.
2. The method of claim 1, wherein the gray scale value displayed for each sub-frame is a sum of a sub-frame integer gray scale and a sub-frame remainder gray scale.
3. The method of claim 2, wherein the sequentially starting the displaying of the sub-frames after receiving the image data of the partial high-order bits comprises:
when receiving image data of a first bit and a subsequent bit corresponding to a subframe integer, calculating to obtain a subframe integer gray scale and a subframe remainder gray scale of a first subframe;
and starting the display of the first subframe according to the subframe integer gray scale and the subframe remainder gray scale of the first subframe.
4. The method of claim 3, wherein the sub-frame integer gray scale is a product of a value of a first bit corresponding to the sub-frame integer and a predetermined non-scattering period.
5. The method of claim 4, wherein the first bit corresponding to the integer number of sub-frames is determined according to a frame gray scale value, a preset non-scattering period and a preset total number of sub-frames.
6. The method of claim 2, further comprising:
uniformly dispersing the weight of the second bit to a plurality of subframes according to the second bit corresponding to the number of the subframes not to be scattered and a preset period not to be scattered;
and obtaining the subframe remainder gray scale of each subframe according to the image data of the second bit and a preset non-scattering period.
7. The method of claim 1, further comprising:
and displaying the image data of the third bit in a designated subframe according to the third bit corresponding to the non-scattering remainder.
8. An apparatus for displaying an image, the apparatus comprising:
the data receiving module is used for receiving and storing the image data transmitted from high to low according to the bit positions of the pixels;
the sub-frame display module is used for sequentially starting the display of sub-frames after receiving part of the image data with high bit positions; wherein the whole frame of image data is dispersed into a plurality of sub-frames, and the image data of low bit is placed in a designated sub-frame;
and the data deleting module is used for sequentially deleting part of the image data with low bits after the appointed subframe is displayed, and releasing the storage space for storing the bits of the next frame of image.
9. An electronic device, comprising:
a memory to store a computer program;
a processor to execute the computer program to implement the method of any one of claims 1 to 7.
10. A non-transitory electronic device readable storage medium, comprising: program which, when run by an electronic device, causes the electronic device to carry out the method of any one of claims 1 to 7.
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