CN114415819B - Low-power consumption MCU framework - Google Patents
Low-power consumption MCU framework Download PDFInfo
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- CN114415819B CN114415819B CN202210308479.XA CN202210308479A CN114415819B CN 114415819 B CN114415819 B CN 114415819B CN 202210308479 A CN202210308479 A CN 202210308479A CN 114415819 B CN114415819 B CN 114415819B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
- H03K5/15026—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages
- H03K5/1504—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages using a chain of active delay devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to the technical field of micro control units and discloses a low-power-consumption MCU (microprogrammed control unit) framework. The invention provides an MCU (microprogrammed control unit) architecture scheme for providing asynchronous clocks for circuits in different clock domains, namely, the MCU architecture scheme comprises a clock module and a plurality of circuit modules which are in one-to-one correspondence with a plurality of different clock domains, wherein the clock module is used for providing a plurality of clock pulse signals which are in one-to-one correspondence and have the same period for the circuit modules, and any two clock pulse signals in the clock pulse signals are configured into two signals which are not overlapped in a high-level period, so that only a certain part of circuits work at a certain moment on the premise of keeping the original performance, the power consumption can be greatly reduced, and compared with a synchronous clock circuit architecture adopting a clock tree, the insertion requirement of a buffer circuit can be effectively reduced, the power consumption is further reduced, the required chip area is reduced, and the MCU architecture scheme is convenient for practical application and popularization.
Description
Technical Field
The invention belongs to the technical field of Micro Controller Units (MCU), and particularly relates to a low-power consumption MCU framework.
Background
The micro control Unit is also called a Single Chip Microcomputer (Microcomputer) or a Single Chip Microcomputer, and is configured to appropriately reduce the frequency and specification of a Central Processing Unit (CPU), and integrate peripheral interfaces such as a Memory (Memory), a counter (Timer), a USB (Universal Serial Bus), an a/D converter, a UART (Universal Asynchronous Receiver/Transmitter), a PLC (Programmable Logic Controller), a DMA (Direct Memory Access), and the like, and even a Liquid Crystal Display (LCD) driving circuit on a Single Chip, thereby forming a Chip-level computer, and performing different combination control for different application occasions.
The currently mainstream MCU architecture is as follows: the CPU and various peripherals use the same clock, or reduce power consumption by dividing or gating the clock, but essentially, the CPU and various peripherals use the same clock. The advantage of this approach is that it satisfies the design approach of synchronous circuit of EDA (Electronic design automation) tool, and it is very suitable for the processing of EDA tool whether in circuit integration or circuit layout and wiring. But the disadvantage is also obvious, namely, because all circuits work under the same clock beat, the power consumption is very large; furthermore, for synchronization of a very long clock, the automatic place and route tool inserts many buffer circuits to control the clock SKEW (i.e. the delay difference between the sub-clock signals generated by the same clock), which further increases the power consumption and chip area.
For example, modern mainstream synchronous clock circuit design is mainly completed based on a clock tree, and according to the actual physical layout situation, an EDA tool inserts different numbers of buffer circuits to make the delays from a clock signal CLK to FF (Flip Flop) registers consistent, but as the circuit scale increases, the number of FF registers increases, and to ensure that the delays of FF registers with huge numbers are consistent, more buffer circuits need to be inserted, which results in a large amount of power consumption consumed on the clock tree rather than on the real logic function; meanwhile, as more buffer circuits are inserted, the chip area is increased.
Disclosure of Invention
The invention aims to solve the problems of very large power consumption and large required chip area caused by the fact that all circuits work under the same clock beat in the existing MCU framework, and provides a novel low-power-consumption MCU framework.
In a first aspect, the present invention provides a low power consumption MCU architecture, which includes a clock module and N circuit modules corresponding to N different clock domains one to one, wherein the clock module has N clock signal output terminals, and the N clock signal output terminals are electrically connected to the clock signal input terminals of the N circuit modules one to one, respectively, and N represents a positive integer greater than or equal to 2;
the clock module is used for generating N clock pulse signals which have the same period and are in one-to-one correspondence with the N clock signal output ends, wherein high level periods of any two clock pulse signals in the N clock pulse signals are not overlapped.
Based on the above invention, an MCU architecture scheme for providing asynchronous clocks to different clock domain circuits can be provided, that is, the MCU architecture scheme includes a clock module and a plurality of circuit modules corresponding to a plurality of different clock domains, wherein the clock module is configured to provide a plurality of clock pulse signals corresponding to the plurality of circuit modules one by one and having the same period, and configure any two clock pulse signals in the plurality of clock pulse signals into two signals having high-level periods that are not overlapped with each other, so that only a certain part of circuits can operate at a certain time on the premise of maintaining the original performance, thereby greatly reducing the power consumption.
In one possible design, the clock module includes a clock signal generation unit, a main path delay unit, an and gate unit, and M shunt delay units, where the clock signal generation unit is configured to generate an original clock signal with a period T, and M = N-1;
the signal input end of the main circuit delay unit is electrically connected with the signal output end of the clock signal generation unit, and the delay duration of the main circuit delay unit is configured to be
Wherein, in the process,
indicating a rise time greater than the pulse signal and less than
K represents a positive integer greater than 2;
the first signal input end of the AND gate unit is electrically connected with the signal output end of the clock signal generating unit, the second signal input end of the AND gate unit is electrically connected with the signal output end of the main circuit delay unit, and the signal output end of the AND gate unit is electrically connected with the first clock signal output end of the N clock signal output ends;
the signal input end of each shunt delay unit in the M shunt delay units is respectively and electrically connected with the signal output end of the AND gate unit, the signal output end of each shunt delay unit is respectively and correspondingly electrically connected with the rest clock signal output ends in the N clock signal output ends one by one, wherein the M shunt delay unitsThe delay time length of the mth branch delay unit in the delay unit is configured as
And m represents a positive integer greater than zero and less than N.
In one possible design, the main circuit delay unit includes a frequency multiplier circuit, a period delay circuit, and a delay line, where the frequency multiplier of the frequency multiplier circuit is configured to be N, and the delay duration of the delay line is configured to be N
；
The period delay circuit is used for carrying out signal delay processing on an input digital signal and outputting a new digital signal with a single delay period, wherein the single delay period refers to one period of an input clock signal;
the signal input end of the frequency doubling circuit and the digital signal input end of the periodic delay circuit are respectively and electrically connected with the signal input end of the main circuit delay unit, the signal output end of the frequency doubling circuit is electrically connected with the clock signal input end of the periodic delay circuit, the digital signal output end of the periodic delay circuit is electrically connected with one end of the delay line, and the other end of the delay line is electrically connected with the signal output end of the main circuit delay unit.
In one possible design, the M shunt delay units include a frequency multiplier circuit and M cycle delay circuits that are sequentially cascaded, where the frequency multiplication number of the frequency multiplier circuit is configured to be N;
the period delay circuit is used for carrying out signal delay processing on an input digital signal and outputting a new digital signal with a delay single period, wherein the single period refers to one period of an input clock signal;
the signal input end of the frequency doubling circuit and the digital signal input end of the first-order cascade period delay circuit in the M period delay circuits are respectively and electrically connected with the signal output end of the AND gate unit, and the signal output end of the frequency doubling circuit is respectively and electrically connected with the clock signal input end of each period delay circuit in the M period delay circuits;
and the digital signal output end of the mth period delay circuit in the M period delay circuits is used as the signal output end of the mth shunt delay unit in the M shunt delay units.
In one possible design, the period delay circuit includes a first inverter, a first D flip-flop and a second D flip-flop;
the signal input end of the first phase inverter and the clock signal input end of the first D trigger are respectively and electrically connected with the clock signal input end of the period delay circuit, and the signal output end of the first phase inverter is electrically connected with the clock signal input end of the second D trigger;
the D end of the first D trigger is electrically connected with the digital signal input end of the periodic delay circuit, the D end of the second D trigger is electrically connected with the Q end of the first D trigger, and the Q end of the second D trigger is electrically connected with the digital signal output end of the periodic delay circuit.
In one possible design, the period delay circuit includes a second inverter, a third inverter, a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor, a tenth field effect transistor, an eleventh field effect transistor, a twelfth field effect transistor, a thirteenth field effect transistor, a fourteenth field effect transistor, a fifteenth field effect transistor, a sixteenth field effect transistor, a seventeenth field effect transistor, an eighteenth field effect transistor, a nineteenth field effect transistor, and a twentieth field effect transistor;
a signal input end of the second phase inverter, a grid electrode of the ninth field effect transistor and a grid electrode of the nineteenth field effect transistor are respectively and electrically connected with a clock signal input end of the period delay circuit, and a signal output end of the second phase inverter is respectively and electrically connected with a grid electrode of the tenth field effect transistor and a grid electrode of the twentieth field effect transistor;
a signal input end of the third phase inverter, a grid electrode of the fourth field effect transistor and a grid electrode of the eighth field effect transistor are respectively and electrically connected with a digital signal input end of the periodic delay circuit, and a signal output end of the third phase inverter is respectively and electrically connected with a grid electrode of the third field effect transistor and a grid electrode of the seventh field effect transistor;
a source electrode of the first field effect transistor, a source electrode of the second field effect transistor and a source electrode of the tenth field effect transistor are respectively and electrically connected with a direct current power supply, a drain electrode of the first field effect transistor, a gate electrode of the second field effect transistor, a drain electrode of the third field effect transistor, a drain electrode of the fifth field effect transistor, a gate electrode of the sixth field effect transistor, a drain electrode of the seventh field effect transistor and a gate electrode of the fourteenth field effect transistor are respectively and electrically connected with a gate electrode of the eighteenth field effect transistor, a gate electrode of the first field effect transistor, a drain electrode of the second field effect transistor, a drain electrode of the fourth field effect transistor, a gate electrode of the fifth field effect transistor, a drain electrode of the sixth field effect transistor, a drain electrode of the eighth field effect transistor and a gate electrode of the thirteenth field effect transistor are respectively and electrically connected with a gate electrode of the seventeenth field effect transistor, a source electrode of the third field effect transistor and a source electrode of the fourth field effect transistor are respectively and electrically connected with a drain electrode of the ninth field effect transistor, a source electrode of the seventh field effect transistor and a source electrode of the eighth field effect transistor are respectively and electrically connected with a drain electrode of the tenth field effect transistor, and a source electrode of the fifth field effect transistor, a source electrode of the sixth field effect transistor and a source electrode of the ninth field effect transistor are respectively grounded;
a source electrode of the eleventh field effect transistor, a source electrode of the twelfth field effect transistor, and a source electrode of the twentieth field effect transistor are electrically connected to the dc power supply, a drain electrode of the eleventh field effect transistor, a gate electrode of the twelfth field effect transistor, a drain electrode of the thirteenth field effect transistor, a drain electrode of the fifteenth field effect transistor, a gate electrode of the sixteenth field effect transistor, and a drain electrode of the seventeenth field effect transistor are electrically connected to the digital signal output terminal of the cycle delay circuit, respectively, a gate electrode of the eleventh field effect transistor, a drain electrode of the twelfth field effect transistor, a drain electrode of the fourteenth field effect transistor, a gate electrode of the fifteenth field effect transistor, and a drain electrode of the sixteenth field effect transistor are electrically connected to a drain electrode of the eighteenth field effect transistor, respectively, a source electrode of the thirteenth field effect transistor and a source electrode of the fourteenth field effect transistor are electrically connected to a drain electrode of the nineteenth field effect transistor, the source electrode of the seventeenth field effect transistor and the source electrode of the eighteenth field effect transistor are respectively and electrically connected with the drain electrode of the twentieth field effect transistor, and the source electrode of the fifteenth field effect transistor, the source electrode of the sixteenth field effect transistor and the source electrode of the nineteenth field effect transistor are respectively grounded.
In one possible design, the first fet, the second fet, the seventh fet, the eighth fet, the tenth fet, the eleventh fet, the twelfth fet, the seventeenth fet, the eighteenth fet, and the twentieth fet each employ a p-channel fet;
the third field effect transistor, the fourth field effect transistor, the fifth field effect transistor, the sixth field effect transistor, the ninth field effect transistor, the thirteenth field effect transistor, the fourteenth field effect transistor, the fifteenth field effect transistor, the sixteenth field effect transistor, and the nineteenth field effect transistor are n-channel field effect transistors, respectively.
In one possible design, the circuit module includes a circuit unit located inside the central processing unit CPU and/or a peripheral unit located outside the CPU.
In one possible design, the N circuit modules include an instruction acquisition circuit module, an instruction decoding circuit module, an operation execution circuit module, and a data write-back circuit module, which are electrically connected in sequence.
In one possible design, the high level period of the clock pulse signal input to the instruction acquisition circuit block, the high level period of the clock pulse signal input to the instruction decoding circuit block, the high level period of the clock pulse signal input to the operation execution circuit block, and the high level period of the clock pulse signal input to the data write-back circuit block cyclically occur in this order periodically.
The invention has the technical effects that:
(1) the invention provides an MCU (micro control unit) architecture scheme for providing asynchronous clocks for circuits in different clock domains, namely, the MCU architecture scheme comprises a clock module and a plurality of circuit modules which are in one-to-one correspondence with a plurality of different clock domains, wherein the clock module is used for providing a plurality of clock pulse signals which are in one-to-one correspondence and have the same period for the circuit modules, and any two clock pulse signals in the clock pulse signals are configured into two signals with mutually non-overlapped high level periods, so that only a certain part of circuits work at a certain moment on the premise of keeping the original performance, the power consumption can be greatly reduced, and compared with a synchronous clock circuit architecture adopting a clock tree, the MCU architecture scheme can effectively reduce the insertion requirement of a buffer circuit, further reduce the power consumption and reduce the required chip area, and is convenient for practical application and popularization.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a low power consumption MCU architecture provided in the present invention.
Fig. 2 is a structural example diagram of a low power consumption MCU architecture provided in the present invention.
FIG. 3 is a timing diagram of the low power consumption MCU architecture provided by the present invention.
Fig. 4 is a schematic structural diagram of a clock module in the low power consumption MCU architecture provided in the present invention.
FIG. 5 is a timing diagram of a clock module in the low power consumption MCU architecture according to the present invention.
Fig. 6 is a schematic structural diagram of a period delay circuit in a clock module according to the present invention.
Detailed Description
The invention is further described with reference to the following figures and specific embodiments. It should be noted that the description of the embodiments is provided to help understanding of the present invention, but the present invention is not limited thereto. Specific structural and functional details disclosed herein are merely representative of exemplary embodiments of the invention. This invention may, however, be embodied in many alternate forms and should not be construed as limited to the embodiments set forth herein.
It will be understood that, although the terms first, second, etc. may be used herein to describe various objects, these objects should not be limited by these terms. These terms are only used to distinguish one object from another. For example, a first object may be referred to as a second object, and similarly, a second object may be referred to as a first object, without departing from the scope of example embodiments of the present invention.
It should be understood that, for the term "and/or" as may appear herein, it is merely an associative relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists independently, B exists independently or A and B exist simultaneously; for the term "/and" as may appear herein, which describes another associative object relationship, it means that there may be two relationships, e.g., a/and B, which may mean: a exists singly or A and B exist simultaneously; in addition, with respect to the character "/" which may appear herein, it generally means that the former and latter associated objects are in an "or" relationship.
Example one
As shown in fig. 1 to 3, the MCU architecture with low power consumption provided in this embodiment includes, but is not limited to, a clock module and N circuit modules corresponding to N different clock domains one to one, where the clock module has N clock signal output terminals, and the N clock signal output terminals are electrically connected to the clock signal input terminals of the N circuit modules one to one, respectively, where N represents a positive integer greater than or equal to 2; the clock module is used for generating N clock pulse signals which have the same period and are in one-to-one correspondence with the N clock signal output ends, wherein high level time periods of any two clock pulse signals in the N clock pulse signals are not overlapped.
As shown in fig. 1, in the specific structure of the low power consumption MCU architecture, the clock domain refers to a region that can be controlled by the same clock signal in the circuit, so that the N circuit modules are N sub-circuits that divide the MCU circuit according to different clock domains, so that the N sub-circuits can operate at different clocks; specifically, the circuit module includes, but is not limited to, a circuit unit located inside the CPU of the central processing unit and/or a peripheral unit located outside the CPU, that is, the circuit module may be a circuit inside the CPU, a circuit outside the CPU, or a combination of the circuit inside the CPU and the circuit outside the CPU. The clock module is used for generating N clock pulse signals corresponding to each other for the N circuit modules to achieve the purpose of controlling different circuit modules, so that the whole of a synchronous clock circuit adopted by the current mainstream design can be reduced to zero, and because the high level time periods of any two clock pulse signals in the N clock pulse signals are not overlapped with each other, only a certain part of circuits can work at a certain moment on the premise of keeping the original performance, so that the power consumption can be greatly reduced, and compared with a synchronous clock circuit framework adopting a clock tree, the insertion requirement of a buffer circuit can be effectively reduced, the power consumption is further reduced, and the required chip area is reduced.
For example, the internal circuit of the CPU may be divided into four parts according to the clock domain, which are respectively used for instruction fetching, instruction decoding, operation execution and write-back, that is, as shown in fig. 2, the N circuit blocks include, but are not limited to, an instruction fetch circuit block (for fetching instructions), an instruction decode circuit block (for decoding instructions), an operation execution circuit block (for executing operations), and a data write-back circuit block (for writing back), etc. which are electrically connected in sequence, and makes the instruction obtaining circuit module work under the control of the first clock pulse signal CLK0, and causes the instruction decoding circuit block to operate under the control of a second clock pulse signal CLK1, and the operation execution circuit module is operated under the control of a third clock pulse signal CLK2, and also causes the data write back circuit block to operate under the control of a fourth clock pulse signal CLK 3. As shown in fig. 3, high level periods of any two clock pulse signals of the first clock pulse signal CLK0, the second clock pulse signal CLK1, the third clock pulse signal CLK2, and the fourth clock pulse signal CLK3 do not overlap with each other (i.e., high levels do not occur at the same time), so that at a certain time, only a circuit module corresponding to a certain clock domain is operated, and thus, by using the MCU architecture scheme that divides a plurality of sub-circuits by different clock domains and provides multiple clocks, power consumption and chip area requirements can be reduced. Furthermore, it is further preferable that, as shown in fig. 3, a high level period of a clock pulse signal input to the instruction obtaining circuit block, a high level period of a clock pulse signal input to the instruction decoding circuit block, a high level period of a clock pulse signal input to the operation executing circuit block, and a high level period of a clock pulse signal input to the data write-back circuit block periodically appear in sequence, which is favorable for sequentially executing the steps of instruction fetching, instruction decoding, operation execution, write-back, and the like, and shortening the required processing time.
Preferably, the clock module includes, but is not limited to, a clock signal generating unit, a main path delay unit, an and gate unit, and M shunt delay units, where the clock signal generating unit is configured to generate an original clock signal with a period T, and M = N-1; the signal input end of the main circuit delay unit is electrically connected with the signal output end of the clock signal generation unit, and the delay duration of the main circuit delay unit is configured to be
Wherein, in the step (A),
indicating a rise time greater than the pulse signal and less than
K represents a positive integer greater than 2; the first signal input end of the AND gate unit is electrically connected with the signal output end of the clock signal generating unit, and the second signal input end of the AND gate unit is electrically connected with the signal of the main circuit delay unitThe signal output end of the AND gate unit is electrically connected with the first clock signal output end of the N clock signal output ends; the signal input end of each shunt delay unit in the M shunt delay units is respectively and electrically connected with the signal output end of the AND gate unit, the signal output end of each shunt delay unit is respectively and correspondingly electrically connected with the rest clock signal output ends in the N clock signal output ends, wherein the delay time length of the mth shunt delay unit in the M shunt delay units is configured to be
And m represents a positive integer greater than zero and less than N.
As shown in fig. 4, the clock signal generating unit may be implemented by using an existing clock signal generator, so as to generate an original clock signal with a square wave and a period T. Specifically, the main circuit delay unit includes, but is not limited to, a frequency multiplier circuit, a period delay circuit, a delay line, and the like, where the frequency multiplier of the frequency multiplier circuit is configured to be N, and the delay duration of the delay line is configured to be N
(the time length thereof is set for the purpose of ensuring that the high-level periods of any two clock pulse signals of the subsequently obtained N clock pulse signals do not overlap with each other); the period delay circuit is used for carrying out signal delay processing on an input digital signal and outputting a new digital signal with a delay single period, wherein the single period refers to one period of an input clock signal; the signal input end of the frequency doubling circuit and the digital signal input end of the periodic time delay circuit are respectively and electrically connected with the signal input end of the main circuit time delay unit, the signal output end of the frequency doubling circuit is electrically connected with the clock signal input end of the periodic time delay circuit, the digital signal output end of the periodic time delay circuit is electrically connected with one end of the time delay line, and the other end of the time delay line is electrically connected with the signal output end of the main circuit time delay unit.
As shown in fig. 5, when N =4, the output period of the frequency multiplier circuit is
The new clock signal is delayed by the period delay circuit and the delay line, so that a delay phase difference can be input at two signal input ends of the AND gate unit
The two clock signals are subjected to AND logic processing through the AND gate unit, so that a clock pulse signal with the period of T and the duty ratio of less than 25% can be obtained, and finally, different delay processing is performed on the clock pulse signal through the 3 shunt delay units, so that two clock pulse signals with high level periods and two non-overlapping clock pulse signals can be output from the 4 clock signal output ends, and the purpose of providing different clocks for the 4 circuit modules is achieved.
Preferably, in order to further reduce the required chip area, as shown in fig. 4, the M shunt delay units include a frequency multiplier circuit and M cycle delay circuits that are sequentially cascaded, where the frequency multiplication frequency of the frequency multiplier circuit is configured to be N; the period delay circuit is used for carrying out signal delay processing on an input digital signal and outputting a new digital signal with a single delay period, wherein the single delay period refers to one period of an input clock signal; the signal input end of the frequency doubling circuit and the digital signal input end of the first-order cascade period delay circuit in the M period delay circuits are respectively and electrically connected with the signal output end of the AND gate unit, and the signal output end of the frequency doubling circuit is respectively and electrically connected with the clock signal input end of each period delay circuit in the M period delay circuits; and the digital signal output end of the mth period delay circuit in the M period delay circuits is used as the signal output end of the mth shunt delay unit in the M shunt delay units. In addition, in order to further reduce the required chip area, the frequency multiplier circuit in the M shunt delay units and the frequency multiplier circuit in the main delay unit may be combined into one, that is, only one frequency multiplier circuit is designed in the whole clock module.
Specifically, the period delay circuit includes a first inverter INV1, a first D flip-flop D1, and a second D flip-flop D2; a signal input end of the first inverter INV1 and a clock signal input end of the first D flip-flop D1 are electrically connected to a clock signal input end of the period delay circuit, respectively, and a signal output end of the first inverter INV1 is electrically connected to a clock signal input end of the second D flip-flop D2; the D end of the first D trigger D1 is electrically connected with the digital signal input end of the period delay circuit, the D end of the second D trigger D2 is electrically connected with the Q end of the first D trigger D1, and the Q end of the second D trigger D2 is electrically connected with the digital signal output end of the period delay circuit. As shown in fig. 4, since a single D flip-flop can constitute a half-cycle signal delay process, a one-cycle signal delay process can be realized by a cascade design of two D flip-flops before and after, and a specific signal timing can be as shown in fig. 5.
To sum up, the MCU architecture with low power consumption provided by this embodiment has the following technical effects:
(1) the present embodiment provides an MCU architecture scheme for providing asynchronous clocks to different clock domain circuits, that is, the MCU architecture scheme includes a clock module and a plurality of circuit modules corresponding to a plurality of different clock domains one by one, where the clock module is configured to provide a plurality of clock pulse signals corresponding to the plurality of circuit modules one by one and having the same period, and configure any two clock pulse signals in the plurality of clock pulse signals into two signals with mutually non-overlapping high level periods, so that only a certain part of circuits can work at a certain time on the premise of maintaining original performance, thereby greatly reducing power consumption.
Example two
As shown in fig. 6, the present embodiment provides another low power consumption MCU architecture based on the low power consumption MCU architecture described in the first embodiment, which is different from the first embodiment in that: the period delay circuit comprises a second inverter INV2, a third inverter INV3, a first field effect transistor FET1, a second field effect transistor FET2, a third field effect transistor FET3, a fourth field effect transistor FET4, a fifth field effect transistor FET5, a sixth field effect transistor FET6, a seventh field effect transistor FET7, an eighth field effect transistor FET8, a ninth field effect transistor FET9, a tenth field effect transistor FET10, an eleventh field effect transistor FET11, a twelfth field effect transistor FET12, a thirteenth field effect transistor FET13, a fourteenth field effect transistor FET14, a fifteenth field effect transistor FET15, a sixteenth field effect transistor FET16, a seventeenth field effect transistor FET17, an eighteenth field effect transistor FET18, a nineteenth field effect transistor FET19 and a twentieth field effect transistor FET 20; a signal input end of the second inverter INV2, a gate of the ninth FET9, and a gate of the nineteenth FET19 are electrically connected to a clock signal input end of the period delay circuit, respectively, and a signal output end of the second inverter INV2 is electrically connected to a gate of the tenth FET10 and a gate of the twentieth FET20, respectively; a signal input end of the third inverter INV3, a gate of the fourth FET4, and a gate of the eighth FET8 are electrically connected to the digital signal input end of the period delay circuit, respectively, and a signal output end of the third inverter INV3 is electrically connected to a gate of the third FET3 and a gate of the seventh FET7, respectively; a source of the first FET1, a source of the second FET2, and a source of the tenth FET10 are electrically connected to a dc power source VDD, respectively, a drain of the first FET1, a gate of the second FET2, a drain of the third FET3, a drain of the fifth FET5, a gate of the sixth FET6, a drain of the seventh FET7, and a gate of the fourteenth FET14 are electrically connected to a gate of the eighteenth FET18, respectively, a gate of the first FET1, a drain of the second FET2, a drain of the fourth FET4, a gate of the fifth FET5, a drain of the sixth FET6, a drain of the eighth FET8, and a gate of the thirteenth FET13 are electrically connected to a seventeenth FET17, a source electrode of the third FET3 and a source electrode of the fourth FET4 are electrically connected to a drain electrode of the ninth FET9, respectively, a source electrode of the seventh FET7 and a source electrode of the eighth FET8 are electrically connected to a drain electrode of the tenth FET10, respectively, and a source electrode of the fifth FET5, a source electrode of the sixth FET6 and a source electrode of the ninth FET9 are grounded, respectively; a source of the eleventh FET11, a source of the twelfth FET12, and a source of the twentieth FET20 are respectively electrically connected to the dc power source VDD, a drain of the eleventh FET11, a gate of the twelfth FET12, a drain of the thirteenth FET13, a drain of the fifteenth FET15, a gate of the sixteenth FET16, and a drain of the seventeenth FET17 are respectively electrically connected to the digital signal output terminal of the periodic delay circuit, a gate of the eleventh FET11, a drain of the twelfth FET12, a drain of the fourteenth FET14, a gate of the fifteenth FET15, and a drain of the sixteenth FET16 are respectively electrically connected to a drain of the eighteenth FET18, and a source of the thirteenth FET13 and a source of the fourteenth FET14 are respectively electrically connected to the nineteenth FET19 A source of the seventeenth FET17 and a source of the eighteenth FET18 are electrically connected to the drain of the twentieth FET20, respectively, and a source of the fifteenth FET15, a source of the sixteenth FET16 and a source of the nineteenth FET19 are grounded, respectively.
As shown in fig. 6, specifically, p-channel FETs are used for the first FET1, the second FET2, the seventh FET7, the eighth FET8, the tenth FET10, the eleventh FET11, the twelfth FET12, the seventeenth FET17, the eighteenth FET18, and the twentieth FET20, respectively; the third FET3, the fourth FET4, the fifth FET5, the sixth FET6, the ninth FET9, the thirteenth FET13, the fourteenth FET14, the fifteenth FET15, the sixteenth FET16, and the nineteenth FET19 each employ an n-channel FET. With the specific design of the foregoing circuit structure, the gate voltage difference between the fifth FET5 and the sixth FET6 can be updated to follow the gate voltage difference between the third FET3 and the fourth FET4 only when the gate voltage difference between the ninth FET9 and the tenth FET10 is positive, and the gate voltage difference between the fifteenth FET15 and the sixteenth FET16 can be updated to follow the gate voltage difference between the thirteenth FET13 and the fourteenth FET14 (i.e. the gate voltage difference between the fifth FET5 and the sixth FET 6) when the gate voltage difference between the nineteenth FET19 and the twentieth FET20 is positive, so that the single-cycle delay processing of the input digital signal can be realized, meanwhile, compared to the cycle delay scheme based on a single inverter and two D flip-flops in the first embodiment, the required number of fets can be reduced from 38 (2 fets are required for a single inverter, 18 fets are required for a single D flip-flop, and 2+2 × 18= 38) to 24 (i.e., 2 × 2+20= 24), which can further reduce the required chip area.
Preferably, in the M cycle delay circuits that are sequentially cascaded, the gate of the third FET3 and the gate of the seventh FET7 in the later cycle delay circuit may be respectively and directly electrically connected to the gate of the fifteenth FET15 in the earlier cycle delay circuit, and the gate of the fourth FET4 and the gate of the eighth FET8 in the later cycle delay circuit may be respectively and directly and electrically connected to the gate of the sixteenth FET16 in the earlier cycle delay circuit, so that the third inverter INV3 may be reduced in design in the later cycle delay circuit, and the required chip area may be further reduced.
Preferably, in the M cycle delay circuits that are sequentially cascaded, the gate of the ninth FET9 and the gate of the nineteenth FET19 in all the later cycle delay circuits are directly and electrically connected to the signal input end of the second inverter INV2 in the first cycle delay circuit, respectively, and the gate of the tenth FET10 and the gate of the twentieth FET20 in all the later cycle delay circuits are directly and electrically connected to the signal output end of the second inverter INV2 in the first cycle delay circuit, respectively, so that the second inverter INV2 can be reduced and designed in all the later cycle delay circuits, respectively, and the required chip area is further reduced.
For details and technical effects of the present embodiment, reference may be made to the first embodiment, which is not described herein again.
Finally, it should be noted that the present invention is not limited to the above alternative embodiments, and that various other forms of products can be obtained by anyone in light of the present invention. The above detailed description should not be taken as limiting the scope of the invention, which is defined in the claims, and which the description is intended to be interpreted accordingly.
Claims (6)
1. A low-power consumption MCU framework is characterized by comprising a clock module and N circuit modules which are in one-to-one correspondence with N different clock domains, wherein the clock module is provided with N clock signal output ends, the N clock signal output ends are respectively and correspondingly electrically connected with the clock signal input ends of the N circuit modules one by one, and N represents a positive integer which is more than or equal to 2;
the clock module is used for generating N clock pulse signals which have the same period and are in one-to-one correspondence with the N clock signal output ends, wherein high level time periods of any two clock pulse signals in the N clock pulse signals are not overlapped with each other;
the clock module comprises a clock signal generating unit, a main path delay unit, an AND gate unit and M shunt delay units, wherein the clock signal generating unit is used for generating an original clock signal with a period of T, and M = N-1;
the signal input end of the main circuit delay unit is electrically connected with the signal output end of the clock signal generation unit, and the delay duration of the main circuit delay unit is configured to be
Wherein, in the step (A),
indicating a rise time greater than the pulse signal and less than
K represents a positive integer greater than 2;
the first signal input end of the AND gate unit is electrically connected with the signal output end of the clock signal generating unit, the second signal input end of the AND gate unit is electrically connected with the signal output end of the main circuit delay unit, and the signal output end of the AND gate unit is electrically connected with the first clock signal output end of the N clock signal output ends;
the signal input end of each shunt delay unit in the M shunt delay units is respectively and electrically connected with the signal output end of the AND gate unit, the signal output end of each shunt delay unit is respectively and correspondingly electrically connected with the rest clock signal output ends in the N clock signal output ends, wherein the delay time length of the mth shunt delay unit in the M shunt delay units is configured to be
M represents a positive integer greater than zero and less than N;
the main circuit delay unit comprises a frequency doubling circuit, a period delay circuit and a delay line, wherein the frequency doubling times of the frequency doubling circuit is configured to be N, and the delay duration of the delay line is configured to be N
；
The period delay circuit is used for carrying out signal delay processing on an input digital signal and outputting a new digital signal with a delay single period, wherein the single period refers to one period of an input clock signal;
the signal input end of the frequency doubling circuit and the digital signal input end of the periodic delay circuit are respectively electrically connected with the signal input end of the main circuit delay unit, the signal output end of the frequency doubling circuit is electrically connected with the clock signal input end of the periodic delay circuit, the digital signal output end of the periodic delay circuit is electrically connected with one end of the delay line, and the other end of the delay line is electrically connected with the signal output end of the main circuit delay unit;
the period delay circuit comprises a second inverter (INV 2), a third inverter (INV 3), a first field effect transistor (FET 1), a second field effect transistor (FET 2), a third field effect transistor (FET 3), a fourth field effect transistor (FET 4), a fifth field effect transistor (FET 5), a sixth field effect transistor (FET 6), a seventh field effect transistor (FET 7), an eighth field effect transistor (FET 8), a ninth field effect transistor (FET 9), a tenth field effect transistor (FET 10), an eleventh field effect transistor (FET 11), a twelfth field effect transistor (FET 12), a thirteenth field effect transistor (FET 13), a fourteenth field effect transistor (FET 14), a fifteenth field effect transistor (FET 15), a sixteenth field effect transistor (16), a seventeenth field effect transistor (FET 17), an eighteenth field effect transistor (FET 18), a nineteenth field effect transistor (19) and a twentieth field effect transistor (FET 20);
a signal input end of the second inverter (INV 2), a gate of the ninth field effect transistor (FET 9), and a gate of the nineteenth field effect transistor (FET 19) are electrically connected to a clock signal input end of the period delay circuit, respectively, and a signal output end of the second inverter (INV 2) is electrically connected to a gate of the tenth field effect transistor (FET 10) and a gate of the twentieth field effect transistor (FET 20), respectively;
a signal input end of the third inverter (INV 3), a gate of the fourth field effect transistor (FET 4) and a gate of the eighth field effect transistor (FET 8) are electrically connected to the digital signal input end of the period delay circuit, respectively, and a signal output end of the third inverter (INV 3) is electrically connected to a gate of the third field effect transistor (FET 3) and a gate of the seventh field effect transistor (FET 7), respectively;
a source of the first FET (FET 1), a source of the second FET (FET 2) and a source of the tenth FET (FET 10) are electrically connected to a dc power supply (VDD), respectively, a drain of the first FET (FET 1), a gate of the second FET (FET 2), a drain of the third FET (FET 3), a drain of the fifth FET (FET 5), a gate of the sixth FET (6), a drain of the seventh FET (FET 7) and a gate of the fourteenth FET (FET 14) are electrically connected to a gate of the eighteenth FET (FET 18), respectively, a gate of the first FET (1), a drain of the second FET (2), a drain of the fourth FET (4), a gate of the fifth FET (FET 5), a drain of the sixth FET (6), The drain of the eighth field-effect transistor (FET 8) and the gate of the thirteenth field-effect transistor (FET 13) are electrically connected to the gates of the seventeenth field-effect transistor (FET 17), the source of the third field-effect transistor (FET 3) and the source of the fourth field-effect transistor (FET 4) are electrically connected to the drain of the ninth field-effect transistor (FET 9), the source of the seventh field-effect transistor (FET 7) and the source of the eighth field-effect transistor (FET 8) are electrically connected to the drain of the tenth field-effect transistor (FET 10), and the source of the fifth field-effect transistor (FET 5), the source of the sixth field-effect transistor (FET 6) and the source of the ninth field-effect transistor (FET 9) are grounded, respectively;
a source of the eleventh FET (FET 11), a source of the twelfth FET (FET 12) and a source of the twentieth FET (FET 20) are respectively electrically connected to the dc power supply (VDD), a drain of the eleventh FET (FET 11), a gate of the twelfth FET (FET 12), a drain of the thirteenth FET (FET 13), a drain of the fifteenth FET (FET 15), a gate of the sixteenth FET (FET 16) and a drain of the seventeenth FET (FET 17) are respectively electrically connected to the digital signal output terminal of the period delay circuit, a gate of the eleventh FET (FET 11), a drain of the twelfth FET (FET 12), a drain of the fourteenth FET (14), a gate of the fifteenth FET (15) and a drain of the sixteenth FET (FET 16) are respectively electrically connected to a drain of the eighteenth FET (18), the source of the thirteenth field effect transistor (FET 13) and the source of the fourteenth field effect transistor (FET 14) are electrically connected to the drain of the nineteenth field effect transistor (FET 19), respectively, the source of the seventeenth field effect transistor (FET 17) and the source of the eighteenth field effect transistor (FET 18) are electrically connected to the drain of the twentieth field effect transistor (FET 20), respectively, and the source of the fifteenth field effect transistor (FET 15), the source of the sixteenth field effect transistor (FET 16) and the source of the nineteenth field effect transistor (FET 19) are grounded, respectively.
2. The MCU architecture of claim 1, wherein the M shunt delay units comprise a frequency multiplier circuit and M periodic delay circuits cascaded in sequence, wherein the frequency multiplier frequency of the frequency multiplier circuit is configured to be N;
the signal input end of the frequency doubling circuit and the digital signal input end of the first cascade-connected period delay circuit in the M period delay circuits are respectively and electrically connected with the signal output end of the AND gate unit, and the signal output end of the frequency doubling circuit is respectively and electrically connected with the clock signal input end of each period delay circuit in the M period delay circuits;
and the digital signal output end of the mth period delay circuit in the M period delay circuits is used as the signal output end of the mth shunt delay unit in the M shunt delay units.
3. The low power consumption MCU architecture of claim 1, wherein said first FET (FET 1), said second FET (FET 2), said seventh FET (FET 7), said eighth FET (FET 8), said tenth FET (FET 10), said eleventh FET (FET 11), said twelfth FET (FET 12), said seventeenth FET (FET 17), said eighteenth FET (FET 18) and said twentieth FET (FET 20) employ p-channel FETs, respectively;
the third field effect transistor (FET 3), the fourth field effect transistor (FET 4), the fifth field effect transistor (FET 5), the sixth field effect transistor (FET 6), the ninth field effect transistor (FET 9), the thirteenth field effect transistor (FET 13), the fourteenth field effect transistor (FET 14), the fifteenth field effect transistor (FET 15), the sixteenth field effect transistor (FET 16), and the nineteenth field effect transistor (FET 19) respectively adopt n-channel type field effect transistors.
4. The low power consumption MCU architecture of claim 1, wherein said circuit module comprises a circuit unit located inside the central processing unit CPU and/or a peripheral unit located outside the CPU.
5. The low power consumption MCU architecture of claim 1, wherein the N circuit modules comprise an instruction acquisition circuit module, an instruction decoding circuit module, an operation execution circuit module and a data write-back circuit module electrically connected in sequence.
6. The low-power consumption MCU architecture of claim 5, wherein a high level period of a clock pulse signal input to said instruction fetch circuit block, a high level period of a clock pulse signal input to said instruction decode circuit block, a high level period of a clock pulse signal input to said operation execution circuit block and a high level period of a clock pulse signal input to said data write-back circuit block cyclically occur in sequence periodically.
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