CN114400991A - Adjustable capacitance circuit and time delay adjusting circuit - Google Patents

Adjustable capacitance circuit and time delay adjusting circuit Download PDF

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Publication number
CN114400991A
CN114400991A CN202111565658.3A CN202111565658A CN114400991A CN 114400991 A CN114400991 A CN 114400991A CN 202111565658 A CN202111565658 A CN 202111565658A CN 114400991 A CN114400991 A CN 114400991A
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China
Prior art keywords
capacitance
circuit
capacitor
adjusting unit
adjustable
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CN202111565658.3A
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Chinese (zh)
Inventor
许强
严波
罗浚洲
王悦
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Puyuan Jingdian Technology Co ltd
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Puyuan Jingdian Technology Co ltd
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Priority to CN202111565658.3A priority Critical patent/CN114400991A/en
Publication of CN114400991A publication Critical patent/CN114400991A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting

Abstract

The invention discloses an adjustable capacitor circuit and a delay adjusting circuit. The adjustable capacitance circuit comprises at least one capacitance adjusting unit; the capacitance adjusting unit comprises a triode, at least one capacitor and a loop module, the triode and the capacitor are connected between a first port and a second port of the adjustable capacitor circuit in series, a base electrode of the triode is connected with the control signal end, and the loop module is connected with the triode and used for providing a conduction loop for the triode. The parasitic capacitance of the triode is very small, the minimum value of the capacitance value adjusting range of the capacitance adjusting unit can be reduced, and the capacitance variation ratio of the capacitance adjusting unit is increased, so that the capacitance variation ratio of the adjustable capacitance circuit can be increased, and the adjustable capacitance circuit can be used in a high-speed circuit. Meanwhile, the value range of the time constant when the adjustable capacitor circuit is used for changing the node time constant is increased, or the value range of the time delay duration when the adjustable capacitor circuit is used for the time delay circuit is increased, so that the application range of the adjustable capacitor circuit is increased.

Description

Adjustable capacitance circuit and time delay adjusting circuit
Technical Field
The embodiment of the invention relates to the technical field of electronic circuits, in particular to an adjustable capacitor circuit and a delay adjusting circuit.
Background
The adjustable capacitor circuit is used as a basic circuit structure and can be widely applied to circuits needing to change node time constants or delay time. For example, in the delay circuit, the delay duration of the delay circuit can be changed by setting an adjustable capacitor circuit for adjusting an equivalent capacitance value of the delay circuit.
In the prior art, the tunable capacitor circuit may include a tunable capacitor device for adjusting the capacitance value, for example, the tunable capacitor device may be a voltage-controlled tunable capacitor. The capacitance value of the tunable capacitor device is relatively small in adjustment range, which is not beneficial to realizing large-range capacitance value adjustment. Or, the adjustable capacitance circuit may further include a plurality of branches, and each branch controls whether the capacitor in the branch is connected to the adjustable capacitance circuit through a metal oxide semiconductor field effect transistor (MOS transistor), so that the number of capacitors in the adjustable capacitance circuit is adjusted through the MOS transistor, and capacitance adjustment of the adjustable capacitance circuit is achieved. Because the MOS tube has larger parasitic capacitance, the capacitance ratio of the adjustable capacitance circuit is smaller, and the application range of the adjustable capacitance circuit is limited.
Disclosure of Invention
The invention provides an adjustable capacitor circuit and a delay adjusting circuit, which are used for improving the capacitance variation ratio of the adjustable capacitor circuit and increasing the application range of the adjustable capacitor circuit.
In a first aspect, an embodiment of the present invention provides an adjustable capacitance circuit, including at least one capacitance adjusting unit;
the capacitance adjusting unit comprises a triode, at least one capacitor and a loop module, the triode and the capacitor are connected in series between a first port and a second port of the adjustable capacitor circuit, the base of the triode is connected with the control signal end, and the loop module is connected with the triode and used for providing a conduction loop for the triode.
Optionally, the capacitance adjusting unit comprises a first capacitance and a second capacitance;
the first pole of the first capacitor is connected with the first port, the second pole of the first capacitor is connected with the first pole of the triode, the second pole of the triode is connected with the first pole of the second capacitor, and the second pole of the second capacitor is connected with the second port.
Optionally, the loop module comprises a first resistor and a second resistor;
the first end of the first resistor and the first end of the second resistor are connected with a first voltage end, the second end of the first resistor is connected with the first pole of the triode, and the second end of the second resistor is connected with the second pole of the triode.
Optionally, the adjustable capacitance circuit comprises at least two capacitance adjusting units; at least two of the capacitance adjusting units are connected in parallel.
Optionally, bases of the triodes in different capacitance adjusting units are connected with different control signal ends.
Optionally, the ratio of the maximum capacitance values of any two capacitance adjusting units is 2n(ii) a Wherein n is an integer greater than or equal to 1.
Optionally, the adjustable capacitance circuit further comprises a voltage-controlled capacitance adjusting unit; the voltage-controlled capacitance adjusting unit is connected with the capacitance adjusting unit in parallel, and is used for continuously adjusting the capacitance value within the capacitance value range of the capacitance adjusting unit.
Optionally, the voltage-controlled capacitance adjusting unit includes a first variable capacitance and a second variable capacitance; a first pole of the first variable capacitor is connected to the first port, a second pole of the first variable capacitor and a first pole of the second variable capacitor are connected to the voltage control terminal, and a second pole of the second variable capacitor is connected to the second port.
Optionally, when the adjustable capacitance circuit includes at least two capacitance adjusting units, a capacitance adjusting unit corresponding to a minimum value of maximum capacitance values of the at least two capacitance adjusting units is a first capacitance adjusting unit; the minimum capacitance value of the voltage-controlled capacitance adjusting unit is equal to the minimum capacitance value of the first capacitance adjusting unit, and the maximum capacitance value of the voltage-controlled capacitance adjusting unit is equal to the maximum capacitance value of the first capacitance adjusting unit.
In a second aspect, an embodiment of the present invention further provides a delay adjusting circuit, which includes a high-speed data interface circuit and the adjustable capacitor circuit provided in the first aspect; the output end of the high-speed data interface circuit is connected with the adjustable capacitor circuit, the high-speed data interface circuit is used for outputting a signal to be delayed, and the adjustable capacitor circuit is used for delaying the signal to be delayed.
According to the technical scheme of the embodiment of the invention, the capacitance adjusting unit in the adjustable capacitance circuit comprises the triode, and the parasitic capacitance of the triode is very small, so that the minimum value of the capacitance adjusting unit is relatively small, the minimum value of the capacitance adjusting range of the capacitance adjusting unit can be reduced, the variable capacitance ratio of the capacitance adjusting unit is increased, the variable capacitance ratio of the adjustable capacitance circuit can be increased, and the adjustable capacitance circuit can be used in a high-speed circuit. Meanwhile, the value range of the time constant when the adjustable capacitor circuit is used for changing the node time constant is increased, or the value range of the time delay duration when the adjustable capacitor circuit is used for the time delay circuit is increased, so that the application range of the adjustable capacitor circuit is increased.
Drawings
Fig. 1 is a schematic structural diagram of an adjustable capacitor circuit provided in the prior art;
fig. 2 is a schematic structural diagram of an adjustable capacitor circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another adjustable capacitor circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another adjustable capacitor circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another adjustable capacitor circuit according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a delay adjusting circuit according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of another delay adjusting circuit according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a schematic structural diagram of an adjustable capacitor circuit provided in the prior art. As shown in fig. 1, the tunable capacitor circuit includes three branches, and each branch includes two constant-volume capacitors and a MOS transistor to form a fully-differential switched capacitor. Illustratively, the tunable capacitor circuit provided in fig. 1 includes three branches, and the first branch to the third branch respectively includes a first MOS transistor S1, a second MOS transistor S2, and a third MOS transistor S3. By respectively controlling the on-off of the first MOS transistor S1, the second MOS transistor S2 and the third MOS transistor S3, whether the capacitance of the branch where the MOS transistor is located is connected to the adjustable capacitance circuit can be controlled. For example, when the first MOS transistor S1 is turned on, the capacitance of the first branch where the first MOS transistor S1 is located is switched into the adjustable capacitance circuit. When the first MOS transistor S1 is turned off, the capacitance of the first branch in which the first MOS transistor S1 is located is broken. Therefore, the quantity of the capacitors in the adjustable capacitor circuit can be controlled by controlling the on or off of the first MOS transistor S1, and further the capacitance value of the adjustable capacitor circuit can be controlled. When the MOS tube is conducted, the conducting capacitance value of the branch where the MOS tube is located is the series equivalent capacitance value of the two capacitors. When the MOS tube is turned off, the turn-off capacitance value of the branch where the MOS tube is located is the parasitic capacitance value of the MOS tube. Because the MOS tube has larger parasitic capacitance, when the MOS tube is switched off, the switching-off capacitance value of the branch where the MOS tube is located is larger. Therefore, the ratio of the on capacitance value to the off capacitance value of the branch where the MOS tube is located is smaller, namely, the capacitance-variable ratio of the branch where the MOS tube is located is smaller, and the application range of the adjustable capacitance circuit is limited.
In view of the above technical problems, an embodiment of the present invention provides an adjustable capacitor circuit. Fig. 2 is a schematic structural diagram of an adjustable capacitor circuit according to an embodiment of the present invention. As shown in fig. 2, the adjustable capacitance circuit includes at least one capacitance adjusting unit 10; the capacitance adjusting unit 10 includes a transistor Q1, at least one capacitor C, and a loop module 111, the transistor Q1 and the capacitor C are connected in series between a first port P1 and a second port P2 of the adjustable capacitance circuit, a base of the transistor Q1 is connected to the control signal terminal CTRL, and the loop module 111 is connected to the transistor Q1, and is configured to provide a conduction loop for the transistor Q1.
In particular, fig. 2 schematically shows that the tunable capacitance circuit comprises one capacitance tuning unit 10. The capacitance adjustment unit 10 is exemplarily shown to include two capacitances C. In the capacitance adjusting unit 10, a first pole of the transistor Q1 is connected to a first port P1 of the adjustable capacitance circuit through a capacitor C, and a second pole of the transistor Q1 is connected to a second port P2 of the adjustable capacitance circuit through the first capacitor C. The first end of the loop module 111 is connected to the first voltage terminal V1, the second end of the loop module 111 is connected to the second voltage terminal V2, and the third end and the fourth end of the loop module 111 are respectively connected to the first pole and the second pole of the transistor Q1, so that when the transistor Q1 is turned on, the loop module 111 can provide a turn-on loop for the transistor Q1. The control signal terminal CTRL provides a control signal for controlling the transistor Q1 to turn on or off. When the control signal provided by the control signal terminal CTRL controls the transistor Q1 to be turned on, the first voltage terminal V1, the loop module 111, a conduction loop is formed between the transistor Q1 and the second voltage terminal V2, and at this time, the capacitor C in the adjusting subunit 110 forms a conduction loop through the transistor Q1, so that the capacitor C can be connected to the adjustable capacitor circuit, the equivalent capacitance value on the capacitor adjusting unit 10 is the series equivalent capacitance of the two capacitors C, and is used as the conduction capacitance value of the capacitor adjusting unit 10, and thus the capacitance value of the adjustable capacitor circuit can be greatly increased. When the transistor Q1 is turned off by the control signal provided by the control signal terminal CTRL, the capacitor C in the capacitance adjusting unit 10 is in an open circuit state, and at this time, the capacitor C in the capacitance adjusting unit 10 cannot be connected to the adjustable capacitance circuit, and the equivalent capacitance value on the capacitance adjusting unit 10 is the parasitic capacitance of the transistor Q1 and is used as the turn-off capacitance value of the capacitance adjusting unit 10, so that the capacitance value of the adjustable capacitance circuit can be adjusted to be approximately unchanged.
The capacitance ratio of the capacitance adjusting unit 10 is a ratio of a maximum value of the capacitance adjusting range of the capacitance adjusting unit 10 to a minimum value of the capacitance adjusting range of the capacitance adjusting unit 10. The maximum value of the capacitance value adjusting range of the capacitance adjusting unit 10 is the on capacitance value of the capacitance adjusting unit 10, that is, the equivalent capacitance value when the two capacitors C are connected to the adjustable capacitance circuit, and the minimum value of the capacitance value adjusting range of the capacitance adjusting unit 10 is the off capacitance value of the capacitance adjusting unit 10, that is, the parasitic capacitance of the triode Q1. Triode Q1 has very little parasitic capacitance for turn-off capacitance value on the capacitance adjustment unit 10 is less, thereby can reduce the minimum of the capacitance value control range of capacitance adjustment unit 10, has increased the varactor of capacitance adjustment unit 10, thereby can increase the varactor of adjustable capacitance circuit, makes adjustable capacitance circuit can be arranged in the high-speed circuit. Meanwhile, the value range of the time constant when the adjustable capacitor circuit is used for changing the node time constant is increased, or the value range of the time delay duration when the adjustable capacitor circuit is used for the time delay circuit is increased, so that the application range of the adjustable capacitor circuit is increased. In addition, each capacitance adjusting unit 10 may include only one transistor Q1, so that it is avoided that an additional transistor Q1 is added when the capacitance adjusting unit 10 forms an adjustable capacitance circuit, and on the basis of increasing the capacitance ratio, the occupied area of the adjustable capacitance circuit is saved, and the cost of the adjustable capacitance circuit is reduced.
It should be noted that fig. 2 exemplarily shows that the transistor Q1 is an N-type transistor, the transistor Q1 is turned on when the control signal provided by the control signal terminal CTRL is at a high level, and the transistor Q1 is turned off when the control signal provided by the control signal terminal CTRL is at a low level. In other embodiments, the transistor Q1 may also be a P-type transistor, which is not limited herein. In addition, the first voltage provided by the first voltage terminal V1 and the second voltage provided by the second voltage terminal V2 may be equal to or different from each other, and only when the transistor Q1 is turned on, the loop module 111 can provide a conductive loop for the transistor Q1. Illustratively, when the transistor Q1 is an N-type transistor, the first voltage terminal V1 and the second voltage terminal V2 may be ground terminals, such that the first pole and the second pole of the transistor Q1 are both low, and when the base of the transistor Q1 outputs a high level, the transistor Q1 may be turned on.
With continued reference to fig. 2, the capacitance adjusting unit 10 includes a first capacitance C1 and a second capacitance C2; a first pole of the first capacitor C1 is connected to the first port P1, a second pole of the first capacitor C2 is connected to a first pole of the transistor Q1, a second pole of the transistor Q1 is connected to a first pole of the second capacitor C2, and a second pole of the second capacitor C2 is connected to the second port P2.
Specifically, the first capacitor C1 and the second capacitor C2 are respectively connected to the first pole and the second pole of the transistor Q1, so that the first capacitor C1, the second capacitor C2 and the transistor Q1 form a fully differential capacitor adjusting unit, and the effect of the capacitor adjusting unit 10 on resisting common mode interference is improved.
Fig. 3 is a schematic structural diagram of another adjustable capacitor circuit according to an embodiment of the present invention. As shown in fig. 3, the loop module 111 includes a first resistor R1 and a second resistor R2; a first end of the first resistor R1 and a first end of the second resistor R1 are connected to the first voltage terminal V1, a second end of the first resistor R1 is connected to a first pole of the transistor Q1, and a second end of the second resistor R2 is connected to a second pole of the transistor Q2.
Specifically, when the loop module 111 includes the first resistor R1 and the second resistor R2, the first terminal of the first resistor R1 and the first terminal of the second resistor R2 are respectively used as the first terminal and the second terminal of the loop module 111, and the first resistor R1 and the second resistor R2 are simultaneously connected to the first voltage terminal V1, so that the first terminal and the second terminal of the loop module 111 input the same voltage. A second end of the first resistor R1 is connected to a first pole of the transistor Q1, so that the first resistor R1 may provide a conducting loop between the first voltage terminal V1 and the first pole of the transistor Q1, and a second end of the second resistor R2 is connected to a second pole of the transistor Q2, so that the second resistor may provide a conducting loop between the first voltage terminal V1 and the second pole of the transistor Q1, when the control signal provided by the control signal terminal CTRL controls the transistor Q1 to conduct, the first resistor R1, the transistor Q1, the second resistor R2, and the first voltage terminal V1 form a conducting loop, so that the capacitor C1 in the capacitance adjusting unit 10 forms a conducting loop through the transistor Q1, and the capacitor C1 is connected to the adjustable capacitor circuit for adjusting a capacitance value of the adjustable capacitor circuit.
It should be noted that, the time constant of the capacitance adjusting unit 10 is related to the equivalent capacitance and the equivalent resistance of the capacitance adjusting unit 10, when the loop module 111 includes the first resistor R1 and the second resistor R2, the first resistor R1 and the second resistor R2 affect the time constant of the capacitance adjusting unit 10, and by setting the resistance values of the first resistor R1 and the second resistor R2 to be small, the effect of the first resistor R1 and the second resistor R2 on the time constant of the capacitance adjusting unit 10 can be reduced. In addition, the resistances of the first resistor R1 and the second resistor R2 may be equal or different, and only when the base of the transistor Q1 outputs a high level, the transistor Q1 is turned on, which is not limited herein.
Fig. 4 is a schematic structural diagram of another adjustable capacitor circuit according to an embodiment of the present invention. As shown in fig. 4, the adjustable capacitance circuit includes at least two capacitance adjusting units 10; at least two capacitance adjusting units 10 are connected in parallel.
Specifically, at least two capacitance adjusting units 10 are connected in parallel, a first pole of one capacitor C in each capacitance adjusting unit 10 is used as the first port P1 of the adjustable capacitance circuit, and a second pole of one capacitor C is used as the second port P2 of the adjustable capacitance circuit. The adjustable capacitance circuit is exemplarily shown in fig. 4 to include three capacitance adjusting units 10. The three capacitance adjusting units 10 are connected in parallel. Through setting up two at least capacitance adjusting unit 10 parallel connection, can insert adjustable capacitance circuit through the electric capacity C1 in a plurality of capacitance adjusting unit 10, can increase adjustable capacitance circuit's capacitance value control range to can further increase adjustable capacitance circuit's varactor ratio, increase adjustable capacitance circuit's application range.
With continued reference to fig. 4, the bases of transistors Q1 in different capacitance adjustment units 10 are connected to different control signal terminals CTRL.
Specifically, the control signals provided by the different control signal terminals CTRL may individually control the on/off of the transistor Q1 in the different capacitance adjusting units 10, so as to respectively control the capacitors C1 in the different capacitance adjusting units 10 to access the adjustable capacitance circuit, and further increase the capacitance adjusting range of the adjustable capacitance circuit. Illustratively, as shown in fig. 4, the adjustable capacitor circuit includes three capacitor adjusting units 10, a base of a transistor Q1 in each capacitor adjusting unit 10 is connected to a first control signal terminal CTRL1, a second control signal terminal CTRL2, and a third control signal terminal CTRL3, respectively, a first control signal provided by the first control signal terminal CTRL1, a second control signal provided by the second control signal terminal CTRL2, and a third control signal provided by the third control signal terminal CTRL3 can control whether the capacitor C1 in the three capacitor adjusting units 10 is connected to the adjustable capacitor circuit, respectively, so that a capacitance adjusting range of the adjustable capacitor circuit can be increased, and thus a capacitance ratio of the adjustable capacitor circuit can be further increased, and a use range of the adjustable capacitor circuit can be increased.
Illustratively, when the first control signal provided by the first control signal terminal CTRL1 controls the transistor Q1 in the first capacitance adjusting unit 10 to turn off, the second control signal provided by the second control signal terminal CTRL2 controls the transistor Q1 in the second capacitance adjusting unit 10 to turn off, and the third control signal provided by the third control signal terminal CTRL3 controls the transistor Q1 in the third capacitance adjusting unit 10 to turn off, the capacitance value of the adjustable capacitance circuit is the sum of the parasitic capacitance of the transistor Q1 in the first capacitance adjusting unit 10, the parasitic capacitance of the transistor Q1 in the second capacitance adjusting unit 10, and the parasitic capacitance of the transistor Q1 in the third capacitance adjusting unit 10, and is the minimum value of the capacitance value adjusting range of the adjustable capacitance circuit. When the first control signal provided by the first control signal terminal CTRL1 controls the transistor Q1 in the first capacitance adjusting unit 10 to be turned on, the second control signal provided by the second control signal terminal CTRL2 controls the transistor Q1 in the second capacitance adjusting unit 10 to be turned off, and the third control signal provided by the third control signal terminal CTRL3 controls the transistor Q1 in the third capacitance adjusting unit 10 to be turned off, the capacitance value of the adjustable capacitance circuit is the sum of the equivalent capacitance value of at least one capacitor C in the first capacitance adjusting unit 10, the parasitic capacitance of the transistor Q1 in the second capacitance adjusting unit 10, and the parasitic capacitance of the transistor Q1 in the third capacitance adjusting unit 10. When the first control signal provided by the first control signal terminal CTRL1 controls the transistor Q1 in the first capacitance adjusting unit 10 to be turned on, the second control signal provided by the second control signal terminal CTRL2 controls the transistor Q1 in the second capacitance adjusting unit 10 to be turned on, and the third control signal provided by the third control signal terminal CTRL3 controls the transistor Q1 in the third capacitance adjusting unit 10 to be turned off, the capacitance value of the adjustable capacitance circuit is the sum of the equivalent capacitance value of at least one capacitor C in the first capacitance adjusting unit 10, the equivalent capacitance value of at least one capacitor C in the second capacitance adjusting unit 10, and the parasitic capacitance value of the transistor Q1 in the third capacitance adjusting unit 10. When the first control signal provided by the first control signal terminal CTRL1 controls the transistor Q1 in the first capacitance adjusting unit 10 to be turned on, the second control signal provided by the second control signal terminal CTRL2 controls the transistor Q1 in the second capacitance adjusting unit 10 to be turned on, and the third control signal provided by the third control signal terminal CTRL3 controls the transistor Q1 in the third capacitance adjusting unit 10 to be turned on, the capacitance value of the adjustable capacitance circuit is the sum of the equivalent capacitance value of at least one capacitor C in the first capacitance adjusting unit 10, the equivalent capacitance value of at least one capacitor C in the second capacitance adjusting unit 10, and the equivalent capacitance value of at least one capacitor C in the third capacitance adjusting unit 10, and is the maximum value of the capacitance value adjusting range of the adjustable capacitance circuit.
On the basis of the technical schemes, the ratio of the maximum capacitance values of any two capacitance adjusting units is 2n(ii) a Wherein n is an integer greater than or equal to 1.
Specifically, the triode has on and off states, so that the capacitance value adjusting range of the capacitance adjusting unit only comprises two values, namely an equivalent capacitance value of at least one capacitor in the capacitance adjusting unit when the triode is turned on and a parasitic capacitance value of the triode in the capacitance adjusting unit when the triode is turned off. When the adjustable capacitor circuit comprises at least two capacitor adjusting units, the minimum values of the capacitors of the at least two capacitor adjusting units are parasitic capacitance values of the triode, and the ratio of the maximum values of the capacitors of any two capacitor adjusting units is set to be 2nThe relation of the capacitance value adjusting ranges of different capacitance adjusting units can be made to be 2nTherefore, the capacitance adjusting unit can realize conversion correspondence between the analog signal and the digital signal. Illustratively, when the adjustable capacitance circuit comprises three capacitance adjusting units, the ratio of the maximum capacitance values of two adjacent capacitance adjusting units is 21At this time, the ratio of the maximum value of the capacitance of the first capacitance adjusting unit to the maximum value of the capacitance of the third capacitance adjusting unit is 22The conversion correspondence between the analog signals and the digital signals is realized by the capacitance adjusting unit.
Fig. 5 is a schematic structural diagram of another adjustable capacitor circuit according to an embodiment of the present invention. As shown in fig. 5, the adjustable capacitance circuit further includes a voltage-controlled capacitance adjusting unit 20; the voltage-controlled capacitance adjusting unit 20 is connected in parallel with the capacitance adjusting unit 10, and the voltage-controlled capacitance adjusting unit 20 is used for continuously adjusting the capacitance value within the capacitance value range of the capacitance adjusting unit 10.
Specifically, the voltage-controlled capacitance adjusting unit 20 may adjust the capacitance value according to the voltage, and the voltage is an analog signal, so that the voltage-controlled capacitance adjusting unit 20 may continuously adjust the capacitance value, and the application occasion of the analog signal is satisfied. In addition, the voltage-controlled capacitance adjusting unit 20 is connected in parallel with the capacitance adjusting unit 10, so that the capacitance value of the adjustable capacitance circuit is the sum of the capacitance value of the voltage-controlled capacitance adjusting unit 20 and the capacitance value of the capacitance adjusting unit 10. When the voltage-controlled capacitance adjusting unit 20 continuously adjusts the capacitance value within the capacitance value range of the capacitance adjusting unit 10, the voltage-controlled capacitance adjusting unit 20 and the capacitance adjusting unit 10 can be matched to continuously adjust the capacitance value within the capacitance value range of the capacitance adjusting unit 10, so that the adjustable capacitance circuit is applied to analog signals, and the application range of the adjustable capacitance circuit is further expanded.
With continued reference to fig. 5, the voltage controlled capacitance adjustment unit 20 includes a first variable capacitance Ct1 and a second variable capacitance Ct 2; a first pole of the first variable capacitor Ct1 is connected to the first port P1, a second pole of the first variable capacitor Ct1 and a first pole of the second variable capacitor Ct2 are connected to the voltage control terminal CV, and a second pole of the second variable capacitor Ct2 is connected to the second port P2.
Specifically, as shown in fig. 5, the first variable capacitor Ct1 and the second variable capacitor Ct2 are back-connected, and the capacitance values of the first variable capacitor Ct1 and the second variable capacitor Ct2 are controlled by the voltage control signal provided by the voltage control terminal CV, so as to adjust the capacitance value of the voltage-controlled capacitance adjusting unit 20. The first variable capacitor Ct1 and the second variable capacitor Ct2 can continuously change capacitance, so that the voltage-controlled capacitance adjusting unit 20 can realize full-value adjustment within a capacitance value adjusting range, and the application occasion of analog signals is met.
On the basis of the technical schemes, when the adjustable capacitance circuit comprises at least two capacitance adjusting units, the capacitance adjusting unit corresponding to the minimum value of the maximum capacitance values of the at least two capacitance adjusting units is a first capacitance adjusting unit; the minimum capacitance value of the voltage-controlled capacitance adjusting unit is equal to the minimum capacitance value of the first capacitance adjusting unit, and the maximum capacitance value of the voltage-controlled capacitance adjusting unit is equal to the maximum capacitance value of the first capacitance adjusting unit.
Specifically, when the adjustable capacitance circuit includes at least two capacitance adjusting units, the minimum capacitance values of the different capacitance adjusting units are equal, and the maximum capacitance values of the different capacitance adjusting units may be different. Illustratively, the ratio of the maximum capacitance values of any two capacitance adjusting units is 2nAt this time, the minimum capacitance value of the voltage-controlled capacitance adjusting unit may be set to be equal to the minimum capacitance value of the capacitance adjusting unit, and the maximum capacitance value of the voltage-controlled capacitance adjusting unit is equal to the minimum capacitance value of the maximum capacitance values of the different capacitance adjusting units, that is, the maximum capacitance value of the first capacitance adjusting unit, so that the voltage-controlled capacitance adjusting unit may continuously adjust the capacitance value adjusting range of the first capacitance adjusting unit. Meanwhile, the on-off states of the triodes in different capacitance adjusting units are controlled, so that the capacitance adjusting ranges of different capacitance adjusting units are matched with the capacitance adjusting range of the voltage-controlled capacitance adjusting unit, the continuous adjustment of the capacitance in the capacitance adjusting ranges of all the capacitance adjusting units is realized, the capacitance adjusting range of the adjustable capacitance circuit is further increased, and the application range of the adjustable capacitance circuit is increased.
Exemplarily, fig. 5 shows that the adjustable capacitance circuit includes three capacitance adjusting units 10 and one voltage-controlled capacitance adjusting unit 20. The ratio of the maximum capacitance values of any two capacitance adjusting units 10 is 2nFor example, the maximum capacitance value of the first capacitance adjusting unit 11 is smaller than the maximum capacitance value of the second capacitance adjusting unit 12, and the ratio of the maximum capacitance value of the second capacitance adjusting unit 12 to the maximum capacitance value of the first capacitance adjusting unit 11 is 2. Of a second capacitance adjusting unit 12The maximum capacitance value is smaller than the maximum capacitance value of the third capacitance adjusting unit 13, and the ratio of the maximum capacitance value of the third capacitance adjusting unit 13 to the maximum capacitance value of the second capacitance adjusting unit 12 is 2. The minimum capacitance value of the capacitance value adjusting range of the voltage-controlled capacitance adjusting unit 20 is the minimum capacitance value of the capacitance value adjusting range of the capacitance adjusting unit 10, that is, the parasitic capacitance value of the transistor Q1. The maximum capacitance value of the capacitance value adjustment range of the voltage-controlled capacitance adjusting unit 20 is the maximum capacitance value of the first capacitance adjusting unit 11. When the capacitance value of the adjustable capacitance circuit is adjusted, the transistors Q1 in the first capacitance adjusting unit 11 to the third capacitance adjusting unit 13 can be controlled to be turned off, so that the capacitance value adjusting range of the adjustable capacitance circuit is the sum of the capacitance value adjusting range of the voltage-controlled capacitance adjusting unit 20 and the parasitic capacitance value of the three transistors Q1, the capacitance value adjusting range of the adjustable capacitance circuit is larger than the capacitance value adjusting range of the first capacitance adjusting unit 11, and continuous adjustment is realized in the capacitance value adjusting range of the first capacitance adjusting unit 11. Or, the transistor Q1 in the first capacitance adjusting unit 11 may be controlled to be turned on, the transistor Q1 in the second capacitance adjusting unit 12 and the third capacitance adjusting unit 13 is turned off, the voltage-controlled capacitance adjusting unit 20 is matched with the first capacitance adjusting unit 11, so that the capacitance value of the adjustable capacitance circuit is the equivalent capacitance value of the voltage-controlled capacitance adjusting unit 20 and at least one capacitor C in the first capacitance adjusting unit 11, and the sum of the parasitic capacitance values of the two transistors Q1, and at this time, the capacitance value adjusting range of the adjustable capacitance circuit is greater than the capacitance value adjusting range of the second capacitance adjusting unit 12, and continuous adjustment is realized outside the capacitance value adjusting range of the first capacitance adjusting unit 11 and within the capacitance value adjusting range of the second capacitance adjusting unit 11. Or, the transistor Q1 in the first capacitance adjusting unit 11 may be controlled to be turned on, the transistor Q1 in the second capacitance adjusting unit 12 may be controlled to be turned on, the transistor Q1 in the third capacitance adjusting unit 13 may be controlled to be turned off, and the voltage-controlled capacitance adjusting unit 20 may cooperate with the first capacitance adjusting unit 11 and the second capacitance adjusting unit 12, so that the capacitance value of the adjustable capacitance circuit is the capacitance value of the voltage-controlled capacitance adjusting unit 20 and the capacitance value of the first capacitance adjusting unit 12The sum of the equivalent capacitance value of at least one capacitor C in the cell 11, the equivalent capacitance value of at least one capacitor C in the second capacitor adjusting unit 12, and the parasitic capacitance value of a transistor Q1, where the capacitance value adjusting range of the adjustable capacitance circuit is greater than the capacitance value adjusting range of the third capacitor adjusting unit 13, and the continuous adjustment is realized outside the capacitance value adjusting range of the second capacitor adjusting unit 12 and within the capacitance value adjusting range of the third capacitor adjusting unit 13. Or, the transistor Q1 in the first capacitance adjusting unit 11 may be controlled to be turned on, the transistor Q1 in the second capacitance adjusting unit 12 may be controlled to be turned on, the transistor Q1 in the third capacitance adjusting unit 13 may be controlled to be turned on, the voltage-controlled capacitance adjusting unit 20 cooperates with the first capacitance adjusting unit 11, the second capacitance adjusting unit 12, and the third capacitance adjusting unit 13, so that the capacitance value of the adjustable capacitance circuit is the sum of the capacitance value of the voltage-controlled capacitance adjusting unit 20 and the equivalent capacitance value of at least one capacitor C in the first capacitance adjusting unit 11, the equivalent capacitance value of at least one capacitor C in the second capacitance adjusting unit 12, and the equivalent capacitance value of at least one capacitor C in the third capacitance adjusting unit 13, and at this time, the capacitance value adjusting range of the adjustable capacitance circuit is greater than twice the capacitance value adjusting range of the third capacitance adjusting unit 13, and is outside the capacitance value adjusting range of the third capacitance adjusting unit 13, and continuous adjustment is achieved within twice the capacitance value adjustment range of the third capacitance adjustment unit 13. Therefore, the capacitance value of the adjustable capacitance circuit can be continuously adjusted within the capacitance value adjusting range, the capacitance adjusting range of the adjustable capacitance circuit is further increased, and the application range of the adjustable capacitance circuit is enlarged.
It should be noted that the above process is only an example of the adjustable capacitance circuit adjusting the capacitance value. In other embodiments, the adjustable capacitance circuit may further include a plurality of capacitance adjusting units, and the capacitance adjusting range and the adjusting process of the adjustable capacitance circuit may be adaptively changed, which is not limited herein.
In addition, the tunable capacitor circuit provided in the foregoing embodiments has a variety of application scenarios, and for example, the tunable capacitor circuit may be integrated on a functional chip or integrated in an integrated circuit, so as to implement that the capacitance of the functional chip or the integrated circuit is tunable, so as to improve the performance of the functional chip or the integrated circuit.
The embodiment of the invention also provides a delay adjusting circuit. Fig. 6 is a schematic structural diagram of a delay adjusting circuit according to an embodiment of the present invention. As shown in fig. 6, the delay adjusting circuit includes a high-speed data interface circuit 200 and an adjustable capacitor circuit 100 provided by any embodiment of the present invention; the output end of the high-speed data interface circuit 200 is connected to the adjustable capacitor circuit 100, the high-speed data interface circuit 200 is configured to output a signal to be delayed, and the adjustable capacitor circuit 100 is configured to delay the signal to be delayed.
Specifically, as shown in fig. 6, the output terminal of the high-speed data interface circuit 200 includes two output ports, which are respectively connected to two ports of the tunable capacitor circuit 100. The high-speed data interface circuit 200 provides a signal to be delayed for the adjustable capacitor circuit 100, and when the signal to be delayed is transmitted to two ports of the adjustable capacitor circuit 100, the adjustable capacitor circuit 100 adjusts the on or off state of the triode in the capacitor adjusting unit according to the delay requirement of the delay adjusting circuit, so that the delay of the signal to be delayed can be realized.
According to the technical scheme, because the capacitance adjusting unit in the adjustable capacitance circuit comprises the triode, the parasitic capacitance of the triode is very small, the minimum value of the capacitance adjusting unit is small, the minimum value of the capacitance adjusting range of the capacitance adjusting unit can be reduced, the variable capacitance ratio of the capacitance adjusting unit is increased, the variable capacitance ratio of the adjustable capacitance circuit can be increased, and the adjustable capacitance circuit can be used in a high-speed circuit. Meanwhile, the value range of the delay time of the delay adjusting circuit can be enlarged, and the application range of the adjustable capacitor circuit is enlarged.
With continued reference to FIG. 6, the high speed data interface circuit 200 is a current mode logic level interface circuit.
Specifically, the Current Mode Logic (CML) level interface circuit includes a current source, two triodes, and two resistors, wherein emitters of the two triodes are connected to an anode of the current source, a cathode of the current source is connected to a ground terminal, collectors of the two triodes are respectively connected to a power supply through a resistor and respectively used as two output terminals of the CML level interface circuit, and bases of the two triodes are respectively connected to a high level input terminal VIN and a low level input terminal VIP and respectively used for controlling the two triodes to conduct in a time-sharing manner. The CML level interface circuit is simple, so that the structure of the delay adjusting circuit can be simplified.
It should be noted that fig. 6 exemplarily shows that the adjustable capacitance circuit 100 only includes the capacitance adjusting unit 10, and in other embodiments, the adjustable capacitance circuit 100 may further include a voltage-controlled capacitance adjusting unit. Fig. 7 is a schematic structural diagram of another delay adjusting circuit according to an embodiment of the present invention. As shown in fig. 7, the adjustable capacitor circuit 100 further includes a voltage-controlled capacitor adjusting unit 20, and the voltage-controlled capacitor adjusting unit 20 can continuously adjust the capacitance value of the adjustable capacitor circuit 100 within the capacitance value adjusting range, so that the delay adjusting circuit can continuously adjust the delay duration within the delay duration adjusting range.
In addition, the delay adjusting circuit provided by the above embodiments has a variety of application scenarios, and for example, the delay adjusting circuit may be integrated on a functional chip or integrated in an integrated circuit, and is used to realize that the capacitance of the functional chip or the integrated circuit is adjustable, so as to improve the performance of the functional chip or the integrated circuit.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (10)

1. An adjustable capacitance circuit is characterized by comprising at least one capacitance adjusting unit;
the capacitance adjusting unit comprises a triode, at least one capacitor and a loop module, the triode and the capacitor are connected in series between a first port and a second port of the adjustable capacitor circuit, the base of the triode is connected with the control signal end, and the loop module is connected with the triode and used for providing a conduction loop for the triode.
2. The tunable capacitance circuit of claim 1, wherein the capacitance tuning unit comprises a first capacitance and a second capacitance;
the first pole of the first capacitor is connected with the first port, the second pole of the first capacitor is connected with the first pole of the triode, the second pole of the triode is connected with the first pole of the second capacitor, and the second pole of the second capacitor is connected with the second port.
3. The tunable capacitance circuit of claim 1, wherein the loop module comprises a first resistor and a second resistor;
the first end of the first resistor and the first end of the second resistor are connected with a first voltage end, the second end of the first resistor is connected with the first pole of the triode, and the second end of the second resistor is connected with the second pole of the triode.
4. The tunable capacitance circuit of claim 1, wherein the tunable capacitance circuit comprises at least two capacitance tuning units; at least two of the capacitance adjusting units are connected in parallel.
5. The tunable capacitance circuit according to claim 4, wherein the base of the transistor in different capacitance tuning units is connected to different control signal terminals.
6. The tunable capacitance circuit of claim 4, wherein the ratio of the maximum capacitance values of any two capacitance tuning units is2n(ii) a Wherein n is an integer greater than or equal to 1.
7. The adjustable capacitance circuit according to any one of claims 1-6, further comprising a voltage controlled capacitance adjustment unit; the voltage-controlled capacitance adjusting unit is connected with the capacitance adjusting unit in parallel, and is used for continuously adjusting the capacitance value within the capacitance value range of the capacitance adjusting unit.
8. The adjustable capacitance circuit of claim 7, wherein the voltage-controlled capacitance adjustment unit comprises a first variable capacitance and a second variable capacitance; a first pole of the first variable capacitor is connected to the first port, a second pole of the first variable capacitor and a first pole of the second variable capacitor are connected to the voltage control terminal, and a second pole of the second variable capacitor is connected to the second port.
9. The adjustable capacitor circuit according to claim 7, wherein when the adjustable capacitor circuit comprises at least two capacitor adjusting units, the capacitor adjusting unit corresponding to the minimum value of the maximum values of the capacitances of the at least two capacitor adjusting units is the first capacitor adjusting unit; the minimum capacitance value of the voltage-controlled capacitance adjusting unit is equal to the minimum capacitance value of the first capacitance adjusting unit, and the maximum capacitance value of the voltage-controlled capacitance adjusting unit is equal to the maximum capacitance value of the first capacitance adjusting unit.
10. A delay adjustment circuit comprising a high speed data interface circuit and an adjustable capacitance circuit as claimed in any one of claims 1 to 9; the output end of the high-speed data interface circuit is connected with the adjustable capacitor circuit, the high-speed data interface circuit is used for outputting a signal to be delayed, and the adjustable capacitor circuit is used for delaying the signal to be delayed.
CN202111565658.3A 2021-12-20 2021-12-20 Adjustable capacitance circuit and time delay adjusting circuit Pending CN114400991A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111565658.3A CN114400991A (en) 2021-12-20 2021-12-20 Adjustable capacitance circuit and time delay adjusting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111565658.3A CN114400991A (en) 2021-12-20 2021-12-20 Adjustable capacitance circuit and time delay adjusting circuit

Publications (1)

Publication Number Publication Date
CN114400991A true CN114400991A (en) 2022-04-26

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Family Applications (1)

Application Number Title Priority Date Filing Date
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