CN114400226A

CN114400226A - Memory and manufacturing method thereof

Info

Publication number: CN114400226A
Application number: CN202111461577.9A
Authority: CN
Inventors: 孔翠翠; 周文犀; 张坤; 吴林春
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-12-02
Filing date: 2021-12-02
Publication date: 2022-04-26

Abstract

The embodiment of the invention provides a memory and a manufacturing method thereof, wherein the manufacturing method of the memory comprises the following steps: providing a stacked structure; the stacked structure comprises a plurality of insulating layers and sacrificial layers which are alternately stacked, and a step structure is formed on at least one side of the stacked structure; the top surface of each layer of ladder of the ladder structure is a sacrificial layer; sequentially forming a first thickening layer and a second thickening layer which are stacked on the top surface of each step, wherein the first thickening layer and the second thickening layer on the top surface of the adjacent steps are electrically isolated from each other; forming a gate line isolation groove penetrating through the stacked structure; removing the sacrificial layer and the second thickening layer to form a first gap; filling a first conductive material in the first gap to form a grid and a grid thickening part; removing part of the first thickening layer close to the grid line separation groove to form a second gap; and filling a second conductive material in the second gap to form a connecting part electrically connecting the grid and the grid thickening part.

Description

Memory and manufacturing method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a memory and a manufacturing method thereof.

Background

In the memory structure, a mode of vertically stacking a plurality of layers of gates is adopted, the central area of a stacking layer is a core storage area, the edge area of the stacking layer is a ladder (SS), the core storage area is used for forming a memory cell string, a Gate layer in the stacking layer is used as a Gate Line (GL) of each layer of memory cells, and the Gate Line is led out through Contact (CT) on the ladder, so that the stacked memory device is realized. As the number of stacked layers of the memory increases, the structure and the manufacturing process of the memory in the related art have many problems.

Disclosure of Invention

In order to solve the related technical problems, embodiments of the present invention provide a memory and a method for manufacturing the same.

An embodiment of the present invention provides a memory, including:

a stacked structure; the stacked structure comprises a plurality of insulating layers and gates which are alternately stacked, and a step structure is formed on at least one side of the stacked structure; the top surface of each layer of ladder of the ladder structure is a grid;

a gate line spacer groove penetrating the stacked structure; the grid line separation groove divides the stacked structure into two regions; and

a gate thickening structure located on each step in each region; the gate thickening structures on adjacent layers of the step are electrically isolated from each other; the grid thickening structure comprises a connecting part and a first thickening part which are arranged on each layer of ladder in parallel, and a grid thickening part covering the connecting part and the first thickening part; the connecting part is at least arranged at one side close to the grid line separation groove;

the grid and the grid thickening part comprise a first conductive material, the connecting part comprises a second conductive material, and the grid thickening part are electrically connected through the connecting part.

In the scheme, grid line separation grooves are formed in two sides of the region; the connecting part comprises a first connecting part and a second connecting part, and the first connecting part and the second connecting part are respectively arranged at one side close to the grid line separation groove at the corresponding side; the first thickened portion is provided between the first connecting portion and the second connecting portion.

In the scheme, a grid line separation groove is formed in one side of the region; the connecting part is arranged at one side close to the side grid line separation groove; the first thickening part is arranged on one side far away from the side grid line separation groove.

In the above scheme, the memory further comprises a plurality of gate conductive contacts; the plurality of gate conductive contacts are respectively in contact with and electrically connected with the gate thickening structures on the corresponding layer steps.

In the above aspect, the material of the intermediate first thickened portion and the material of the insulating layer have different etching selectivity ratios.

In the above scheme, the insulating layer includes a first silicon oxide, and the first thickened portion includes a second silicon oxide; the first silicon oxide and the second silicon oxide have different physical parameters.

In the above scheme, the first conductive material and the second conductive material are the same or different materials.

In the above scheme, the first conductive material includes tungsten; the material of the second conductive material comprises tungsten or polysilicon.

The embodiment of the invention also provides a manufacturing method of the memory, which is characterized by comprising the following steps:

providing a stacked structure; the stacked structure comprises a plurality of insulating layers and sacrificial layers which are alternately stacked, and a step structure is formed on at least one side of the stacked structure; the top surface of each layer of ladder of the ladder structure is a sacrificial layer;

sequentially forming a first thickening layer and a second thickening layer which are stacked on the top surface of each step, wherein the first thickening layer and the second thickening layer on the top surface of the adjacent steps are electrically isolated from each other;

forming a gate line isolation groove penetrating through the stacked structure;

removing the sacrificial layer and the second thickening layer to form a first gap;

filling a first conductive material in the first gap to form a grid and a grid thickening part;

removing part of the first thickening layer close to the grid line separation groove to form a second gap;

and filling a second conductive material in the second gap to form a connecting part electrically connecting the grid and the grid thickening part.

In the foregoing scheme, the removing the portion of the first thickening layer near the gate line isolation groove includes:

and etching at least the first thickening layer through the grid line separation groove to remove a part of the first thickening layer close to the grid line separation groove, wherein the etching rate of an etching source to the first thickening layer is greater than the etching rate to the insulating layer in the etching process.

In the above scheme, the insulating layer includes a first silicon oxide, and the first thickening layer includes a second silicon oxide; the first silicon oxide and the second silicon oxide have different physical parameters.

In the foregoing aspect, the forming of the first and second stacked thickening layers includes:

forming a first thickened material layer at least covering the step structure;

forming a second thickened layer of material overlying the first thickened layer of material;

and removing the first thickening material layer and the second thickening material layer of each layer of the step side wall to form the first thickening layer and the second thickening layer.

In the above scheme, when the first gap is filled with the first conductive material, the first conductive material further covers the side wall of the gate line spacing groove;

the method further comprises the following steps:

removing the first conductive material covering the side wall of the grid line separation groove; when the first conductive material covering the side wall of the grid line separation groove is removed, the first conductive material of the first gap close to the grid line separation groove is removed together.

In the above scheme, when the first thickening layer near the gate line separation groove is removed, the insulating layer near the gate line separation groove is removed together.

In the above scheme, when the second gap is filled with the second conductive material, the second conductive material further covers the side wall of the gate line spacing groove;

the method further comprises the following steps:

and removing the second conductive material covering the side wall of the grid line separation groove.

In the above scheme, the method further comprises:

forming a trench hole through the stacked structure;

forming a first dielectric layer covering the side wall and the bottom of the channel hole; the dielectric constant of the material of the first dielectric layer is greater than 3.9;

and forming a storage structure in the channel hole formed with the first dielectric layer.

In the above solution, the stacking structure at least includes a first sub-stacking structure and a second sub-stacking structure which are stacked;

the forming a trench hole through the stacked structure includes:

forming a first sub-channel hole through the first sub-stacked structure;

forming a second sub-channel hole through the second sub-stacked structure; the second sub-channel hole and the first sub-channel hole, which are communicated, form the channel hole.

In the above aspect, after forming the connection portion that electrically connects the gate electrode and the gate thickening portion, the method further includes:

forming a second dielectric layer on the side wall and the bottom of the grid line separation groove;

and filling a semiconductor material in the grid line separation groove formed with the second dielectric layer.

The embodiment of the invention provides a memory and a manufacturing method thereof, wherein the manufacturing method of the memory comprises the following steps: providing a stacked structure; the stacked structure comprises a plurality of insulating layers and sacrificial layers which are alternately stacked, and a step structure is formed on at least one side of the stacked structure; the top surface of each layer of ladder of the ladder structure is a sacrificial layer; sequentially forming a first thickening layer and a second thickening layer which are stacked on the top surface of each step, wherein the first thickening layer and the second thickening layer on the top surface of the adjacent steps are electrically isolated from each other; forming a gate line isolation groove penetrating through the stacked structure; removing the sacrificial layer and the second thickening layer to form a first gap; filling a first conductive material in the first gap to form a grid and a grid thickening part; removing part of the first thickening layer close to the grid line separation groove to form a second gap; and filling a second conductive material in the second gap to form a connecting part electrically connecting the grid and the grid thickening part. In the embodiments of the present invention, by forming the connection portion and the first thickened portion on the gate exposed on the top surface of the step in the step structure and forming the gate thickened portion (two thickened layers) on the connection portion and the first thickened portion, the etching process window of the gate contact hole is increased, the risk of over-etching of the gate contact hole is reduced, and reliable gate extraction is realized; meanwhile, on one hand, in the process of forming the grid thickening part, the first thickening part is included in the grid thickening part instead of forming the filling of the solid conductive material (the first conductive material or the second conductive material), so that more conductive materials are prevented from being deposited, and more conductive materials are prevented from remaining; on the other hand, the connecting part and the gate thickening part are formed by two process steps, the deposition thickness of the conductive material formed in each process step can be distributed in a balanced mode, and the conductive material can be removed after each process step, so that the problem of residual conductive material for forming the gate is solved, the risks of wrong connection between a gate contact hole and a gate layer of the memory and gate leakage current of the memory are reduced, and the performance of the memory is improved.

Drawings

Fig. 1a is a schematic diagram illustrating a step region formed in a method for manufacturing a memory according to an embodiment of the invention;

fig. 1b is a schematic diagram illustrating a gate line spacer after being formed in a method for manufacturing a memory according to an embodiment of the invention;

FIG. 1c is a schematic diagram illustrating a location of a defect generated during a method for manufacturing a memory according to an embodiment of the invention;

FIG. 2 is a flow chart illustrating an implementation of another method for manufacturing a memory according to an embodiment of the invention;

FIGS. 3a to 3e are schematic cross-sectional views illustrating another memory formation process I according to an embodiment of the invention;

FIGS. 4a to 4j are schematic cross-sectional views illustrating another memory formation process II according to an embodiment of the invention;

FIG. 5a is a schematic cross-sectional view taken along section A-A of FIG. 4 j;

FIG. 5B is a schematic cross-sectional view taken along section B-B of FIG. 4 j;

FIG. 5c is a cross-sectional view of a Y-Z section of the memory according to an embodiment of the invention;

fig. 6a to 6h are schematic cross-sectional views illustrating another forming process three in the memory according to the embodiment of the invention.

Reference numerals

A SUBS-substrate structure; 101-a substrate; 102-a pad oxide layer; 103-a bottom polysilicon layer; 104-a buffer oxide layer; 105-a top polysilicon layer; ST-stacked structure; 201-an insulating layer; 202-a sacrificial layer; 203' -a first thickened layer of material; 204' -a second thickened layer of material; 203-a first thickening layer; 2031 — a first thickening layer first portion; 2032 — a first thickening; 204-a second thickening layer; 205-a third dielectric layer; an SS-ladder structure; a SS-T-step top surface; SS-S-step sidewalls; GAP1 — first void; GAP2 — second void; 206' -a first conductive material; 208' -a second conductive material; 206-a gate; 207-gate thickening; 208-a connecting part; GLS-gate line spacer; GAP 3-third void; RS-convex part; 209-a second dielectric layer; 210-filling a semiconductor material; CT-contact; a CH-channel hole; CHS-channel structure; 211-a first dielectric layer; 212-barrier dielectric layer; 213-a charge trapping layer; 214-a tunneling dielectric layer; 215-a channel layer; 216-a filler layer; ST1 — first sub-stack structure; ST2 — a second sub-stack structure; 217' -etching barrier material layer; 217-etch stop layer; CH 1-first sub-channel hole; CH 2-second subchannel hole.

Detailed Description

In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention are further described in detail below with reference to the drawings and the specific embodiments of the specification.

In the embodiments of the present invention, the terms "first", "second", and the like are used for distinguishing similar objects, and are not used for describing a specific order or sequence.

In embodiments of the present invention, unless otherwise expressly specified or limited, an "upper" or "lower" relationship between two layers in a semiconductor structure may be a direct contact between the two layers, or an indirect contact between the two layers through an intermediate layer.

In embodiments of the present invention, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal pair of surfaces at the top and bottom surfaces of a continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. Also, a layer may include multiple sublayers.

Spatially relative terms, such as "under," "below," "lower," "over," "upper," "upward," "downward," and the like, may describe one element or feature's relationship to another element(s) or feature(s) for ease of description herein, as illustrated in the figures, in embodiments of the invention. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

It should be noted that, for convenience of description, the first direction and the second direction are expressed as two orthogonal directions in the substrate plane or the stacked structure plane, that is, two lateral surfaces extending laterally in the substrate plane or the stacked structure plane; the third direction is a direction perpendicular to the substrate plane or the stacking structure plane, i.e., a direction in which the stacking structures are stacked. The first direction is indicated as the X direction in the drawing; the second direction is indicated as the Y direction in the drawing; the third direction is indicated as the Z direction in the drawing.

In practical application, a method for forming a lead-out line on a gate comprises the following steps: forming a dielectric layer on the stepped structure; etching the dielectric layer to obtain a stepped contact hole or a gate channel hole penetrating through the stepped structure; after the step structure is filled with the conductive material in the gate contact hole, a lead-out wire in the gate contact hole can be formed, so that the lead-out of the gate line at the step position is realized. However, as the number of stacked layers of the memory structure increases, in actual operation, during the process of etching the dielectric layer to obtain the gate contact hole, over-etching may occur, that is, the over-etching may penetrate through the corresponding stepped layer or gate layer, and even extend to the next stepped layer or the next stepped layers of the corresponding stepped layer, so that the different gate layers are connected incorrectly, thereby affecting the performance of the device.

In one embodiment, the thickness of the gate layer in the gate contact hole etching area is increased and the gate contact hole etching window is increased by adding a thickening layer to the exposed gate layer on the top surface of the step in the stepped structure. However, adding a thickening layer to the gate layer requires more gate material to be deposited; as more gate materials are deposited, in the process of forming a gate, residues of the gate materials are easily formed at the corner of the gate line spacer groove GLS, so that the gate leakage current of the finally formed memory is caused, and the performance of the memory is affected.

Fig. 1a is a schematic diagram of a memory after a step region is formed in the method for manufacturing the memory according to the above embodiment.

The above embodiment provides a memory structure in which a stacked structure 1ST having alternately stacked insulating layers 1201 and sacrificial layers 1202 is formed on a substrate 1SUBS, a stepped structure 1SS is formed in the stacked structure 1ST, a thickened sacrificial layer 1204 is formed on the sacrificial layer 1202 exposed to the step top surfaces 1SS-T, and the sacrificial layer 1202 and the thickened sacrificial layer 1204 are integrally connected.

Fig. 1b is a schematic diagram of the memory according to the above embodiment after forming the gate line spacer.

In the memory structure provided by the above embodiment, after the gate line isolation trench opening is formed, the sacrificial layer 1202 and the thickened sacrificial layer 1204 of the stacked structure 1ST in fig. 1a are replaced by a gate material to form a gate 1206, a gate 1207 with a thickened portion is formed at a position where the stepped structure 1SS is exposed to the step top surface 1SS-T, and the gate 1207 with the thickened portion is used to enlarge a gate contact hole etching window and reduce the risk of over-etching during etching a dielectric layer to obtain a gate contact hole.

The thickness of the gate electrode 1207 with a thickened portion on the step top surface 1SS-T is the sum of the first thickness 1H1 and the second thickness 1H2, the gate electrode 1206 between the insulating layers 1201 in the stacked structure 1ST has the first thickness 1H1, and since the thickness of the gate electrode 1207 with a thickened portion is larger than the thickness of the gate electrode 1206 between the insulating layers 1201, the increased thickness is the second thickness 1H 2. The gate material is deposited by a process that is necessary to meet the process requirement of the gate 1207 at the thickened portion of the step top surface 1SS-T, i.e., by depositing the gate material with the sum of the first thickness 1H1 and the second thickness 1H2 (1H1+1H2), so that the method needs to deposit more gate material, which brings difficulty in removing the unnecessary gate material on the side wall of the gate line spacer.

Fig. 1c is a schematic diagram of a location where a defect is generated during the manufacturing method of the memory according to the above embodiment.

In the process of depositing the gate material, more gate materials are deposited on the side wall of the gate line separating groove 1GLS, and as more gate materials are deposited, incomplete removal of the gate materials is easily caused when the gate materials on the side wall of the gate line separating groove are removed, especially, the residue of the gate materials is easily formed at the corner position 1CP of the gate line separating groove 1GLS even if the removal margin is increased, so that the gate leakage current of the finally formed memory affects the performance of the memory.

According to the manufacturing method of the memory provided by the embodiment of the invention, the connecting part and the first thickening part are formed on the grid exposed from the top surface of the step in the step structure, and the grid thickening part (two thickening layers) is formed on the connecting part and the first thickening part, so that the etching process window of the grid contact hole is increased, the risk of over-etching of the grid contact hole is reduced, and reliable grid leading-out is realized; meanwhile, the connecting part and the thickened part of the grid electrode are formed by two process steps, so that the deposition thickness of the conductive material for forming the grid electrode is not required to be additionally increased, the residual problem of the conductive material for forming the grid electrode is solved, the risks of wrong connection between a grid electrode contact hole and a grid electrode layer of the memory and grid electrode leakage current of the memory are reduced, and the performance of the memory is improved.

Fig. 2 is a schematic flow chart illustrating an implementation of a method for manufacturing a memory according to an embodiment of the present invention. As shown in fig. 2, the method for manufacturing the memory includes:

step S10: providing a stacked structure; the stacked structure comprises a plurality of insulating layers and sacrificial layers which are alternately stacked, and a step structure is formed on at least one side of the stacked structure; the top surface of each layer of ladder of the ladder structure is a sacrificial layer;

step S20: sequentially forming a first thickening layer and a second thickening layer which are stacked on the top surface of each step, wherein the first thickening layer and the second thickening layer on the top surface of the adjacent steps are electrically isolated from each other;

step S30: forming a gate line isolation groove penetrating through the stacked structure;

step S40: removing the sacrificial layer and the second thickening layer to form a first gap;

step S50: filling a first conductive material in the first gap to form a grid and a grid thickening part;

step S60: removing part of the first thickening layer close to the grid line separation groove to form a second gap;

step S70: and filling a second conductive material in the second gap to form a connecting part electrically connecting the grid and the grid thickening part.

Fig. 3a to fig. 3e are schematic cross-sectional views illustrating another memory forming process according to an embodiment of the invention. In detail, fig. 3a to 3e are schematic diagrams illustrating a structure forming process of a step region in a memory according to another cross section (X-Z cross section in the drawings) along a first direction and a third direction according to an embodiment of the present invention.

Referring to fig. 2 and fig. 3a, step S10 is executed. Providing a stack structure ST; the stacked structure ST comprises a plurality of insulating layers 201 and sacrificial layers 202 which are alternately stacked, and at least one side of the stacked structure ST is provided with a step structure SS; the top surface SS-T of each step of the step structure SS is a sacrificial layer 202.

In practical applications, the material of the insulating layer 201 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, and other high dielectric constant (high-k) dielectrics; the material of the sacrificial layer 202 includes, but is not limited to, nitride, silicon carbide, silicon, and silicon germanium. In one embodiment, the sacrificial layer 202 may be formed of silicon nitride (SiN); the insulating layer 201 may be made of silicon oxide (SiO)₂) The stack structure formed thereby is a nitride-oxide (NO) stack. In some embodiments, the insulating layer 201 and the sacrificial layer 202 may have the same thickness as each other, or may have different thicknesses from each other. In a subsequent process, the sacrificial layer 202 may be removed, and a gate metal material may be filled at the removed position to form a gate 206 (refer to fig. 5a below), and the gate 206 metal material may include metal tungsten (W).

In practical applications, the insulating Layer 201 and the sacrificial Layer 202 can be formed by a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, an Atomic Layer Deposition (ALD) process, or the like.

In practice, the provision stack structure ST may be formed on a substrate structure SUBS, which may have main surfaces (X-Y plane in the drawing) extending in a first direction and a second direction as a horizontal direction.

In some embodiments, the substrate structure SUBS may be selected according to actual requirements of the device, and is a composite stacked structure including a pad oxide layer 102, a bottom polysilicon layer 103, a buffer oxide layer 104, and a top polysilicon layer 105, which are sequentially stacked on a substrate 101 along a third direction (Z direction in the drawing). The material of the substrate 101 may include a Silicon (Si) substrate, a Germanium (Ge) substrate, a Silicon Germanium (SiGe) substrate, a Silicon-on-Insulator (SOI) substrate, a Germanium-on-Insulator (GOI) substrate, or the like; the material of the pad oxide layer 102 may include silicon oxide, the material of the bottom polysilicon layer 103 may include polysilicon, the material of the buffer oxide layer 104 may include silicon oxide, and the material of the top polysilicon layer 105 may include polysilicon. In practical applications, the pad oxide layer 102, the bottom polysilicon layer 103, the buffer oxide layer 104, and the top polysilicon layer 105 on the substrate 101 may be formed by PVD, CVD, or ALD processes. The substrate structure SUBS formed in this way is suitable for forming a silicon Epitaxial layer (SEG) by performing Epitaxial Growth of silicon on the back surface of the substrate 101 in a post-process, and for realizing extraction of a Common Source (Common Source) on the back surface of the substrate 101.

In practical application, at least one side of the stack structure ST is formed with a step structure SS; the step structure SS is composed of a plurality of steps, and each step comprises an oxide layer 201 and a sacrificial layer 202; the top surface SS-T of each layer of the step structure SS is a sacrificial layer 202.

Referring to fig. 2 and fig. 3b to fig. 3e, step S20 is executed. A first and second thickened

layers

203 and 204 are sequentially stacked on the top surface SS-T of each step, the first and second thickened

layers

203 and 204 on the top surface SS-T of the adjacent step being electrically isolated from each other.

In some embodiments, the method of forming stacked first and second thickening layers comprises:

forming a first thickened material layer 203' at least covering the step structure SS;

forming a second layer of thickened material 204 'covering said first thickened material 203';

removing the first and second thickened material layers 203 ', 204' of each of the step sidewalls SS-S to form the first and second thickened

layers

203, 204.

It should be noted that the first thickened material layer 203' may cover only the top surface SS-T and the step sidewall SS-S of the step structure SS, or may cover the surface of other regions except the step structure SS at the same time, which is not specifically limited herein, and the regions except the step structure SS may be selectively covered according to the process requirements.

Referring to fig. 3b, a first thickened material layer 203' covering at least the step structure SS may be formed on the stack structure ST by a PVD process, a CVD process, or an ALD process.

In some embodiments, during the etching, the etching source etches the first thickened material layer 203' at a different rate than both the insulating layer 201 and the sacrificial layer 202. Illustratively, the material of the sacrificial layer 202 is silicon nitride, the material of the insulating layer 201 is conventional silicon oxide, and the material of the first thickened material layer 203' is low-temperature silicon oxide. Illustratively, the material of the sacrificial layer 202 is silicon nitride, the material of the insulating layer 201 is silicon oxide, and the material of the first thickened material layer 203' is polysilicon. In practice, the first thickened material layer 203' comprises low-temperature silicon oxide formed by a low-temperature oxidation process at a temperature of less than 500 ℃, and the material of the insulating layer 201 comprises conventional silicon oxide formed by a thermal oxidation process at a temperature of 800 ℃ to 1200 ℃. For example, when wet etching is performed using sulfuric acid or the like as an etchant, the low-temperature type silicon oxide has an etching rate of about two to three times that of the conventional type silicon oxide.

In practical applications, the thickness of the first thickened material layer 203' can be selected according to the practical requirements of the device. In some embodiments, the first thickened material layer 203' and the sacrificial layer 202 may have the same thickness, which is beneficial for forming the connection portion 208 and the gate 206 in the subsequent process to keep the same thickness (refer to fig. 5a described below).

Referring to fig. 3c, a second thickened material layer 204 ' is formed on the first thickened material layer 203 ' at least covering the first thickened material layer 203 ', which may be formed by a PVD process, a CVD process or an ALD process or the like.

In practice, the second thickened material layer 204' and the sacrificial layer 202 have the same or different etching selectivity. It is understood that when the second thickened material layer 204' and the sacrificial layer 202 have similar etching selectivity, they are more easily removed together in the subsequent step S40. In some embodiments, the material of the second thickened material layer 204' is the same as the material of the sacrificial layer 202, and is silicon nitride.

In some embodiments, the second thickened material layer 204' comprises topological Silicon Nitride (TS SIN), and the material of the sacrificial layer 202 comprises conventional Silicon Nitride (SIN). For example, when wet etching is performed using phosphoric acid or the like as an etchant, the TS SIN material has an etch rate of SIN of about two to three times.

In some embodiments, the second thickened material layer 204' includes TS SIN, which has an etch anisotropy. Illustratively, TS SIN formed on the step sidewall SS-S has a different etch selectivity than TS SIN formed on the step top surface SS-T.

In practical applications, the thickness of the second thickened material layer 204' can be selected according to the practical requirements of the device. In some embodiments, the second thickened material layer 204' and the sacrificial layer 202 may have the same thickness, which facilitates the simultaneous formation of the gate 206 and the gate thickening 207 in the same step in the subsequent process, keeping the gate 206 and the gate thickening 207 with the same thickness (refer to fig. 5a described below).

Referring to fig. 3d, the first and second thickened layers 203 and 204 'of the first and second thickened material layers 203 and 204' of each of the step sidewalls SS-S may be removed by an etching process.

Here, the first and second thickening layers 203 and 204 on the top surfaces SS-T of adjacent steps are electrically isolated from each other, and it is understood that the first and second thickening layers 203 and 204 on the top surface SS-T of each step and the sidewalls SS-S of one step on the step are spaced apart from each other in the first direction.

In some embodiments, since TS SIN material also has an anisotropic etch rate, for example, TS SIN formed on the step sidewalls SS-S has a different etch selectivity than TS SIN formed on the step top surface SS-T. When the second thickening layer 204 is TS SIN and wet etching is performed by using phosphoric acid or the like as an etchant, the etching rate of TS SIN formed on the step sidewall SS-S is about two to three times that of TS SIN formed on the step top surface SS-T, which is beneficial to selectively removing TS SIN formed on the step sidewall SS-S by an etching process, is beneficial to forming the second thickening layer 204, and maintains the adjustability and stability of the subsequent process.

In practical application, in the process of etching the first thickened material layer 203 'and the second thickened material layer 204', the anisotropic control is adopted, and the etching rate of the step side wall SS-S and the step top surface SS-T is accurately controlled by capturing an etching end Signal (Endpoint Signal), so that the first thickened material layer 203 'and the second thickened material layer 204' of each step side wall SS-S are removed, and simultaneously, the first thickened layer 203 and the second thickened layer 204 which are remained on the step top surface SS-T are formed, as shown in fig. 3 d.

Referring to fig. 3e, the third dielectric layer 205 filling the step region SS may be formed by a High-Density Plasma Chemical Vapor Deposition (HDPCVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD) process. In practical applications, the third dielectric layer 205 includes Tetraethylorthosilicate (TEOS).

Thereafter, the third dielectric layer 205 may be planarized by a Chemical Mechanical Polishing (CMP) process.

FIGS. 4a to 4j are schematic cross-sectional views illustrating another memory formation process II according to an embodiment of the invention; illustratively, FIG. 4a is a cross-sectional view taken along C-C of FIG. 3 e. In detail, fig. 4a to 4j are schematic diagrams illustrating a structure forming process of a gate line spacer region along a second direction and a third direction section (Y-Z section in the drawings) in another memory according to an embodiment of the present invention.

Referring to fig. 2 and fig. 4a to 4b, step S30 is executed.

Referring to fig. 3e and fig. 4a, it should be noted that fig. 3e and fig. 4a are schematic structural diagrams of the memory formed in the same process step along different cross-sectional directions: fig. 4a is a cross-sectional view taken along line C-C of fig. 3e, fig. 3e is a schematic structural view taken along line X-Z of the stepped region, and fig. 4a is a schematic structural view taken along line Y-Z of the core region.

Referring to fig. 4b, a gate line spacer GLS may be formed through the stacked structure SS through an etching process. In practical applications, the plurality of gate line spacing grooves GLS may be formed in the stacked structure ST by a dry etching process, such as ion milling etching, plasma etching, reactive ion etching, laser ablation, and the like.

Referring to fig. 2 and fig. 4b to 4c, step S40 is executed.

Referring to fig. 4b to 4c, the sacrificial layer 202 and the second thickening layer 204 may be removed by an etching process to form the first GAPs GAP 1. In practical applications, when the sacrificial layer 202 and the second thickening layer 204 in the stacked structure SS are removed through the gate line spacer GLS to form the first GAP1, the sacrificial layer 202 and the second thickening layer 204 are removed by etching using the gate line spacer GLS as an etchant channel. The etching may be selective wet etching or vapor etching.

In some embodiments, the sacrificial layer 202 and the second thickening layer 204 may be removed by a wet etching process, optionally using phosphoric acid as an etchant. Referring to step S20 and fig. 3b to 3e, the second thickening layer 204 includes TS SIN, and the material of the sacrificial layer 202 includes conventional SIN; for example, when wet etching is performed using phosphoric acid or the like as an etchant, the TS SIN material has an etch rate of about two to three times that of normal SIN. This property of TS SIN material is advantageous for subsequent processes, for example, in case the thickness of the second thickening layer 204 is larger than the thickness of the sacrificial layer 202, the removal of TS SIN by the SIN removal process in the same process step can simultaneously and completely remove TS SIN, facilitate the removal of the second thickening layer 204 while removing the sacrificial layer 202, facilitate the formation of the subsequent gate thickening layer 207 (refer to fig. 5a described below), and maintain the scalability and stability of the subsequent processes.

Referring to fig. 2 and fig. 4c to 4e, step S50 is executed.

Referring to fig. 4c to 4e, the first GAP1 is filled with a first conductive material 206' to form a gate 206 and a gate thickening 207.

In some embodiments, when the first GAP1 is filled with the first conductive material 206 ', the first conductive material 206' also covers the sidewalls of the gate line spacer;

the method further comprises the following steps:

removing the first conductive material 206' covering the side walls of the gate line separation grooves; when the first conductive material 206 'covering the gate line spacer sidewalls is removed, the first conductive material 206' in the first GAP1 near the gate line spacer GLS is removed together.

Referring to fig. 4c and 4d, the first conductive material 206' may be formed in the first GAPs GAP1 by one or more deposition processes including, but not limited to, PVD processes, CVD processes, ALD processes, or any combination thereof. For example, the first conductive material 206' may be formed by an atomic layer deposition process.

In some embodiments, the first conductive material 206' comprises tungsten.

In some embodiments, when the first GAP1 is filled with the first conductive material 206 ', the first conductive material 206' also covers the sidewalls of the gate line spacer; the thickness of the first conductive material 206' covering the gate line spacer trench is a fourth width W4.

Referring to fig. 4d and 4e, the first conductive material 206' covering the gate line spacer sidewalls may be removed by an etching process to form a gate thickening portion 207 remaining in the stack structure ST, the gate electrode 206 and the top surface SS-T of the stepped structure. The gate thickening 207 and the gate 206 of the top surface SS-T of the step are spaced apart from each other in a third direction by a second thickening layer 204; the gate thickening 207 and the sidewall SS-S of the step are spaced apart from each other in the first direction (refer to fig. 5a described below).

In practical applications, the first conductive material 206' covering the sidewalls of the gate line isolation trenches is removed by dry etching, such as ion milling, plasma etching, reactive ion etching, laser ablation, or the like.

Referring to fig. 4d and 4e, in some embodiments, when the first conductive material 206 'covering the gate line spacer sidewalls is removed, portions of the first conductive material 206' in the first GAPs GAP1 are removed together, forming a third GAP3, and the third GAP3 has a third width W3. Because the removing amount of the first conductive material 206 ' covering the side wall of the gate line spacer is the sum of the fourth width W4 and the third width W3, compared with the process only having the removing amount of the fourth width W4, the process increases the removing amount of the additional third width W3, so that the first conductive material 206 ' covering the side wall of the gate line spacer is completely removed, the problem of residue of the first conductive material 206 ' is solved, the gate leakage current of the finally formed memory is prevented, and the performance of the memory is ensured. Meanwhile, the amount of the first conductive material 206' removed to cover the gate line spacer sidewalls is controlled to be the third width W3 such that the third width W3 is within a process control range, and the third width W3 may be 0-0.5 times the fourth width W4; the third width W3 is within the process control range, so that the width of the actually formed third GAP3 is prevented from being too large, which may cause more second conductive material 208 'to be deposited when the connection portion 207 is formed in a subsequent process, and finally increase the risk that the second conductive material 208' remains in the gate line spacer GLS, which may affect the performance of the memory.

Referring to fig. 2 and fig. 4e to 4f, step S60 is executed.

Referring to fig. 4e to 4f, a portion of the first thickening layer 203 near the gate line spacer GLS is removed to form a second GAP 2. The first thickening layer 203 includes a first thickening layer first portion 2031 near the gate line spacer GLS portion and a first thickening portion 2032 far from the gate line spacer GLS portion (refer to fig. 4e above), and a second GAP2 is formed after removing the first thickening layer first portion 2031.

In some embodiments, the first thickening layer first portion 2031 may be removed by an etching process to form second interstitial GAPs 2. In practical applications, when the first thickening layer first portion 2031 is removed through the gate line spacer GLS to form the second GAP2, the first thickening layer first portion 2031 is removed by etching using the gate line spacer GLS as an etchant channel. The etching may be selective wet etching or vapor etching.

In some embodiments, the first thickening layer first portion 2031 and a portion of the insulating layer 201 may be removed by a wet etch process, optionally using sulfuric acid as an etchant.

In some embodiments, when removing a portion of the first thickening layer 203 near the gate line spacer GLS, a portion of the insulating layer 201 near the gate line spacer GLS is removed together.

In some embodiments, when the first thickening layer 203 is removed near the gate line spacer GLS to form the second GAP2, a part of the material of the insulating layer 201 is removed together, and the plane formed by the insulating layer 201 and the gate electrode 206 along the third direction is an uneven plane, and it is preferable to form the insulating layer 201 and the gate electrode 206 flush along the third direction.

In some embodiments, the removing the portion of the first thickening layer 203 near the gate line spacer GLS includes:

etching at least the first thickening layer 203 through the gate line spacer GLS to remove a portion of the first thickening layer 203 close to the gate line spacer GLS, wherein an etching rate of an etching source to the first thickening layer 203 is greater than an etching rate to the insulating layer 202 during the etching process.

In some embodiments, the insulating layer 201 comprises a first silicon oxide, the first thickening layer 203 comprises a second silicon oxide; the first silicon oxide and the second silicon oxide have different physical parameters. The physical parameters comprise density, grain size, mesoporous size, dielectric constant and the like, and the difference of the physical parameters of the first silicon oxide and the second silicon oxide is finally shown to comprise the difference of etching rates. Illustratively, the material of the first silicon oxide is a conventional silicon oxide, and the material of the second silicon oxide is a low-temperature silicon oxide (see the above-mentioned related description about fig. 3 b).

In some embodiments, referring to step S20 and fig. 3b to 3e, the first thickening layer 203 comprises low temperature silicon oxide, and the material of the insulating layer 201 comprises conventional silicon oxide. For example, when wet etching is performed using sulfuric acid or the like as an etchant, the low-temperature type silicon oxide has an etching rate of about two to three times that of the conventional type silicon oxide.

In some embodiments, the characteristic that the low-temperature silicon oxide has an etching rate about two to three times that of the conventional silicon oxide is utilized, so that a portion of the insulating layer 201 is removed at the same time of forming the second GAP2, and a plane formed by the insulating layer 201 and the gate 206 along the third direction is a non-obvious rugged plane, and the insulating layer 201 and the gate 206 are preferably formed to be flush along the third direction, which is beneficial for the subsequent manufacturing process of forming the connection portion 208.

Referring to fig. 2 and fig. 4f to 4h, step S60 is executed.

The second GAP2 is filled with a second conductive material 208', forming a connection 208 electrically connecting the gate 206 and the gate thickening portion 207.

Referring to fig. 4f through 4g, the second conductive material 208' may be formed in the second GAPs GAP2 by one or more deposition processes including, but not limited to, PVD processes, CVD processes, ALD processes, or any combination thereof. For example, the second conductive material 208' may be formed by an atomic layer deposition process.

In some embodiments, the first conductive material 206 'and the second conductive material 208' deposited on the basis of two process steps are the same or different materials. In practice, the material 206 'of the first conductive material comprises tungsten and the material 208' of the second conductive material comprises tungsten or doped polysilicon.

In some embodiments, when the second GAP2 is filled with the second conductive material 208 ', the second conductive material 208' also covers the sidewalls of the gate line spacer. A fifth width W5 (refer to fig. 4g) of the thickness of the second conductive material 208' covering the sidewalls of the gate line spacer.

Referring to fig. 4g to 4h, in some embodiments, when the second conductive material 208 'is filled in the second GAP2 (see fig. 4f), the second conductive material 208' also covers the sidewalls of the gate line spacer GLS (see fig. 4 g);

the method further comprises the following steps:

the second conductive material 208' covering the gate line spacer sidewalls is removed.

The second conductive material 208' covering the gate line spacer sidewalls may be removed by an etching process to form the connection portion 208 remaining in the second GAP 2. Wherein the connection portion 208 is shown in a cross-sectional view, specifically, in a cross-sectional view of a Y-Z cross-section (i.e., fig. 4h), to contact and electrically connect the gate 206 with the gate thickening portion 207; the connection 208 is shown in another cross-sectional view, specifically, in a cross-sectional view in an X-Z cross-section (i.e., fig. 5a below) to contact and electrically connect the gate 206 to the gate thickening 207.

In some embodiments, when the second conductive material 208 'covering the gate line spacer sidewalls is removed, the second conductive material 208' in the third GAP3 is guaranteed to be removed together, forming the connection portion 208 filled in the second GAP 2.

In practical applications, the second conductive material 208' covering the sidewalls of the gate line spacer grooves may be removed by dry etching, such as ion milling, plasma etching, reactive ion etching, laser ablation, or the like.

Referring to fig. 4h, since the connection portion 208 is close to the gate line spacer GLS and the width of the second GAP2 (see fig. 4f) is such that the second width W2 is smaller than the first width W1 of the first GAP1 (see fig. 4c), the conductive material for filling the second GAP2 is less than the electrical material for filling the first GAP1, that is, the filling amount of the conductive material for forming the connection portion 208 is less than the filling amount of the conductive material for forming the gate 206 or the gate connection portion 207, so that the formation of the connection portion 208 is easier and the filling amount of the conductive material is less than that for forming the gate 206 or the gate connection portion 207. The amount of the second conductive material 208' formed on the gate line spacer trench sidewalls is relatively reduced. The process of the filling amount of the second width W2 reduces the additional filling amount (the filling amount of the first width W1 minus the filling amount of the second width W2) with respect to the process of the filling amount of the first width W1, thereby reducing the removal amount of the second conductive material 208' (refer to fig. 4g) formed at the gate line bank sidewall. The second conductive material 208 'covering the side wall of the grid line separation groove is removed completely, the problem of residue of the second conductive material 208' is solved, the grid leakage current of the finally formed memory is prevented, and the performance of the memory is ensured. Meanwhile, the amount of the second conductive material 208' removed to cover the gate line spacer sidewalls is controlled to be the fifth width W5 (refer to fig. 4g) or a process control margin (not shown) is added on the basis of the fifth width W5, and the process control margin (not shown) may be 0 to 0.5 times the fifth width W5; the connecting portion 208 remaining in the second GAP2 is prevented from being over-etched, resulting in the width of the connecting portion 208 being smaller than the second width W2, resulting in the problem of poor electrical connection between the gate thickened portion 207 and the gate 206 of the finally formed memory, thereby ensuring the performance of the memory.

Referring to fig. 4i, in some embodiments, after forming a connection 208 electrically connecting the gate 206 and the gate thickening 207, the method further comprises:

forming a second dielectric layer 209 on the side wall and the bottom of the gate line separation groove GLS;

the gate line spacer GLS formed with the second dielectric layer is filled with a semiconductor material 210.

In some embodiments, the sides and bottom of the gate line spacer GLS are covered with a second dielectric layer 209, and the second dielectric layer 209 is filled with a semiconductor material 210. In practical applications, the second dielectric layer 209 is used for insulation, and the material may include an insulating material, such as silicon oxide. The semiconductor material 210 filled in the second dielectric layer 209 may include a semiconductor material, such as polysilicon, and the semiconductor material 210 is in a floating state, so as to achieve shielding and anti-interference effects.

Referring to fig. 4j, in some embodiments, after forming the second dielectric layer 209 in the gate line spacer GLS and filling the second dielectric layer with the semiconductor material 210, the method further includes:

a contact CT is formed in the third dielectric layer 205 on the gate thickening 207 in the step structure SS.

In some embodiments, a gate contact hole (not shown) is formed after etching the third dielectric layer 205, the gate contact hole (not shown) penetrates through the third dielectric layer 205 to the gate thickening layer 207, and a gate contact hole (not shown) of the gate thickening layer 207 is formed. A fill conductive material is deposited in the gate contact holes (not shown) to form contacts CT which serve as the lead-out lines for the gate 206.

In some embodiments, the gate 206 is electrically connected to the contact CT through the connection portion 208 and the gate extension portion 207, forming a lead-out of the gate 206 via the contact CT.

FIGS. 5a and 5B are cross-sectional views taken along A-A and B-B, respectively, of FIG. 4 j; fig. 5c is a schematic cross-sectional view of a Y-Z cross section, and in detail, fig. 5c shows cross-sectional structure information between two adjacent gate line spacer GLSs in the memory. Further, the lead-out structure of the gate 206 is depicted from a cross-sectional schematic view of a plurality of different cross-sections.

Referring to fig. 5a and 5b, in the cross-sectional views of the X-Z section, the gate 206 at the portion exposed on the step top surface SS-T is electrically connected to the connection portion 208 near the gate line spacer GLS; referring to fig. 5c, in a cross-sectional view of the Y-Z section, a connection portion 208 near the gate line spacing groove GLS is electrically connected to the gate thickening portion 207, the gate thickening portion 207 is electrically connected to the contact CT, and the gate 206 is led out through the connection portion 208 and the gate thickening portion 207 via the contact CT.

Fig. 6a to 6h are schematic cross-sectional views illustrating another memory forming process according to another embodiment of the invention. In detail, fig. 6a to 6h are schematic diagrams illustrating a structure forming process of a channel hole of a core region in a memory along a second direction and a third direction cross section (Y-Z cross section in the drawings) or a first direction and a third direction (X-Z cross section in the drawings) according to another embodiment of the present invention.

In some embodiments, the stack structure ST includes at least a first sub-stack structure ST1 and a second sub-stack structure ST 2;

the forming of the channel hole CH through the stack structure ST includes:

forming a first sub-channel hole CH1 penetrating the first sub-stacked structure ST 1;

forming a second sub-channel hole CH2 penetrating the second sub-stacked structure ST 2; the second sub-channel hole CH2 and the first sub-channel hole CH1, which are in communication, form the channel hole CH.

Referring to fig. 6a, a first sub-stack structure ST1 is formed on a substrate, a first sub-stack structure ST1 is provided, which is composed of a substrate structure SUBS and a plurality of insulating layers 201 and sacrificial layers 202 formed on the substrate structure SUBS in an alternating stacking manner, and the process of forming the substrate structure SUBS and the first sub-stack structure ST1 may refer to fig. 2 and fig. 3a, and a method for forming the stack structure ST in step S10 and the structure thereof are performed, which are not described herein again.

Referring to fig. 6b, a first sub-channel hole CH1 is formed through the first sub-stack structure ST 1. The first sub-channel hole CH1 penetrating the stack structure ST1 may be formed by an etching process. In practical applications, a plurality of first sub-channel holes CH1 are formed in the stacked structure SS by using a dry etching process, such as ion milling, plasma etching, reactive ion etching, laser ablation, etc.

Referring to fig. 6c, an etch stop material layer 217' is formed in the first sub-channel hole CH 1. The etch barrier material layer 217' filling the first sub-channel hole CH1 may be formed by a vapor deposition process of plasma enhanced chemistry. In practice, the etch stop material layer 217' comprises carbon or polysilicon.

Referring to fig. 6d, the etching barrier material layer 217 'may be planarized by a chemical mechanical polishing process to remove the etching barrier material layer 217' on the surface of the insulating layer 201 on the top surface of the first sub-channel hole CH1, thereby forming the etching barrier layer 217 filled in the first sub-channel hole CH 1.

Referring to fig. 6e, a second sub-stacked structure ST2 is formed on the first sub-stacked structure ST1, a second sub-stacked structure ST2 is formed by a plurality of insulating layers 201 and sacrificial layers 202 alternately stacked on the first sub-stacked structure ST1, a forming process of the second sub-stacked structure ST2 may refer to fig. 2 and fig. 3a, and a forming method and a forming structure of the stacked structure ST including the plurality of insulating layers 201 and the sacrificial layers 202 alternately stacked in step S10 are performed, which are not described herein again.

Referring to fig. 6f, a first sub-channel hole CH2 is formed through the second sub-stacked structure ST 2. The second sub-channel hole CH2 penetrating the stack structure ST2 may be formed by an etching process. In practical applications, a plurality of second sub-channel holes CH2 are formed in the stacked structure SS by using a dry etching process, such as ion milling, plasma etching, reactive ion etching, laser ablation, etc.

The etch stopper 217 filled in the first sub-channel hole CH1 is removed. Forming a second sub-channel hole CH2 penetrating the second sub-stacked structure ST 2; the second sub-channel hole CH2 and the first sub-channel hole CH1, which are in communication, form the channel hole CH.

Referring to fig. 6g to 6h, a channel structure CHs is formed in the channel hole CH.

In some embodiments, the stack structure ST further includes:

forming a channel hole CH penetrating through the stacked structure ST, wherein a first dielectric material layer 211 is formed on the wall of the channel hole CH, and the dielectric constant range of the first dielectric material layer 211 is more than 3.9; a memory structure is formed in the channel hole CH of the first dielectric material layer 211.

Referring to fig. 6g, in some embodiments, when the channel hole CH is formed, a first dielectric material layer 211 is formed, and the first dielectric material layer 211 covers the sidewall and the bottom surface of the channel hole CH. That is, a first dielectric material layer 211 is formed between the ONOP film and the sidewall and bottom surface of the trench hole, and the first dielectric material layer 211 has a dielectric material with a dielectric constant larger than that of SiO2 (k-3.9) for ensuring a sufficient gate dielectric thickness, reducing leakage current, and reducing impurity diffusion.

Assuming that the first dielectric material layer 211 is not formed when the channel hole CH is formed, that is, the first dielectric material layer 211 is not formed between the ONOP film and the sidewall and the bottom of the channel hole, the first dielectric material layer 211 is formed in a subsequent process, for example, after step S40 is performed, before step S50 is performed, the first dielectric material layer 211 is required to be formed, the first dielectric material layer 211 formed at this time wraps around the surface of the insulating layer 201 and the first thickening layer 203, and the first dielectric material layer 211 wrapped around the surface of the first thickening layer 203 blocks the etching of the first portion 2031 in the subsequent process, which results in that the second GAP2 cannot be formed or the first dielectric material layer 211 in the space of the second GAP2 cannot be removed even if the second GAP2 is formed, which finally results in that the connection portion 208 cannot be formed or the connection portion 208 is isolated by the first dielectric material layer 211, causing the first layer of dielectric material 211 to cut off the current path between the connection 208 and the gate 206, the connection 208 and the gate thickening 207. Therefore, it is necessary to form the first dielectric material layer 211 when the channel hole CH is formed, i.e., to form the first dielectric material layer 211 between the ONOP film and the wall of the channel hole.

Referring to fig. 6h, in some embodiments, the channel structure CHS includes a first dielectric material layer 211, a blocking dielectric layer 212, a charge trapping layer 213, a tunneling dielectric layer 214, a channel layer 215, and a filling layer 216, which are sequentially stacked along a radial direction of the channel hole. In practical applications, the first dielectric material layer 211, the blocking dielectric layer 212, the charge trapping layer 213, the tunneling dielectric layer 214, and the channel layer 215 are formed along the sidewall of the storage channel holeAnd the bottom surface are formed in this order. The first dielectric material layer 211 is used for ensuring that the gate dielectric thickness is thick enough, reducing leakage current and impurity diffusion, and the material has a dielectric material with a dielectric constant larger than that of SiO2 (k-3.9), and comprises Ta₂O₅(k～26)、TiO₂(k～80)、ZrO₂(k～25)、Al₂O₃(k-9), HfSiOx (k-4-25) and HfO₂(k-25); the blocking dielectric layer 212 is used for blocking the outflow of charges in the storage layer, and the material can be silicon oxide; the charge trapping layer 213 is used to trap and store charges, and may be silicon nitride; electrons from channel layer 215 may tunnel through tunnel dielectric layer 214 into charge-trapping layer 213, and tunnel dielectric layer 214 may be silicon oxide; the channel layer 215 material may be polysilicon; the fill layer 216 may be silicon oxide or polysilicon, which is equivalent to the fill layer being replaced by the same material as the channel layer 215. In some embodiments, blocking dielectric layer 212, charge-trapping layer 213, tunnel dielectric layer 214, and channel layer 215 are referred to as an ONOP film.

It should be noted that fig. 6a to 6f show that the channel hole CH in the memory provided in the embodiment of the present invention is formed by etching a first sub-channel hole CH1 and a second sub-channel hole CH2 twice, respectively, and the first sub-channel hole CH1 is communicated with the second sub-channel hole CH 2; it should not be construed as limiting the process of forming the channel hole CH. In practical applications, the process of forming the channel hole CH is not limited to this, and may be selected according to actual needs.

The channel hole CH may also be a channel hole CH formed by one-time etching, and the detailed steps thereof are similar to those in fig. 6a to 6b, and are not repeated here, but only the key steps in the forming process are briefly described: specifically, a stacked structure ST is formed on a substrate, a substrate structure SUBS and a stacked structure ST formed by a plurality of insulating layers 201 and sacrificial layers 202 which are alternately stacked and arranged are provided on the substrate structure SUBS; a channel hole CH is formed through the stack structure ST. After the channel hole CH is formed, a channel structure CHs is formed in the channel hole CH, and the detailed steps thereof are similar to those in fig. 6g to 6h, and are not described again here.

It should be noted that although an exemplary method of forming a memory is described herein, it is understood that one or more steps may be omitted from the formation of such a memory. For example, in practical applications, a corresponding mask layer is generated before an etching process is performed.

Based on the above method for manufacturing a memory, an embodiment of the present invention further provides a memory, with reference to fig. 5a to 5c, where the memory includes:

a stack structure ST; the stacked structure ST comprises a plurality of insulating layers 201 and gates 206 which are alternately stacked, and a stepped structure SS is formed on at least one side of the stacked structure; the top surface SS-T of each layer of the ladder structure SS is a gate 206;

a gate line spacer GLS penetrating the stack structure ST; the gate line spacer GLS divides the stack structure ST into two regions; and

a gate thickening structure located on each step in each region; the gate thickening structures on adjacent layers of the step are electrically isolated from each other; the gate thickening structure includes a connecting portion 208 and a first thickening portion 2032 arranged side by side on each step, and a gate thickening portion 207 covering the connecting portion 208 and the first thickening portion 2032; the connecting part is at least arranged at one side close to the grid line separation groove GLS;

the gate 206 and the gate thickening 207 comprise a first conductive material 206 ', the connection 208 comprises a second conductive material 208', and the gate 206 and the gate thickening 207 are electrically connected by the connection 208.

In some embodiments, there is a grid line spacer GLS on both sides of the region; the connection portion 208 includes a first connection portion and a second connection portion, which are respectively disposed at one side close to the corresponding side gate line spacing groove GLS; the first thickened portion 2032 is provided between the first connection portion and the second connection portion.

In some embodiments, a grid line spacer GLS is present on one side of the region; the connecting portion 208 is disposed at a side close to the side grid line separating groove GLS; the first thickened portion 2032 is provided on a side away from the side-gate line-dividing groove GLS.

In some embodiments, the memory further comprises a plurality of gate conductive contacts CT; the plurality of gate conductive contacts CT are respectively in contact with and electrically connected to the gate thickening structures on the corresponding layer steps.

Referring to fig. 5b and 5c, in practical applications, the gate thickening portion 207 and the gate 206 on which the top surface SS-T of the step is located are electrically connected by a connection portion 208 in the third direction. Specifically, the connection portion 208 is divided into a first connection portion and a second connection portion by the first thickened portion 2032, that is, the first thickened portion 2032 is disposed between the first connection portion and the second connection portion or the first thickened portion 2032 is disposed at one side of the first connection portion, and the first thickened portion 2032 is far away from the gate line spacing groove GLS and the first connection portion is close to the gate line spacing groove GLS; the gate thickening portion 207 covers the connection portion 208 with the first thickening portion 2032, thus forming a gate thickening structure including: the gate thickening portion 207, the connecting portion 208, and the first thickening portion 2032 function as the gate thickening portion 207 and the connecting portion 208 are electrically connected to the gate 206, which is beneficial for connecting the gate conductive contact CT to the gate thickening layer of the gate thickening structure in the subsequent process for leading out the gate 206.

In some embodiments, a first thickened portion 2032 and a connecting portion 208 are formed on the gate 206 on which the top surface SS-T of the step is located, the gate thickened portion 207 is formed on the first thickened portion 2032 and the connecting portion 208, which is equivalent to two thickened layers formed on the gate 206 on which the top surface SS-T of the step is located, that is, the first thickened portion 2032 and the connecting portion 208 with a third thickness H3 and the gate thickened layer with a second thickness H2 are formed on the gate 206 with a first thickness H1. In practical application, the number of layers of the multilayer thickening structure is selected according to the actual requirements of the device, and is not limited to two thickening layers; meanwhile, different second thicknesses H2 and/or third thicknesses H3 can be selected according to the actual requirements of the device, so that the process window of etching a gate contact hole (not shown) can be greatly increased through different selections of the number of layers of the multilayer thickening structure and the thickness of each thickening layer, and the formation of contact CT in the subsequent process is facilitated; the situation that the wrong connection between different grid layers possibly penetrates through the grid 206 and influences the performance of the memory is avoided.

In some embodiments, the material of the intermediate first thickened portion 2032 has a different etch selectivity ratio than the material of the insulating layer 201.

In some embodiments, the insulating layer 201 comprises a first silicon oxide, the first thickening 2032 comprises a second silicon oxide; the first silicon oxide and the second silicon oxide have different physical parameters.

In some embodiments, the first conductive material 206 'and the second conductive material 208' are the same or different materials.

In some embodiments, the first conductive material 206' comprises tungsten; the material of the second conductive material 208' includes tungsten or polysilicon.

It should be noted that, the components of the memory provided in the embodiment of the present invention are already embodied in the foregoing step S10 to step S70, and are not described herein again.

It should be noted that the memory mentioned in the embodiment of the present invention may include a three-dimensional NAND type memory.

In addition, the technical solutions described in the embodiments of the present invention may be arbitrarily combined without conflict.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims

1. A memory, comprising:

2. The memory of claim 1, wherein gate line spacer trenches are present on both sides of the region; the connecting part comprises a first connecting part and a second connecting part, and the first connecting part and the second connecting part are respectively arranged at one side close to the grid line separation groove at the corresponding side; the first thickened portion is provided between the first connecting portion and the second connecting portion.

3. The memory of claim 1, wherein a gate line spacer is present on one side of the region; the connecting part is arranged at one side close to the side grid line separation groove; the first thickening part is arranged on one side far away from the side grid line separation groove.

4. The memory of claim 1, further comprising a plurality of gate conductive contacts; the plurality of gate conductive contacts are respectively in contact with and electrically connected with the gate thickening structures on the corresponding layer steps.

5. The memory of claim 1, wherein a material of the intermediate first thickening portion has a different etch selectivity ratio than a material of the insulating layer.

6. The memory of claim 5, wherein the insulating layer comprises a first silicon oxide, the first thickening comprises a second silicon oxide; the first silicon oxide and the second silicon oxide have different physical parameters.

7. The memory of claim 1, wherein the first conductive material and the second conductive material are the same or different materials.

8. The memory of claim 7, wherein the first conductive material comprises tungsten; the material of the second conductive material comprises tungsten or polysilicon.

9. A method of manufacturing a memory, comprising:

sequentially forming a first thickening layer and a second thickening layer which are stacked on the top surface of each layer of the ladder, wherein the first thickening layer and the second thickening layer on the top surface of the ladder of the adjacent layer are electrically isolated from each other;

forming a gate line isolation groove penetrating through the stacked structure;

10. The method of claim 9, wherein the removing the portion of the first thickening layer adjacent to the gate line spacer trench comprises:

11. The method of claim 10, wherein the insulating layer comprises a first silicon oxide, the first thickening layer comprises a second silicon oxide; the first silicon oxide and the second silicon oxide have different physical parameters.

12. The method of claim 9, wherein the first conductive material and the second conductive material are the same or different materials.

13. The method of manufacturing a memory according to claim 12, wherein the first conductive material comprises tungsten; the material of the second conductive material comprises tungsten or polysilicon.

14. The method of manufacturing a memory of claim 9, wherein forming the stacked first and second thickening layers comprises:

forming a first thickened material layer at least covering the step structure;

15. The method of manufacturing a memory device according to claim 9, wherein the first conductive material further covers sidewalls of the gate line spacer grooves when the first conductive material is filled in the first voids;

the method further comprises the following steps:

16. The method of claim 15, wherein portions of the insulating layer adjacent to the gate line spacer are removed together while removing portions of the first thickening layer adjacent to the gate line spacer.

17. The method of manufacturing a memory device according to claim 15, wherein when the second conductive material is filled in the second voids, the second conductive material also covers sidewalls of the gate line spacer grooves;

the method further comprises the following steps:

18. The method of manufacturing a memory of claim 9, further comprising:

forming a trench hole through the stacked structure;

19. The method of manufacturing a memory according to claim 18, wherein the stack structure includes at least a first sub-stack structure and a second sub-stack structure that are stacked;

the forming a trench hole through the stacked structure includes:

forming a first sub-channel hole through the first sub-stacked structure;

20. The method of manufacturing a memory according to claim 9, wherein after forming a connection portion that electrically connects the gate and the gate thickening portion, the method further comprises: