CN114400181A - Preparation method of semiconductor device and semiconductor device - Google Patents

Preparation method of semiconductor device and semiconductor device Download PDF

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Publication number
CN114400181A
CN114400181A CN202210061094.8A CN202210061094A CN114400181A CN 114400181 A CN114400181 A CN 114400181A CN 202210061094 A CN202210061094 A CN 202210061094A CN 114400181 A CN114400181 A CN 114400181A
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layer
gate stack
dielectric layer
semiconductor device
substrate
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张书浩
李宁
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The embodiment of the disclosure provides a preparation method of a semiconductor device, which comprises the following steps: forming a dielectric layer on a substrate; performing a first etching process on the dielectric layer to form an opening in the dielectric layer; forming a gate stack layer in the opening; and performing a second etching process on the dielectric layer to form side wall layers at two ends of the grid stacking layer.

Description

Preparation method of semiconductor device and semiconductor device
Technical Field
The present disclosure relates to the field of semiconductor manufacturing, and in particular, to a method for manufacturing a semiconductor device and a semiconductor device.
Background
Semiconductor devices, such as Dynamic Random Access Memories (DRAMs), include transistors that include gate stacks formed by sequentially depositing multiple material layers and then etching the material layers.
However, the materials of the layers are different, and during etching, the lateral etching rates of the materials of the layers are different, so that the surface of the sidewall of the finally formed gate stack layer has uneven topography, which affects the electrical performance and reliability of the device.
Disclosure of Invention
The embodiment of the disclosure provides a preparation method of a semiconductor device, which comprises the following steps: forming a dielectric layer on a substrate; performing a first etching process on the dielectric layer to form an opening in the dielectric layer; forming a gate stack layer in the opening; and performing a second etching process on the dielectric layer to form side wall layers at two ends of the grid stacking layer.
In the above scheme, the material of the dielectric layer includes an oxide, a nitride, or an oxynitride.
In the above scheme, the performing a second etching process on the dielectric layer includes:
forming a protective layer on the gate stack layer; in a direction parallel to the channel, two ends of the protective layer protrude outwards relative to two ends of the grid stacking layer;
and etching the dielectric layer by taking the protective layer as a mask to form a side wall layer, wherein the side wall layer covers the two ends of the grid stacking layer.
In the above scheme, the protective layer is a photoresist layer; forming a protective layer on the gate stack layer, comprising:
forming a photoresist layer above the gate stack layer and the dielectric layer;
and performing an exposure and development process on the photoresist material layer to form the protective layer, wherein two ends of the protective layer protrude outwards relative to two ends of the grid stacking layer.
In the above scheme, forming a gate stack layer in the opening includes:
depositing a grid stacking material layer on the dielectric layer, wherein the grid stacking material layer covers the surface of the dielectric layer and at least fills part of the opening;
and performing a planarization process on the grid stacking material layer and the dielectric layer to form a grid stacking layer positioned in the opening.
In the above scheme, the gate stack material layer includes a polysilicon material layer, a diffusion barrier material layer, and a metal material layer stacked from bottom to top.
In the above scheme, the gate stack material layer further includes a cap material layer located on the metal material layer.
In the above scheme, before forming the dielectric layer on the substrate, the method further includes: a layer of gate insulating material is formed on the substrate.
In the above scheme, after the second etching process is performed on the dielectric layer, the method further includes: and etching the grid insulating material layer to form a grid insulating layer at the bottoms of the grid stacking layer and the side wall layer, wherein two ends of the grid insulating layer are aligned with two ends of the side wall layer.
In the above scheme, after the second etching process is performed on the dielectric layer, the method further includes: and doping the substrates on two sides of the grid stacking layer to form a first source/drain region and a second source/drain region.
The disclosed embodiment also provides a semiconductor device, including:
a substrate;
the grid stacking layer is positioned on the substrate;
the side wall layer covers two ends of the grid stacking layer;
and the roughness of the surface of the grid stacking layer, which is in contact with the side wall layer, is less than 0.1.
In the above scheme, the material of the sidewall layer includes an oxide, a nitride or an oxynitride.
In the above aspect, the semiconductor device further includes: and the grid insulating layer is positioned between the grid stacking layer and the substrate and between the side wall layer and the substrate.
In the above scheme, the gate stack layer includes a polysilicon layer, an anti-diffusion barrier layer and a metal layer stacked from bottom to top.
In the above scheme, the gate stack layer further includes a cap layer, and the cap layer is located above the metal layer.
In the above aspect, the semiconductor device further includes: and the first source/drain region and the second source/drain region are positioned at two sides of the grid stacking layer.
The embodiment of the disclosure provides a preparation method of a semiconductor device and the semiconductor device, wherein the method comprises the following steps: forming a dielectric layer on a substrate; performing a first etching process on the dielectric layer to form an opening in the dielectric layer; forming a gate stack layer in the opening; and performing a second etching process on the dielectric layer to form side wall layers at two ends of the grid stacking layer. By forming the opening in the dielectric layer and filling the gate stack layer in the opening, the gate stack layer with good sidewall surface flatness can be obtained, thereby improving the electrical performance and reliability of the device. In addition, the dielectric layer is subjected to a secondary etching process to form the side wall layer, so that the forming process of the side wall layer can be simplified, and the production cost is saved.
The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the disclosure will be apparent from the description and drawings, and from the claims.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
FIG. 1 is a schematic diagram of an exemplary semiconductor device;
fig. 2 is a block flow diagram of a method of fabricating a semiconductor device provided by an embodiment of the present disclosure;
fig. 3 to 11 are process flow diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without one or more of these specific details. In other instances, well-known features of the art have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. And the discussion of a second element, component, region, layer or section does not necessarily imply that the first element, component, region, layer or section is necessarily present in the disclosure.
Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Semiconductor devices, such as DRAMs, include transistors that include a gate stack, which is typically made up of multiple layers of different materials.
Fig. 1 is a schematic diagram of an exemplary semiconductor device. As shown in fig. 1, the semiconductor device includes a substrate 10, a gate stack layer 12, and a gate insulating layer 13 between the substrate 10 and the gate stack layer 12. Optionally, the semiconductor device further includes sidewall layers 11 located at two ends of the gate stack layer 12.
The gate stack 12 is formed by stacking a plurality of different materials, and is typically formed by first depositing the materials in bulk and then etching the materials.
However, since the lateral etching rates of the materials of the gate stack layer 12 are different during etching, the flatness of the side 12b of the gate stack layer formed finally is poor, which affects the electrical performance and reliability of the semiconductor device.
Based on this, the following technical scheme of the embodiment of the disclosure is proposed:
the embodiment of the present disclosure provides a method for manufacturing a semiconductor device, as shown in fig. 2, the method includes the following steps:
step 210: forming a dielectric layer on a substrate;
step 220: performing a first etching process on the dielectric layer to form an opening in the dielectric layer;
step 230: forming a gate stack layer in the opening;
step 240: and performing a second etching process on the dielectric layer to form side wall layers at two ends of the grid stacking layer.
In the embodiment of the disclosure, by forming the opening in the dielectric layer and then filling the gate stack layer in the opening, the gate stack layer with better sidewall surface flatness can be obtained, so that the electrical performance and reliability of the device can be improved. In addition, the dielectric layer is subjected to a secondary etching process to form the side wall layer, so that the forming process of the side wall layer can be simplified, and the production cost is saved.
In order to make the aforementioned objects, features and advantages of the present disclosure more comprehensible, embodiments accompanying the present disclosure are described in detail below. In describing the embodiments of the present disclosure in detail, the drawings are not to be taken as a general scale, and the drawings are for illustrative purposes only and should not be taken as limiting the scope of the present disclosure.
Fig. 3 to 11 are process flow diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.
First, as shown in fig. 3, a dielectric layer 21a is formed on the substrate 20 in step 210.
The material of the dielectric layer 21a includes oxide, nitride or oxynitride, such as: silicon oxide, silicon nitride, silicon oxynitride, etc., but not limited thereto, other insulating materials may also be used as the material of the dielectric layer 21a according to the embodiment of the present disclosure, such as: silicon carbide.
The substrate may be a semiconductor substrate; specifically including at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In a specific embodiment, the substrate is a silicon substrate.
It is understood that before forming the dielectric layer 21a on the substrate 20, the method further comprises: a layer of gate insulating material 23a is formed on the substrate 20. The material of the gate insulating material layer 23a may be oxide, nitride, oxynitride, or the like, such as: silicon oxide, silicon nitride, silicon oxynitride, or the like.
It is understood that, in some embodiments, other structures, such as a silicon germanium layer, etc., may be further included between the substrate 20 and the gate insulating material layer 23a, and are not particularly limited herein.
The formation of the dielectric layer 21a and the gate insulating material layer 23a may be formed using one or more thin film deposition processes; the plurality of thin film deposition processes include, but are not limited to, a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, an Atomic Layer Deposition (ALD) process, or a combination thereof.
Then, as shown in fig. 4, step 220 is performed to perform a first etching process on the dielectric layer 21a to form an opening TH1 in the dielectric layer 21 a. The dielectric layer 21a is made of a single material, and when the opening TH1 is formed by etching, there is no difference in etching rate, so that the formed opening TH1 has a smooth side wall, and further, a gate stack layer formed in the opening TH1 subsequently has a side wall surface with good flatness, thereby improving the electrical performance and reliability of a semiconductor device.
In actual process, an opening TH1 is formed in the dielectric layer 21a, including: forming a photoresist layer (not shown) on the dielectric layer 21 a; next, performing processes such as exposure and development on the photoresist layer to form a mask pattern (not shown) on the dielectric layer 21 a; finally, an etching process is performed on the dielectric layer 21a by using the mask pattern as a mask, so as to form an opening TH1 in the dielectric layer 21a, as shown in fig. 4.
Here, the opening TH1 is formed above the gate insulating material layer 23a, and the etching process for forming the opening TH1 may be a dry etching process or a wet etching process, which is not limited herein.
Next, as shown in fig. 5 and 6, step 230 is performed to form a gate stack layer 22 in the opening TH 1.
In some embodiments, forming the gate stack layer 22 in the opening TH1 includes:
depositing a gate stack material layer 22a on the dielectric layer 21a, wherein the gate stack material layer 22a covers a surface of the dielectric layer 21a and at least fills a portion of the opening TH1, as shown in fig. 5;
a planarization process is performed on the gate stack material layer 22a and the dielectric layer 21a to form the gate stack layer 22 located in the opening TH1, as shown in fig. 6.
Here, the gate stack material layer 22a includes a polysilicon material layer 221a, a diffusion barrier material layer 222a, and a metal material layer 223a stacked from bottom to top. Wherein, the material of the diffusion barrier preventing material layer 222a may include, but is not limited to, titanium nitride, etc.; the material of the metal material layer 223a includes, but is not limited to, metal tungsten, metal silicide (TiSi)2、CoSi2And NiSi2Etc.) and tungsten nitride, etc.
Optionally, the gate stack material layer 22a further includes a cap material layer 224a on the metal material layer 223 a. The cap material layer 224a may be used to protect the gate stack material layer 22a from oxidation, nitridation or contamination during subsequent processes. The material of the cap material layer 224a includes, but is not limited to, oxide, nitride, oxynitride or other insulating material; specifically, the material of the cap material layer 224a may be silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide.
The formation of the gate stack material layer 22a may be formed using one or more thin film deposition processes; the plurality of thin film deposition processes include, but are not limited to, a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, an Atomic Layer Deposition (ALD) process, or a combination thereof.
The planarization process can be specifically a chemical grinding process or a mechanical polishing process; after the planarization process, the gate stack layer 22 is formed in the opening TH1, and the gate stack layer 22 includes a polysilicon layer 221, a diffusion barrier layer 222, a metal layer 223, and a capping layer 224, which are sequentially stacked from bottom to top.
In the embodiment of the disclosure, the sidewall surface of the opening TH1 is smooth, so that the sidewall surface of the gate stack layer 22 finally formed therein has better flatness. Specifically, the roughness Ra of the surface of the gate stack layer 22 in contact with the dielectric layers 21a on both sides of the gate stack layer 22 is 0.1 or less, for example, 0.09, 0.08, 0.06, 0.05, or the like.
Finally, as shown in fig. 7 to 9, step 240 is performed to perform a second etching process on the dielectric layer 21a to form sidewall layers 21 at two ends of the gate stack layer 22.
In an actual process, performing a second etching process on the dielectric layer, wherein the second etching process comprises the following steps:
forming a protective layer 26 on the gate stack layer 22, as shown in fig. 7 to 8; wherein, in a direction parallel to the channel, two ends of the protection layer 26 protrude outward relative to two ends of the gate stack layer 22;
and etching the dielectric layer 21a by using the protection layer 26 as a mask to form a sidewall layer 21, specifically referring to fig. 9, where the sidewall layer 21 covers the two ends of the gate stack layer 22.
In some embodiments, the protective layer is a photoresist layer 26; forming a protective layer 26 on the gate stack layer 22, including:
forming a photoresist layer 26a over the gate stack layer 22 and the dielectric layer 21a, as shown in fig. 7;
an exposure and development process is performed on the photoresist layer 26a to form the protection layer 26, and two ends of the protection layer 26 protrude outward relative to two ends of the gate stack layer 22, as shown in fig. 8.
It is understood that the material of the sidewall layer 21 is the same as the material of the dielectric layer 21a, and in particular, the material of the sidewall layer 21 may include, but is not limited to, an oxide, a nitride, an oxynitride, or the like.
In the related art, after the gate stack layer is formed, sidewall material layers are formed on two sides of the gate stack layer, and then the sidewall material layers are etched to form sidewall layers. In the embodiment of the present disclosure, after the gate stack layer is formed, the dielectric layers on both sides of the gate stack layer are subjected to the second etching process to directly form the sidewall layer without depositing a sidewall material layer in advance. The preparation method of the semiconductor device provided by the embodiment of the disclosure simplifies the forming process of the side wall layer, and is beneficial to reducing the production cost.
According to some embodiments, after performing the second etching process on the dielectric layer 21a, the method further includes: etching the gate insulating material layer 23a to form a gate insulating layer 23 at the bottom of the gate stack layer 22 and the sidewall layer 21, wherein two ends of the gate insulating layer 23 are aligned with two ends of the sidewall layer 21, as shown in fig. 10.
Optionally, after performing the second etching process on the dielectric layer 21a, the method further includes: the substrate 20 on both sides of the gate stack 22 is doped to form a first source/drain region 24 and a second source/drain region 25 of the first conductivity type, as shown in fig. 11.
In some specific embodiments, the first conductivity type may be n-type, and the dopant selected for doping includes at least one of arsenic, phosphorus, and antimony; but not limited thereto, the first conductivity type may also be p-type, and the dopant selected for doping includes at least one of boron, indium and gallium.
Optionally, a contact structure, such as a bit line contact (not shown), may be further formed on the first source/drain region 24, so as to form an electrical connection between the first source/drain region 24 and a bit line (not shown); at the same time, a storage node contact (not shown) is formed on the second source/drain region 25 to make an electrical connection between the second source/drain region 25 and an information storage structure (not shown). Without limitation, the positions of the bit line contacts (not shown) and the storage node contacts (not shown) may be interchanged, for example, the bit line contacts (not shown) may be formed on the second source/drain regions 25, so as to form an electrical connection between the second source/drain regions 25 and the bit lines (not shown); at the same time, a storage node contact (not shown) is formed on the first source/drain region 24 to make an electrical connection between the first source/drain region 24 and an information storage structure (not shown).
The type of the specific contact structure formed on the first source/drain region 24 and the second source/drain region 25 can be flexibly selected according to actual requirements, and the disclosure is not limited to this.
The embodiment of the present disclosure also provides a semiconductor device, as shown in fig. 11, the device includes:
a substrate 20;
a gate stack layer 22 on the substrate 20;
a sidewall layer 21 covering both ends of the gate stack layer 22;
wherein, the roughness of the surface of the gate stack layer 22 contacting the sidewall layer 21 is below 0.1.
It is understood that the gate stack is made up of multiple material layers. In the prior art, the gate stack layer is usually formed by etching, but due to different etching rates of the multilayer materials, the finally formed gate stack layer has poor flatness on the surface in contact with the side wall layer, that is, the roughness is large, and the electrical performance and reliability of the semiconductor device are affected.
In the embodiment of the disclosure, when the gate stack layer is formed, a dielectric layer is formed on a substrate; then, forming an opening TH1 in the dielectric layer by etching; then forming a gate stack material layer in the opening TH1 and on the dielectric layer, wherein the gate stack material layer may specifically include a polysilicon material layer, a diffusion barrier material layer, a metal material layer, a cap material layer, and the like; and finally, performing a planarization process on the grid stacking material layer to obtain the grid stacking layer. In the above process, the dielectric layer is made of a single material, so that there is no difference in etching rate when the opening TH1 is formed by etching, and the opening TH1 has smooth sidewalls, so that the roughness of the gate stack layer formed in the opening TH1 is below 0.1, for example, 0.09, 0.08, 0.06, or 0.05, which may improve the electrical performance and reliability of the finally formed semiconductor device.
With continued reference to fig. 11, the substrate 20 may be a semiconductor substrate; specifically including at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In a specific embodiment, the substrate 20 is a silicon substrate.
It is understood that the semiconductor device further includes: a gate insulating layer 23, wherein the gate insulating layer 23 is located between the gate stack layer 22 and the substrate 20, and between the sidewall layer 21 and the substrate 20.
It is understood that, in some embodiments, other structures, such as a silicon germanium layer, etc., may be further included between the substrate 20 and the gate insulating layer 23, and are not particularly limited herein.
In an actual process, the formation of the gate insulating layer 23 may be formed using one or more thin film deposition processes; the plurality of thin film deposition processes include, but are not limited to, a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, an Atomic Layer Deposition (ALD) process, or a combination thereof.
As shown in fig. 11, the gate stack layer 22 is located above the gate insulating layer 23. In some specific embodiments, the gate stack layer 22 includes a polysilicon layer 221, an anti-diffusion barrier layer 222 and a metal layer 223 stacked from bottom to top. Wherein, the material of the diffusion barrier layer 222 may include, but is not limited to, titanium nitride, etc.; the material of the metal layer 223 includes, but is not limited to, metal tungsten, metal silicide (TiSi)2、CoSi2And NISi2Etc.) and tungsten nitride, etc.
Optionally, the gate stack layer 22 further includes a cap layer 224, and the cap layer 224 is located above the metal layer 223.
The cap layer 224 may be used to maintain electrical insulation between the gate stack 22 and other structures formed on the substrate, and the material of the cap layer 224 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and other insulating materials.
The material of the sidewall layer 21 includes, but is not limited to, oxide, nitride or oxynitride, such as: silicon oxide, silicon nitride, silicon oxynitride, and the like, but not limited thereto, any insulating material satisfying the conditions may be used as the sidewall layer according to the embodiment of the present disclosure.
In the embodiment of the present disclosure, the method for forming the sidewall layer includes: after the grid stacking layer is formed, the dielectric layers on two sides of the grid stacking layer are subjected to a second etching process, and then the side wall layer can be directly formed. Compared with the method for forming the side wall layer by regrowing a new dielectric layer and then etching after forming the gate stack layer in the related art, the method simplifies the forming process of the side wall layer and is beneficial to reducing the production cost.
In actual processing, the gate stack layer may be formed using one or more thin film deposition processes; the plurality of thin film deposition processes include, but are not limited to, a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, an Atomic Layer Deposition (ALD) process, or a combination thereof.
In some embodiments, as shown in fig. 11, the semiconductor device further includes: a first source/drain region 24 and a second source/drain region 25 located at both sides of the gate stack layer 22.
In particular, the first source/drain region 24 and the second source/drain region 25 may have a first conductivity type. More specifically, the first conductivity type may be n-type, and the doping agent selected for doping includes at least one of arsenic, phosphorus, and antimony; but not limited thereto, the first conductivity type may be p-type, and the doping thereof may be performed by using a dopant selected from the group consisting of at least one of boron, indium and gallium.
Optionally, a contact structure (not shown), such as a bit line contact (not shown), is further disposed on the first source/drain region 24, so as to form an electrical connection between the first source/drain region 24 and a bit line (not shown); meanwhile, a storage node contact (not shown) is provided on the second source/drain region 25 to electrically connect the second source/drain region 25 with an information storage structure (not shown).
The specific positions of the bit line contact (not shown) and the storage node contact (not shown) may be interchanged, for example, a bit line contact (not shown) is provided on the second source/drain region 25, so as to form an electrical connection between the second source/drain region 25 and a bit line (not shown); meanwhile, a storage node contact (not shown) is provided on the first source/drain region 24 to electrically connect the first source/drain region 24 with an information storage structure (not shown).
The type of the specific contact structure disposed on the first source/drain region 24 and the second source/drain region 25 can be flexibly selected according to actual requirements, and the disclosure is not limited to this.
In summary, in the embodiments of the present disclosure, when forming the gate stack layer, a method of forming an opening with smooth sidewall in the dielectric layer first and then filling the gate stack layer in the opening is adopted, so that the gate stack layer with good sidewall surface flatness can be obtained, and thus the electrical performance and reliability of the semiconductor device are improved. In addition, the second etching process is performed on the dielectric layer to form the side wall layer, so that the forming process of the side wall layer is simplified, and the production cost is reduced.
It should be noted that the method for manufacturing a semiconductor device provided in the embodiments of the present disclosure may be applied to a DRAM structure or other semiconductor devices, and is not limited herein. The embodiment of the semiconductor device preparation method provided by the disclosure and the embodiment of the semiconductor device belong to the same concept; the technical features of the technical means described in the embodiments may be arbitrarily combined without conflict.
The above description is only exemplary of the present disclosure and should not be taken as limiting the scope of the present disclosure, which is intended to cover any variations, modifications, equivalents, and improvements included within the spirit and scope of the present disclosure.

Claims (16)

1. A method of fabricating a semiconductor device, the method comprising:
forming a dielectric layer on a substrate;
performing a first etching process on the dielectric layer to form an opening in the dielectric layer;
forming a gate stack layer in the opening;
and performing a second etching process on the dielectric layer to form side wall layers at two ends of the grid stacking layer.
2. The method of claim 1, wherein the material of the dielectric layer comprises an oxide, a nitride, or an oxynitride.
3. The method of claim 1 or 2, wherein performing a second etching process on the dielectric layer comprises:
forming a protective layer on the gate stack layer; in a direction parallel to the channel, two ends of the protective layer protrude outwards relative to two ends of the grid stacking layer;
and etching the dielectric layer by taking the protective layer as a mask to form a side wall layer, wherein the side wall layer covers the two ends of the grid stacking layer.
4. The method of claim 3, wherein the protective layer is a photoresist layer; forming a protective layer on the gate stack layer, comprising:
forming a photoresist layer above the gate stack layer and the dielectric layer;
and performing an exposure and development process on the photoresist material layer to form the protective layer, wherein two ends of the protective layer protrude outwards relative to two ends of the grid stacking layer.
5. The method of claim 1, wherein forming a gate stack layer within the opening comprises:
depositing a grid stacking material layer on the dielectric layer, wherein the grid stacking material layer covers the surface of the dielectric layer and at least fills part of the opening;
and performing a planarization process on the grid stacking material layer and the dielectric layer to form a grid stacking layer positioned in the opening.
6. The method of claim 5, wherein the gate stack material layer comprises a bottom-up stacked polysilicon material layer, a diffusion barrier material layer, and a metal material layer.
7. The method of claim 6, wherein the gate stack material layer further comprises a cap material layer on the metal material layer.
8. The method of claim 1, wherein prior to forming the dielectric layer on the substrate, the method further comprises: a layer of gate insulating material is formed on the substrate.
9. The method of claim 8, wherein after performing the second etching process on the dielectric layer, the method further comprises: and etching the grid insulating material layer to form a grid insulating layer at the bottoms of the grid stacking layer and the side wall layer, wherein two ends of the grid insulating layer are aligned with two ends of the side wall layer.
10. The method of claim 1, wherein after performing the second etching process on the dielectric layer, the method further comprises: and doping the substrates on two sides of the grid stacking layer to form a first source/drain region and a second source/drain region.
11. A semiconductor device, comprising:
a substrate;
the grid stacking layer is positioned on the substrate;
the side wall layer covers two ends of the grid stacking layer;
and the roughness of the surface of the grid stacking layer, which is in contact with the side wall layer, is less than 0.1.
12. The semiconductor device according to claim 11, wherein a material of the sidewall layer comprises an oxide, a nitride, or an oxynitride.
13. The semiconductor device according to claim 11, further comprising: and the grid insulating layer is positioned between the grid stacking layer and the substrate and between the side wall layer and the substrate.
14. The semiconductor device according to claim 11 or 13, wherein the gate stack layer comprises a polysilicon layer, a diffusion-preventing barrier layer and a metal layer stacked from bottom to top.
15. The semiconductor device of claim 14, wherein the gate stack further comprises a cap layer, the cap layer being located above the metal layer.
16. The semiconductor device according to claim 11, further comprising: and the first source/drain region and the second source/drain region are positioned at two sides of the grid stacking layer.
CN202210061094.8A 2022-01-19 2022-01-19 Preparation method of semiconductor device and semiconductor device Pending CN114400181A (en)

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