CN114399468A - Circuit board pin defect identification method based on characteristic self-learning - Google Patents
Circuit board pin defect identification method based on characteristic self-learning Download PDFInfo
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- 230000007547 defect Effects 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000003466 welding Methods 0.000 claims abstract description 99
- 239000011159 matrix material Substances 0.000 claims abstract description 59
- 238000005476 soldering Methods 0.000 claims abstract description 38
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 32
- 229910000679 solder Inorganic materials 0.000 claims description 13
- 238000004364 calculation method Methods 0.000 claims description 6
- 238000012937 correction Methods 0.000 claims description 6
- 238000012546 transfer Methods 0.000 claims description 6
- 230000002950 deficient Effects 0.000 claims description 5
- 238000000605 extraction Methods 0.000 claims description 5
- PXFBZOLANLWPMH-UHFFFAOYSA-N 16-Epiaffinine Natural products C1C(C2=CC=CC=C2N2)=C2C(=O)CC2C(=CC)CN(C)C1C2CO PXFBZOLANLWPMH-UHFFFAOYSA-N 0.000 claims description 3
- 238000012216 screening Methods 0.000 claims description 3
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- 208000013715 atelosteogenesis type I Diseases 0.000 description 16
- 238000001514 detection method Methods 0.000 description 4
- 238000007689 inspection Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- G06T7/00—Image analysis
- G06T7/0002—Inspection of images, e.g. flaw detection
- G06T7/0004—Industrial image inspection
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T3/00—Geometric image transformations in the plane of the image
- G06T3/14—Transformations for image registration, e.g. adjusting or mapping for alignment of images
- G06T3/147—Transformations for image registration, e.g. adjusting or mapping for alignment of images using affine transformations
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
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- G06T7/30—Determination of transform parameters for the alignment of images, i.e. image registration
- G06T7/33—Determination of transform parameters for the alignment of images, i.e. image registration using feature-based methods
- G06T7/337—Determination of transform parameters for the alignment of images, i.e. image registration using feature-based methods involving reference images or patches
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- G—PHYSICS
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- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
- G06T7/70—Determining position or orientation of objects or cameras
- G06T7/73—Determining position or orientation of objects or cameras using feature-based methods
- G06T7/74—Determining position or orientation of objects or cameras using feature-based methods involving reference images or patches
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- G—PHYSICS
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- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/20—Special algorithmic details
- G06T2207/20092—Interactive image processing based on input by user
- G06T2207/20104—Interactive definition of region of interest [ROI]
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- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/30—Subject of image; Context of image processing
- G06T2207/30108—Industrial image inspection
- G06T2207/30141—Printed circuit board [PCB]
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Abstract
The application discloses a circuit board pin defect identification method based on feature self-learning, which comprises the following steps: acquiring an AOI color image and a corresponding configuration file of a standard circuit board; establishing a welding spot position model of a standard circuit board and a standard soldering tin characteristic matrix X; obtaining a chip sub-picture of a chip in a circuit board to be tested; extracting corresponding sub-welding point pictures from each chip sub-picture based on the welding point position model, and calculating the soldering tin height value of each pixel point in each sub-welding point picture to form a soldering tin characteristic matrix Y of the corresponding welding point; and calculating a normalized geometric intersection coefficient gamma of the soldering tin characteristic matrix Y and the corresponding standard soldering tin characteristic matrix X, and judging whether the welding spots have defects one by one according to a geometric intersection coefficient threshold value. The invention can effectively reduce the omission factor, improve the efficiency and the accuracy and reduce the workload of manually searching for the defects.
Description
Technical Field
The invention belongs to the technical field of circuit board detection, and relates to a circuit board pin defect identification method based on feature self-learning.
Background
The circuit board can make the circuit miniaturized, direct-viewing, play important role to fixed circuit's batch production and optimization electrical apparatus overall arrangement.
Most circuit board manufacturers in China adopt a method of manually checking the defects of the circuit boards by using a magnifying glass or a projector. Because the labor intensity of manual inspection is high, the eyes are easy to fatigue, and the missing inspection rate is very high. And with the development of miniaturization and digitalization of electronic products, the circuit board also develops towards high density and high precision, and the manual inspection method is basically not realized. For a circuit board with higher density and precision (0.12-0.10 mm), the inspection cannot be carried out at all. The detection means is lagged behind, so that the product percent of pass of domestic multilayer boards (8-12 layers) is only 50-60%.
In addition, the circuit board production base also adopts AOI equipment to detect the circuit board defects, but still has a plurality of defects, and the more serious defect is a missing detection, namely, the defect is not detected. Defects in the type of weld by AOI equipment are probably undetectable with a probability of > 60%. That is, assuming that there are 100 defects in the circuit board, 60 AOIs could not be found and could pass the past. Manually checking only the AOI detected abnormality, and not checking the condition that the detection is not carried out. This defect can only be discovered later by electrical measurements and fed back into the AOI pipeline. The false alarm condition is low in severity, but is frequent, most of the false alarm condition is caused by fonts, and the false alarm condition can be eliminated manually.
Disclosure of Invention
In order to overcome the defects in the prior art, the application provides a circuit board pin defect identification method based on feature self-learning.
In order to achieve the above purpose, the invention adopts the following technical scheme:
the method for identifying the pin defect of the circuit board based on the characteristic self-learning comprises the following steps:
step 1: acquiring a standard circuit board AOI color image and a corresponding configuration file, which correspond to a circuit board to be tested and are used for feature self-learning, wherein the standard circuit board AOI color image comprises the model number and the position of a chip on the circuit board;
step 2: establishing a standard welding spot model of a chip in an AOI color image of a standard circuit board, wherein the standard welding spot model comprises a welding spot position model and a standard soldering tin characteristic matrix X;
and step 3: acquiring an AOI color image of a circuit board to be detected, and performing SIFT image comparison on the AOI color image of a standard circuit board to obtain chip sub-pictures of chips in the circuit board to be detected, wherein each chip sub-picture comprises a single chip and all corresponding welding points of the single chip;
and 4, step 4: extracting corresponding sub-welding point pictures from each chip sub-picture based on the welding point position model in the step 2, wherein each sub-welding point picture comprises a single welding point, calculating the soldering tin height value of each pixel point in each sub-welding point picture, and forming a soldering tin feature matrix Y of the corresponding welding point;
and 5: and calculating a normalized geometric intersection coefficient gamma of the soldering tin characteristic matrix Y and the corresponding standard soldering tin characteristic matrix X, and judging whether the welding spots have defects one by one according to a geometric intersection coefficient threshold value.
The invention further comprises the following preferred embodiments:
preferably, step 2 specifically comprises:
step 2.1: carrying out chip area external expansion by taking the center of the chip as the center to obtain a chip matrix of a corresponding phase model;
step 2.2: searching welding spots in the area expanded in the step 2.1, acquiring ROI (region of interest) welding spot areas based on color information during welding spot searching, and extracting a welding spot matrix to further obtain a welding spot position model of the chip of the type;
step 2.3: acquiring all welding spot matrixes in the expanded region, wherein all welding spot matrixes are non-defective welding spots, and calculating the soldering tin height value of each pixel point in the welding spot matrixes;
step 2.4: and calculating the average value of the soldering tin height values of all the pixel points in the same soldering point matrix to form a standard soldering tin characteristic matrix X of the soldering point.
Preferably, in step 2.1, the chip is located in the center, and the rectangular area where the chip is located is expanded by 1.5 times to obtain the chip matrix.
Preferably, in step 2.2, the RGB image is converted into an HSV image, and a blue portion in the HSV image is extracted as a solder joint matrix, so as to obtain a position of the solder joint matrix relative to the chip matrix and a solder joint bounding box, and the solder joint position model is stored as a solder joint position model of the chip of the model; the welding spot surrounding box is a rectangular frame containing welding spots and a chip.
Preferably, in step 2.2, the extraction range is: h: (100, 124), S: (43, 255), V: (46, 255).
Preferably, in step 2.3, the calculation formula of the solder height value is as follows:
height＝B-G/5.-R/3.0
b, G, R represents the component value of B, the component value of G, and the component value of R of the corresponding pixel RGB.
Preferably, the SIFT image calibration in step 3 specifically includes:
(1) respectively calculating SIFT feature points of the image to be detected and the template image;
(2) converting the SIFT feature points into a description matrix for Flann feature matching;
(3) after feature matching, through RANSAC screening, calculating a transfer correction matrix;
(4) and performing affine transformation on the image to be measured according to the transfer correction matrix to finish calibration.
Preferably, in step 4, the sub-welding-point picture extracting process is as follows:
(1) obtaining a chip sub-picture containing a single chip and all corresponding welding spots thereof according to the configuration file;
(2) and acquiring pictures of each welding point one by one according to the positions of the welding points in the welding point position model relative to the chip, wherein the pictures are sub welding point pictures.
Preferably, in step 5, the normalized geometric intersection coefficient γ is calculated by the formula:
wherein, XmnIs an element of a standard solder feature matrix, YmnFor the elements of the solder feature matrix to be tested, sbs represents the absolute value, and m and n represent the rows and columns of the matrix.
Preferably, according to calculation experience, the threshold value is 0.7, and when the normalized geometric intersection coefficient gamma is less than 0.7, the corresponding solder joint is considered to be defective.
The beneficial effect that this application reached:
the method identifies the defects by using the self-learning image processing technology, has feasibility of application, can effectively reduce the omission factor, improve the efficiency and the accuracy rate, and reduce the workload of manually searching the defects; meanwhile, the problem that the PCB is measured until the next process can be avoided, the problem can be effectively found earlier, and the problem is solved.
Drawings
FIG. 1 is a flow chart of the method of the present invention;
FIG. 2 is a diagram of a process embodying the present invention.
Detailed Description
The present application is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present application is not limited thereby.
As shown in fig. 1 and 2, the method for identifying pin defects of a circuit board based on feature self-learning of the present invention comprises the following steps:
step 1: acquiring a standard circuit board AOI color image and a corresponding configuration file, which correspond to a circuit board to be tested and are used for feature self-learning, wherein the standard circuit board AOI color image comprises the model number of a chip on the circuit board, the position of the chip and the like;
step 2: the method comprises the following steps of establishing a standard welding spot model of a chip in an AOI color image of a standard circuit board, wherein the standard welding spot model comprises a welding spot position model and a standard soldering tin characteristic matrix X, and specifically comprises the following steps:
step 2.1: carrying out chip area external expansion by taking the center of the chip as the center to obtain a chip matrix;
in specific implementation, the center of the chip is used as the center, and the rectangular area where the chip is located is expanded by 1.5 times to obtain a chip matrix.
For example, the chip height is 50, the chip width is 100, a rectangular area where the chip is located is formed, the center of the area is the center of the chip, and the area is expanded by 1.5 times, so that an area containing a welding spot is obtained: the height was 75 and the width was 150, resulting in a chip matrix.
Step 2.2: searching welding spots in the area expanded in the step 2.1, acquiring ROI (region of interest) welding spot areas based on color information during welding spot searching, and extracting a welding spot matrix to further obtain a welding spot position model of the chip of the type;
considering that the blue soldering tin part is an important position for ensuring the quality of the welding spot, extracting the blue part to obtain an ROI (region of interest);
specifically, the RGB image is converted into an HSV image, a blue part in the HSV image is extracted to serve as a welding spot matrix, and then the position of the welding spot matrix relative to the chip matrix and a welding spot surrounding box are obtained and stored as a welding spot position model of the chip of the model.
The welding spot surrounding box is a rectangular frame containing welding spots and a chip.
The extraction range is as follows: h: (100, 124), S: (43, 255), V: (46, 255).
Step 2.3: acquiring all welding spot matrixes in the expanded region, wherein all welding spot matrixes are non-defective welding spots, and calculating the soldering tin height value of each pixel point in the welding spot matrixes;
the calculation formula of the soldering tin height value is as follows:
height＝B-G/5.-R/3.0
b, G, R represents the component value of B, the component value of G, and the component value of R of the corresponding pixel RGB.
Step 2.4: and calculating the average value of the soldering tin height values of all the pixel points in the same soldering point matrix to form a standard soldering tin characteristic matrix X of the soldering point.
The same chip pin pad is similar in height.
And step 3: acquiring an AOI color image of a circuit board to be detected, performing SIFT image comparison on the AOI color image of the circuit board to be detected and an AOI color image of a standard circuit board, and acquiring a chip sub-picture of a chip in the circuit board to be detected, wherein if the circuit board comprises a plurality of chips, step 3 is to acquire a plurality of chip sub-pictures, and each chip sub-picture comprises a single chip and all welding points corresponding to the single chip;
the SIFT image is accurate, and specifically comprises the following steps:
(1) respectively calculating SIFT feature points of the image to be detected and the template image;
(2) converting the SIFT feature points into a description matrix for Flann feature matching;
(3) after feature matching, through RANSAC screening, calculating a transfer correction matrix;
(4) and performing affine transformation on the image to be measured according to the transfer correction matrix to finish calibration.
And 4, step 4: extracting corresponding sub-welding point pictures from each chip sub-picture based on the welding point position model in the step 2, wherein each sub-welding point picture comprises a single welding point, calculating the soldering tin height value of each pixel point in each sub-welding point picture, and forming a soldering tin feature matrix Y of the corresponding welding point;
the extraction process of the sub-welding point picture comprises the following steps:
(1) obtaining a chip sub-picture containing a single chip and all corresponding welding spots thereof according to the configuration file;
(2) and acquiring pictures of each welding point one by one according to the positions of the welding points in the welding point position model relative to the chip, wherein the pictures are sub welding point pictures.
It is understood that the location of each die and its corresponding pad are contained in the pad placement model file.
And 5: and calculating a normalized geometric intersection coefficient gamma of the soldering tin characteristic matrix Y and the corresponding standard soldering tin characteristic matrix X, and judging whether the welding spots have defects one by one according to a geometric intersection coefficient threshold value.
The normalized geometric intersection coefficient γ is calculated as:
wherein, XmnIs an element of a standard solder feature matrix, YmnFor the elements of the solder feature matrix to be tested, sbs represents the absolute value, and m and n represent the rows and columns of the matrix.
The factor is approximately 1, indicating that the two weld points are more similar.
According to the calculation experience, the threshold value is set to be 0.7, and when the normalized geometric intersection coefficient gamma is less than 0.7, the corresponding welding spot is considered to be defective.
Step 6: and when a new circuit board is obtained, repeating the step 1-2 so as to continuously learn and update the model.
The method identifies the defects by using the self-learning image processing technology, has feasibility of application, can effectively reduce the omission factor, improve the efficiency and the accuracy rate, and reduce the workload of manually searching the defects; meanwhile, the problem that the PCB is measured until the next process can be avoided, the problem can be effectively found earlier, and the problem is solved.
The present applicant has described and illustrated embodiments of the present invention in detail with reference to the accompanying drawings, but it should be understood by those skilled in the art that the above embodiments are merely preferred embodiments of the present invention, and the detailed description is only for the purpose of helping the reader to better understand the spirit of the present invention, and not for limiting the scope of the present invention, and on the contrary, any improvement or modification made based on the spirit of the present invention should fall within the scope of the present invention.
Claims (10)
1. The method for identifying the pin defect of the circuit board based on the characteristic self-learning is characterized by comprising the following steps:
the method comprises the following steps:
step 1: acquiring a standard circuit board AOI color image and a corresponding configuration file, which correspond to a circuit board to be tested and are used for feature self-learning, wherein the standard circuit board AOI color image comprises the model number and the position of a chip on the circuit board;
step 2: establishing a standard welding spot model of a chip in an AOI color image of a standard circuit board, wherein the standard welding spot model comprises a welding spot position model and a standard soldering tin characteristic matrix X;
and step 3: acquiring an AOI color image of a circuit board to be detected, and performing SIFT image comparison on the AOI color image of a standard circuit board to obtain chip sub-pictures of chips in the circuit board to be detected, wherein each chip sub-picture comprises a single chip and all corresponding welding points of the single chip;
and 4, step 4: extracting corresponding sub-welding point pictures from each chip sub-picture based on the welding point position model in the step 2, wherein each sub-welding point picture comprises a single welding point, calculating the soldering tin height value of each pixel point in each sub-welding point picture, and forming a soldering tin feature matrix Y of the corresponding welding point;
and 5: and calculating a normalized geometric intersection coefficient gamma of the soldering tin characteristic matrix Y and the corresponding standard soldering tin characteristic matrix X, and judging whether the welding spots have defects one by one according to a geometric intersection coefficient threshold value.
2. The feature self-learning based circuit board pin defect identification method according to claim 1, wherein:
the step 2 specifically comprises the following steps:
step 2.1: carrying out chip area external expansion by taking the center of the chip as the center to obtain a chip matrix of a corresponding phase model;
step 2.2: searching welding spots in the area expanded in the step 2.1, acquiring ROI (region of interest) welding spot areas based on color information during welding spot searching, and extracting a welding spot matrix to further obtain a welding spot position model of the chip of the type;
step 2.3: acquiring all welding spot matrixes in the expanded region, and calculating the soldering tin height value of each pixel point in the welding spot matrixes;
step 2.4: and calculating the average value of the soldering tin height values of all the pixel points in the same soldering point matrix to form a standard soldering tin characteristic matrix X of the soldering point.
3. The feature self-learning based circuit board pin defect identification method according to claim 2, characterized in that:
in step 2.1, the center of the chip is taken as the center, and the rectangular area where the chip is located is expanded by 1.5 times to obtain a chip matrix.
4. The feature self-learning based circuit board pin defect identification method according to claim 2, characterized in that:
in the step 2.2, the RGB image is converted into an HSV image, a blue part in the HSV image is extracted to serve as a welding spot matrix, and then the position of the welding spot matrix relative to the chip matrix and a welding spot surrounding box are obtained and stored as a welding spot position model of the chip of the model; the welding spot surrounding box is a rectangular frame containing welding spots and a chip.
5. The feature self-learning based circuit board pin defect identification method according to claim 2, characterized in that:
in step 2.2, the extraction range is as follows: h: (100, 124), S: (43, 255), V: (46, 255).
6. The feature self-learning based circuit board pin defect identification method according to claim 2, characterized in that:
in step 2.3, the calculation formula of the soldering tin height value is as follows:
height＝B-G/5.-R/3.0
b, G, R represents the component value of B, the component value of G, and the component value of R of the corresponding pixel RGB.
7. The feature self-learning based circuit board pin defect identification method according to claim 1, wherein:
step 3, the SIFT image is accurate, and the method specifically comprises the following steps:
(1) respectively calculating SIFT feature points of the image to be detected and the template image;
(2) converting the SIFT feature points into a description matrix for Flann feature matching;
(3) after feature matching, through RANSAC screening, calculating a transfer correction matrix;
(4) and performing affine transformation on the image to be measured according to the transfer correction matrix to finish calibration.
8. The feature self-learning based circuit board pin defect identification method according to claim 1, wherein:
in step 4, the sub-welding point picture extraction process is as follows:
(1) obtaining a chip sub-picture containing a single chip and all corresponding welding spots thereof according to the configuration file;
(2) and acquiring pictures of each welding point one by one according to the positions of the welding points in the welding point position model relative to the chip, wherein the pictures are sub welding point pictures.
9. The feature self-learning based circuit board pin defect identification method according to claim 1, wherein:
in step 5, the normalized geometric intersection coefficient γ is calculated by the following formula:
wherein, XmnIs an element of a standard solder feature matrix, YmnFor the elements of the solder feature matrix to be tested, sbs represents the absolute value, and m and n represent the rows and columns of the matrix.
10. The feature self-learning based circuit board pin defect identification method according to claim 9, wherein:
according to calculation experience, the threshold value is 0.7, and when the normalized geometric intersection coefficient gamma is less than 0.7, the corresponding welding spot is considered to be defective.
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