CN114388685A

CN114388685A - Wafer-level packaging structure of sensor and packaging method thereof

Info

Publication number: CN114388685A
Application number: CN202011119450.4A
Authority: CN
Inventors: 狄云翔; 刘孟彬; 韩凤芹
Original assignee: Ningbo Semiconductor International Corp
Current assignee: Ningbo Semiconductor International Corp
Priority date: 2020-10-19
Filing date: 2020-10-19
Publication date: 2022-04-22

Abstract

The invention discloses a wafer level packaging structure of a sensor and a packaging method thereof, wherein the wafer level packaging method of the sensor comprises the following steps: providing a first substrate, wherein the first substrate comprises a base and a dielectric layer arranged on the surface of the base; forming a detection structure layer on a first substrate, wherein the detection structure layer comprises a detection structure; providing a second substrate, wherein the second substrate is provided with a first cavity; bonding a second substrate on the first substrate, wherein the first cavity faces the detection structure layer; removing the substrate; providing a third substrate; at least part of cofferdams are arranged on one side of the detection structure layer far away from the second substrate and/or the third substrate; and a third substrate is bonded on one side of the detection structure layer, which is far away from the second substrate, through a cofferdam, the cofferdam and the third substrate enclose a second cavity, and the second cavity faces the detection structure layer.

Description

Wafer-level packaging structure of sensor and packaging method thereof

Technical Field

The invention relates to the field of semiconductor device manufacturing, in particular to a wafer level packaging structure of a sensor and a packaging method thereof.

Background

With the continuous development of MEMS sensing technology, sensor packaging is pursuing higher performance. Sensors using thermopiles as core components have been widely used in the fields of infrared temperature measurement, infrared detection, infrared alarm, infrared imaging, infrared guidance, and the like. The basic principle of the sensor is that according to the Seebeck effect of thermoelectric materials, a plurality of pairs of thermocouples are generally connected into a stack to convert infrared radiation signals absorbed by the outside into electric signals, so that the temperature is measured. Of the two ends, the end that absorbs infrared light is called the hot zone and the substrate end is called the cold zone. Conventional sensors mostly use TO packages. Along with the increasing demand of electronic products such as mobile phones and wearable devices on integrated temperature measurement chips, the miniaturization demand is also put forward on the size of the chips.

However, in the conventional TO packaging process, a thermopile chip is attached TO a packaging base, a chip bonding pad is connected with a pin of the base through a wire bonding, and finally a cap and the base are hermetically packaged, so that the packaging size is large (5 × 5 × 3mm), the pin is long, and the application of the thermopile chip in miniaturized equipment is severely restricted.

Therefore, how to improve the packaging method of the sensor, reduce the packaging size of the chip, and meet the application requirements of the chip in miniaturized devices is a problem at present.

Disclosure of Invention

The invention aims to provide a wafer level packaging structure of a sensor and a packaging method thereof, which can solve the problems that the packaging process precision of the sensor is poor, the packaging size is large, and the application requirement in miniaturized equipment cannot be met.

In order to achieve the above object, the present invention provides a wafer level packaging method for a sensor, comprising:

providing a first substrate, wherein the first substrate comprises a base and a dielectric layer arranged on the surface of the base;

forming a detection structure layer on the first substrate, wherein the detection structure layer comprises a detection structure;

providing a second substrate having a first cavity;

bonding the second substrate on the first substrate, wherein the first cavity faces the detection structure layer;

removing the substrate;

providing a third substrate;

at least part of cofferdams are arranged on one side of the detection structure layer far away from the second substrate and/or the third substrate;

and bonding the third substrate on one side of the detection structure layer far away from the second substrate through the cofferdam, wherein the cofferdam and the third substrate enclose a second cavity facing the detection structure layer.

The invention also provides a wafer level packaging structure of the sensor, which comprises:

a second substrate having a first cavity;

a detection structure layer comprising at least a detection structure at least partially located over the first cavity;

the dielectric layer covers the surface, far away from the second substrate, of the detection structure layer;

the metal cofferdam is positioned above the dielectric layer;

the third substrate is positioned above the metal cofferdam, the metal cofferdam and the third substrate enclose a second cavity, and the second cavity encloses at least part of the detection structure;

and the electric connection structure leads out the electrical property of the detection structure.

The invention has the beneficial effects that:

a second cavity is formed by bonding a third substrate on the prepared detection structure layer in a surrounding mode, an electric connection structure is arranged, and the electric property of the thermocouple is led out to complete packaging of the detection structure layer, so that the packaging size is greatly reduced, and the application requirement of the sensor in miniaturized equipment is met. The second cavity is not etched on the third substrate, but is bonded to form a cavity in addition, so that the problems that the back cavity etching process is not well controlled and the size precision of the cavity is poor are solved, and the measurement precision of the sensor is improved. The wafer level manufacturing process has the advantages of short period, high efficiency and low cost.

Furthermore, the first substrate comprises top silicon, and the top silicon is made of monocrystalline silicon, so that the top silicon of the SOI substrate can be directly utilized to form the first thermoelectric strip and/or the second thermoelectric strip of the thermocouple, the manufacturing process is simplified, and the packaging efficiency is improved.

Furthermore, the electric connection structure is divided into a first connection part, a second connection part and a third connection part, and the three parts are formed in different manufacturing processes respectively, so that the process difficulty is reduced, and the yield and the reliability of wafer-level packaging of the sensor are improved.

Furthermore, a cofferdam made of a metal material is formed, and a second cavity is formed by bonding a third substrate on the cofferdam, so that the air tightness and the structural strength of the wafer-level packaging of the sensor are improved, the temperature concentration and interference shielding of the sensor are facilitated, and the quality, the reliability and the yield of the wafer-level packaging of the sensor are improved.

Furthermore, a flat layer is arranged and flattened, the second substrate and the detection structure layer are bonded by a fusion bonding method, the alignment precision of bonding and the structural strength of wafer-level packaging of the sensor are improved, the manufacturing process is simplified, and fusion bonded bonding materials are easy to obtain, so that the packaging efficiency is improved, and the packaging cost is reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 to 20 are schematic structural diagrams illustrating different steps of a wafer level packaging method for a sensor according to embodiment 1 of the present invention.

Description of reference numerals:

10-a substrate; 11-a dielectric layer; 111-a second via; 21-a first thermoelectric material layer; 211-a first thermoelectric strip; 22-an isolation layer; 221-a first trench; 23-a second thermoelectric strip; 24-a passivation layer; 25-a planarization layer; 26-a second substrate; 27-a first cavity; 30-a first connection; 31-cofferdam; 32-a third substrate; 321-a second via; 33-a second cavity; 34-a second connection; 35-an insulating layer; 351-a third via; 36-third connection.

Detailed Description

The invention is described in further detail below with reference to the figures and specific examples. The advantages and features of the present invention will become more apparent from the following description and drawings, it being understood, however, that the concepts of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. The drawings are in simplified form and are not to scale, but are provided for convenience and clarity in describing embodiments of the invention.

The terms "first," "second," and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other sequences than described or illustrated herein. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method. Although elements in one drawing may be readily identified as such in other drawings, the present disclosure does not identify each element as being identical to each other in every drawing for clarity of description.

The invention provides a wafer level packaging method of a sensor, wherein a detection structure is used as a sensing structure of the sensor, such as an MEMS cantilever structure, a thermopile structure, a filter structure and the like.

Example 1

The embodiment 1 of the invention provides a wafer-level packaging method of a sensor, which comprises the following steps:

s01: providing a first substrate, wherein the first substrate comprises a base 10 and a dielectric layer 11 arranged on the surface of the base 10;

s02: forming a detection structure layer on a first substrate, wherein the detection structure layer comprises a detection structure;

s03: providing a second substrate 26, the second substrate 26 having a first cavity 27; bonding a second substrate 26 on the first substrate, the first cavity 27 facing the detection structure layer;

s04: removing the substrate 10;

s05: providing a third substrate 32, providing at least part of a cofferdam 31 on the side of the detection structure layer far away from the second substrate 26 and/or on the third substrate 32, bonding the third substrate 32 on the side of the detection structure layer far away from the second substrate 26 through the cofferdam 31, and enclosing a second cavity 33 by the cofferdam 31 and the third substrate 32, wherein the second cavity 33 faces the detection structure layer.

It should be noted that the above step S0N does not represent a sequential order.

The wafer level packaging method of the sensor will be described with reference to fig. 1 to 20. Fig. 1 to 20 are schematic structural diagrams corresponding to different steps of a wafer level packaging method of a sensor according to an embodiment of the invention.

Referring to fig. 1 to 2, step S01 is performed: a first substrate is provided, which includes a base 10 and a dielectric layer 11 disposed on a surface of the base 10.

Specifically, the material of the substrate 10 includes a semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III/V compound semiconductors, a Double Side Polished silicon wafer (DSP), a ceramic substrate 10 such as alumina, a quartz or glass substrate 10, and the like.

In this embodiment, the substrate 10 is made of silicon, referring to fig. 2, after the substrate 10 is formed, a dielectric layer 11 is formed on the substrate 10, the dielectric layer 11 is made of silicon nitride or silicon oxide, the dielectric layer 11 serves as a stop layer for a subsequent thinning process, and serves to support a structure subsequently formed on the dielectric layer 11 after the thinning process, and also serves to isolate the dielectric, and also serves to insulate heat, so that temperature exchange between a subsequently formed structural layer and the outside in a direction close to the dielectric layer 11 is prevented, sensitivity and accuracy of the sensor are improved, and quality and reliability of the sensor are ensured. The dielectric layer 11 may be formed by a chemical vapor deposition or physical vapor deposition or atomic layer deposition method. The dielectric layer 11 may be formed on the substrate 10 by thermal oxidation, deposition, with a contact interface.

In other embodiments, the first substrate further includes a top silicon layer, the top silicon layer is located on the dielectric layer 11, and the top silicon layer is made of monocrystalline silicon. In this case, the first substrate constitutes an SOI substrate, and parasitic latch-up in the circuit can be eliminated.

Referring to fig. 3 to 8, step S02 is performed: a detection structure layer is formed on the first substrate and comprises a detection structure. In this embodiment, the detection structure layer may cover the surface of the first substrate, and in other embodiments, only the functional region of the first substrate may be covered with the detection structure layer, that is, the detection structure layer exposes a portion of the first substrate.

In the present embodiment, the sensing structure includes at least some thermocouples including the first thermoelectric strip 211 and the second thermoelectric strip 23 connected to each other, and the thermocouples measure the amount of infrared rays incident on the infrared sensor by manufacturing a circuit using the first thermoelectric strip 211 and the second thermoelectric strip 23 and generating a thermal electromotive force by generating a temperature difference using the principle of the "seebeck effect", and in the present embodiment, a plurality of thermocouples are connected in series to increase the sensitivity of the sensor, thereby improving the quality and reliability of the sensor. The first thermoelectric strip 211 and the second thermoelectric strip 23 may be arranged in parallel on the same horizontal plane, or may be stacked in a direction perpendicular to the first substrate, a portion of the first thermoelectric strip 211 and the second thermoelectric strip 23 connected to each other serves as a hot end of the thermocouple, and a portion of the thermocouple far away from the hot end is a cold end. In one embodiment, there are a plurality of thermocouples, and the plurality of thermocouples are arranged in an array. In other embodiments, the detection structure as a sensing structure of the sensor may be a MEMS cantilever structure, a thermopile structure, a filter structure, etc., and may further include at least a portion of a thermistor or at least a portion of a photoresistor.

In this embodiment, the method for forming the detection structure layer includes: referring to fig. 3, a first thermoelectric material layer 21 is formed on a first substrate; referring to fig. 4, the first thermoelectric material layer 21 is patterned to form a plurality of discrete first thermoelectric strips 211; referring to fig. 5, forming an isolation layer 22 on the first substrate and the first thermoelectric bar 211 to cover the first thermoelectric bar 211 and the first substrate, referring to fig. 6, patterning the isolation layer 22 to form a first trench 221, wherein the first trench 221 penetrates through the isolation layer 22 and exposes a portion of the surface of the first thermoelectric bar 211; referring to fig. 7, a second thermoelectric material layer is formed on the separation layer 22 and the first thermoelectric bars 211, the second thermoelectric material layer is patterned to form a plurality of discrete second thermoelectric bars 23, and the second thermoelectric bars 23 and the corresponding first thermoelectric bars 211 are electrically connected to each other through the first trenches 221. The material combination of the first thermoelectric strip 211 and the second thermoelectric strip 23 includes: p-type and n-type single crystal silicon, single crystal silicon and polycrystalline silicon, single crystal silicon and metal, polycrystalline silicon and metal, p-type polycrystalline silicon and n-type polycrystalline silicon, and the metal includes aluminum, copper, gold, titanium, or tungsten. The material of the isolation layer 22 includes dielectric materials such as silicon dioxide (SiO2), silicon nitride (Si3N4), and aluminum oxide (Al2O 3). When the isolation layer 22 is silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), it may be formed by a deposition process. The first thermoelectric material layer 21 and/or the second thermoelectric material layer may be formed by physical vapor deposition such as magnetron sputtering or evaporation, or chemical vapor deposition. The method of patterning the first thermoelectric material layer 21, the isolation layer 22, and the second thermoelectric material layer includes a dry etching process including, but not limited to, Reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser cutting.

In this embodiment, the number of the first thermoelectric strips 211 is equal to that of the second thermoelectric strips 23, the second thermoelectric strips 23 are electrically connected with the corresponding first thermoelectric strips 211 to form a plurality of thermocouples, the plurality of thermocouples are connected in series, the first thermoelectric strips 211 are made of polysilicon, and the second thermoelectric strips 23 are made of metal. In other embodiments, when the material of the thermocouple includes metal, the first thermoelectric strip 211 and the second thermoelectric strip 23 are directly connected to each other, and when the material of the thermocouple does not include metal, the first thermoelectric strip 211 and the second thermoelectric strip 23 are connected to each other through a metal material such as aluminum, copper, gold, titanium, or tungsten. In another embodiment, the first thermoelectric bar 211 and/or the second thermoelectric bar 23 are formed by patterning the top silicon of the SOI substrate, which simplifies the manufacturing process and improves the packaging efficiency.

Referring to fig. 8, in the present embodiment, after forming the thermocouple, forming a passivation layer 24 covering the thermocouple, wherein the passivation layer 24 is made of a single layer of silicon nitride, silicon dioxide, phosphosilicate glass, borophosphosilicate glass, or polyimide film, or a stacked insulating film formed of the single layer of silicon nitride, silicon dioxide, phosphosilicate glass, borophosphosilicate glass, or polyimide film. The passivation layer 24 may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, laser ablation deposition, or molecular beam deposition. The passivation layer 24 can serve as a dielectric isolation layer and also can serve as an infrared absorption layer, and heat generated by infrared absorption is effectively transferred to the detection structure layer, so that the device performance is improved.

Referring to fig. 9 to 10, step S03 is performed: providing a second substrate 26, the second substrate 26 having a first cavity 27; a second substrate 26 is bonded to the first substrate with the first cavity 27 facing the detection structure layer.

The material of the second substrate 26 refers to the material of the base 10 of the first substrate, in this embodiment, the material of the second substrate 26 is a semiconductor material, and is capable of transmitting infrared rays, so that the device performance is improved. In other embodiments, the second substrate may also be an optical material such as glass, optical filter, lens, etc., or a polymer material such as a dry film, molding compound, etc.

In the present embodiment, the first cavity 27 is formed by an etching process, and the bottom surface of the first cavity 27 is rectangular, but in other embodiments of the present invention, the bottom surface of the first cavity 27 may also be circular, oval, or polygonal except rectangular, such as pentagonal, hexagonal, etc. In the present embodiment, the first cavity 27 surrounds the thermocouple at the hot end portion, so that the first cavity 27 is formed to improve the transmittance of infrared rays, and also plays a role in heat insulation, thereby preventing the detection structure layer from exchanging with the external temperature in the direction close to the passivation layer 24, and thus improving the device performance.

In this embodiment, the detection structure layer covers the surface of the first substrate, and the second substrate is bonded to the detection structure layer on the first substrate. In other embodiments, a second substrate may be bonded to the exposed surface of the first substrate of the detection structure layer.

In this embodiment, the method for bonding the second substrate 26 and the detection structure layer includes forming a flat layer 25 on the detection structure layer, the second substrate 26 is fusion bonded to the flat layer 25, and the material of the flat layer 25 includes: silicon oxide, silicon nitride or silicon oxynitride, the planarization layer 25 is planarized prior to fusion bonding, and the first cavity 27 faces the thermocouple after fusion bonding. A flat layer 25 is formed on the detection structure layer and is subjected to planarization treatment, and then the second substrate 26 and the detection structure layer are bonded by a fusion bonding method, so that the alignment precision of bonding and the structural strength of wafer-level packaging of the sensor are improved, the manufacturing process is simplified, and fusion bonded bonding materials are easy to obtain, so that the packaging efficiency is improved, and the packaging cost is reduced.

Referring to fig. 11, step S04 is performed: the substrate 10 is removed. The dielectric layer 11 is exposed after the substrate 10 is removed.

In this embodiment, the substrate 10 is removed by etching or mechanical polishing, and the dielectric layer 11 is used as a stop layer of the polishing process to prevent excessive polishing. In other examples, a temporary bonding layer is further disposed between the substrate 10 and the dielectric layer 11, and the substrate 10 may be removed by etching the temporary bonding layer, which facilitates rapid peeling of the substrate 10 and improves process efficiency. In another example, the position of the temporary bonding layer may be replaced with a thermal expansion tape, which is peeled off the substrate 10 by heating in such a manner that the thermal expansion tape loses adhesiveness.

Referring to fig. 12 to 14, step S05 is performed: providing a third substrate 32, providing at least part of a cofferdam 31 on the side of the detection structure layer far away from the second substrate 26 and/or on the third substrate 32, bonding the third substrate 32 on the side of the detection structure layer far away from the second substrate 26 through the cofferdam 31, and enclosing a second cavity 33 by the cofferdam 31 and the third substrate 32, wherein the second cavity 33 faces the detection structure layer.

The material of the third substrate 32 refers to the material of the base 10 of the first substrate, and is not described in detail here.

Referring to fig. 12, a dam 31 may be formed on the third substrate 32, or referring to fig. 13, the dam 31 may be formed on the side of the detection structure layer away from the second substrate 26, or a part of the dam 31 is formed on the third substrate 32 and a part of the dam 31 is formed on the side of the detection structure layer away from the second substrate 26. In this embodiment, the dam 31 is formed on the side of the dielectric layer 11 away from the second substrate 26. The material of the bank 31 includes a dry film, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, ethyl silicate, polysilicon, a single layer of aluminum, titanium, nickel, gold, chromium, copper, or platinum, an alloy, or a laminated film thereof. In this embodiment, the material of the dam 31 is metal, a metal film layer is formed on a surface of the dielectric layer 11 away from the second substrate 26, and then the dam 31 is formed by an etching process, where the shape of the dam 31 may be a ring shape or a polygon. In this embodiment, the width between the inner surface and the outer surface of the dam 31 satisfies the support of the second cavity, and the height of the dam 31 ranges from 1 micron to 20 microns, such as 5 microns, 10 microns, and 15 microns. The cofferdam in the range can support the second cavity, reduce temperature loss, prevent corrosion or oxidation of the cofferdam in the environment and improve the reliability of the product. A dam 31 is located outside at least part of the thermocouples, surrounding at least part of the thermocouples.

In other embodiments, the material of the dam 31 is a photo-etching material, such as a dry film, the dam 31 is formed by a film-coating process, and the dam 31 is formed on the third substrate 32, so that the processes of forming the third substrate 32 and the dam 31 can be performed separately from the process of forming the detection structure layer, thereby improving the packaging efficiency.

In other embodiments, the third substrate 32 further includes a third cavity, the bank 31 surrounds the third cavity, the forming process of the third cavity refers to the forming process of the first cavity 27, and the distance from the detection structure layer to the bottom of the third cavity is 10 micrometers to 200 micrometers, such as 50 micrometers, 100 micrometers, 150 micrometers, and the like. The third cavity is formed to better play a role in heat insulation, prevent the detection structure layer from exchanging with the outside temperature in the direction close to the medium layer 11, and ensure the quality and the reliability of the sensor.

In other embodiments, the second cavity 33 is formed in the third substrate 32, and the sidewall of the second cavity 33 serves as at least a portion of the dam 31, and at least a portion of the dam 31 is made of the same material as the third substrate 32, so that the process of forming the dam 31 is simplified by directly forming the second cavity 33 on the third substrate 32, and the packaging efficiency is improved.

Referring to fig. 14, in the present embodiment, a metal bonding process is applied, and a third substrate 32 is bonded on the side of the dielectric layer 11 away from the second substrate 26 through a dam 31, the dam 31 and the third substrate 32 enclose a second cavity 33, and the second cavity 33 encloses a hot end portion thermocouple. The shape of the bottom surface of the second cavity 33 may be circular, elliptical, or polygonal other than rectangular, such as pentagonal, hexagonal, etc. The second cavity 33 is used for heat insulation, and the medium layer 11 is matched to prevent the detection structure layer from exchanging with the external temperature in the direction close to the medium layer 11, so that the quality and the reliability of the sensor are ensured. In addition, the cofferdam 31 made of metal is formed, the third substrate 32 is bonded on the cofferdam 31, and the second cavity 33 is formed, so that the air tightness and the structural strength of the wafer-level packaging of the sensor are improved, the temperature concentration and the interference shielding of the sensor are facilitated, and the quality, the reliability and the yield of the wafer-level packaging of the sensor are improved. Moreover, the second cavity 33 is not etched on the substrate 10, but is bonded and enclosed into a cavity through the cofferdam 31, so that the problems that the back cavity etching process is not well controlled and the size precision of the cavity is poor are solved, and the measurement precision of the sensor can be improved.

Referring to fig. 15 to 20, in the present embodiment, the method further includes: and forming an electric connection structure, wherein the electric connection structure leads out the electrical property of the detection structure layer.

In this embodiment, the method for forming the electrical connection structure includes: after removing the substrate 10, patterning the dielectric layer 11, forming a first through hole, forming a first connection portion 30 electrically connecting the thermocouple and penetrating the first through hole; bonding the third substrate 32; patterning the third substrate 32 to form a second via hole 321, forming a second connection portion 34 electrically connecting the first connection portion 30 and penetrating the second via hole 321; after the second connection portion 34 is formed, a third connection portion 36 is formed to electrically connect the second connection portion 34, and the electrical connection structure includes the first connection portion 30, the second connection portion 34, and the third connection portion 36. The material of the electrical connection structure includes: polysilicon, a single layer of aluminum, titanium, nickel, gold, chromium, copper, or platinum, an alloy, or a laminated film thereof. In this embodiment, there are two electrical connection structures, and they are isolated from each other.

Referring to fig. 15, after the substrate 10 is removed and before the second cavity 33 is formed, the dielectric layer 11 is etched by an etching process to form a first via, which is not limited in shape and may be a circular via or a square via. In this embodiment, there are two first through holes, and the first through holes penetrate through the dielectric layer 11 and respectively expose a portion of the surface of the first thermoelectric bar 211. In other embodiments, the first via exposes a portion of the surface of the first thermoelectric bar 211 and a portion of the surface of the second thermoelectric bar 23, respectively.

Referring to fig. 13, a layer of electrically connecting structure material is formed on the dielectric layer 11, the first through hole is filled and covers the dielectric layer 11, the first connection portion 30 is formed by patterning, and the first connection portion 30 fills the first through hole and protrudes from the surface of the dielectric layer 11. In this embodiment, the width of the first connection portion 30 is the same as that of the first through hole, and when the first connection portion 30 is formed, a cofferdam 31 is formed through a patterned electrically connecting structure material layer, the cofferdam 31 is located at the periphery of the first connection portion 30, the second cavity 33 surrounds the first connection portion 30, and the surface of the cofferdam 31 away from the detection structure layer is flush with the surface of the first connection portion 30 away from the detection structure layer. By forming the first connection portion 30 and the dam 31 in the same process, the process is simplified and the packaging efficiency is improved. In one embodiment, the third substrate 32 has a third cavity, and the first connection portion 30 is formed at the periphery of the third cavity, so that the structural strength of the device is improved, the heat insulation effect of the third cavity is improved, and the performance of the device is improved.

Referring to fig. 16, the third substrate 32 is patterned to form second through holes 321, the second through holes 321 penetrate through the third substrate 32, in this embodiment, there are two second through holes 321, and projections of the two second through holes 321 in a direction perpendicular to the dielectric layer 11 overlap projections of the two first through holes in a direction perpendicular to the dielectric layer 11, respectively, referring to fig. 17, a layer of an electrical connection structure material is formed on the third substrate 32, the second through holes 321 are filled and the third substrate 32 is covered, the second connection portions 34 are patterned, and the second connection portions 34 are filled in the second through holes 321 and the peripheries of the second through holes 321 are covered. In this embodiment, the third substrate 32 is bonded first and then patterned to form the second through hole 321, and in other embodiments, the second through hole 321 may be patterned first and then bonded to the third substrate 32.

Referring to fig. 18, in this embodiment, after forming the second connection portion 34, forming an insulating layer 35 on the third substrate 32 and the second connection portion 34 to cover the third substrate 32 and the second connection portion 34, wherein the material of the insulating layer 35 refers to the material of the dielectric layer 11, and the insulating layer 35 plays a role in protecting the electrical connection structure and isolating the dielectric, so as to improve the reliability of the wafer level package of the sensor. Referring to fig. 19, the insulating layer 35 is patterned to form third through holes 351, the third through holes 351 penetrate through the insulating layer 35, in this embodiment, there are two third through holes 351, which respectively expose partial surfaces of the two second connection portions 34, an electrical connection structure material layer is formed on the insulating layer 35, the third through holes 351 are filled, and the insulating layer 35 is covered, referring to fig. 20, the third connection portions 36 are formed by patterning, in this embodiment, there are two third connection portions 36 which are isolated from each other, and the third connection portions 36 are filled in the third through holes 351 and protrude out of the surface of the insulating layer 35.

In this embodiment, the electrical connection structure is used to lead out the electrical property of the thermocouple and connect to an external circuit. The electrical connection structure is divided into the first connection portion 30, the second connection portion 34 and the third connection portion 36, which are formed in different processes, so as to form the electrical connection structure, thereby reducing the process difficulty and improving the yield and reliability of the wafer level package of the sensor. According to the invention, the third substrate 32 is bonded on the prepared detection structure layer to form the second cavity 33 in an enclosing mode, and the electric connection structure is arranged, so that the electric property of the thermocouple is led out to complete the packaging of the detection structure layer, the packaging size is greatly reduced, and the application requirement of the sensor in miniaturized equipment is met. The wafer level manufacturing process has the advantages of short period, high efficiency and low cost.

Example 2

Referring to fig. 20, a wafer level package structure of a sensor according to an embodiment 2 of the present invention includes:

a second substrate 26, the second substrate 26 having a first cavity 27;

a detection structure layer comprising a detection structure at least partially located above the first cavity 27;

a dielectric layer 11 covering the surface of the detection structure layer far away from the second substrate 26;

the metal cofferdam 31 is positioned above the dielectric layer 11;

a third substrate 32, wherein the third substrate 32 is located above the metal cofferdam 31, the metal cofferdam 31 and the third substrate 32 enclose a second cavity 33, and the second cavity 33 encloses at least part of the detection structure;

In this embodiment, the metal dam 31 and at least a portion of the electrical connection structure have the same layer structure, that is, the metal dam 31 is formed together when the electrical connection structure is formed, for example, when the electrical connection structure is formed by deposition and electroplating, the metal dam 31 and a portion of the electrical connection structure, for example, the first connection portion 30 is higher than the dielectric layer 11, and the material, thickness, layer number, compactness, and the like are the same.

In this embodiment, the sensing structure includes at least a portion of a thermocouple, the thermocouple including a first thermoelectric strip and a second thermoelectric strip connected to each other, the first thermoelectric strip and the second thermoelectric strip being stacked or juxtaposed. In other embodiments, the detection structure as a sensing structure of the sensor may be a MEMS cantilever structure, a thermopile structure, a filter structure, etc., and the detection structure may further include at least a portion of a thermistor or at least a portion of a photoresistor.

In this embodiment, the second substrate further includes a top silicon layer, the top silicon layer is located on a side of the dielectric layer 11 away from the third substrate 32, the top silicon layer is made of monocrystalline silicon, and the first thermoelectric strip 211 and/or the second thermoelectric strip 23 are formed of the top silicon layer.

In this embodiment, a planarization layer 25 is included between the detection structure layer and the second substrate 26.

In this embodiment, the detection structure is a plurality of, and a plurality of detection structures are array arrangement.

In this embodiment, a third cavity is formed on the side of the third substrate 32 facing the thermoelectric inductor.

In this embodiment, the third substrate 32 includes a circuit therein.

With respect to the materials, structures and positional relationships of the second substrate 26, the planarization layer 25, the thermocouple, the dielectric layer 11, the metal dam 31, the third substrate 32 and the electrical connection structure, reference is made to the previous method embodiment section, and with respect to the structures of the first cavity 27, the second cavity 33 and the third cavity, reference is also made to the previous method embodiment section, and no further description is given here.

In the embodiment of the invention, the second cavity 33 is formed by bonding the third substrate 32 on the prepared detection structure layer, and the electric connection structure is arranged to lead out the electric property of the thermocouple to complete the packaging of the detection structure layer, so that the packaging size is greatly reduced, and the application requirement of the sensor in miniaturized equipment is met. The second cavity 33 is not etched on the third substrate 32, but is bonded to form a cavity, so that the problems that the back cavity etching process is not well controlled and the size precision of the cavity is poor are solved, and the measurement precision of the sensor is improved. The wafer level manufacturing process has the advantages of short period, high efficiency and low cost.

Further, the first substrate comprises top silicon, and the top silicon is made of monocrystalline silicon, so that the first thermoelectric strip 211 and/or the second thermoelectric strip 23 of the thermocouple can be formed by directly using the top silicon of the SOI substrate, the manufacturing process is simplified, and the packaging efficiency is improved.

Furthermore, the electrical connection structure is divided into the first connection portion 30, the second connection portion 34 and the third connection portion 36, which are formed in different processes, so that the process difficulty is reduced, and the yield and reliability of the wafer level package of the sensor are improved.

Further, a dam 31 made of a metal material is formed, and a third substrate 32 is bonded on the dam 31 to form a second cavity 33, so that the air tightness and the structural strength of the wafer-level package of the sensor are improved, the temperature concentration and interference shielding of the sensor are facilitated, and the quality, the reliability and the yield of the wafer-level package of the sensor are improved.

Furthermore, the flat layer 25 is arranged, the flat layer 25 is flattened, the second substrate 26 and the detection structure layer are bonded by a fusion bonding method, the alignment precision of bonding and the structural strength of wafer-level packaging of the sensor are improved, the manufacturing process is simplified, and fusion bonded bonding materials are easy to obtain, so that the packaging efficiency is improved, and the packaging cost is reduced.

It should be noted that, in the present specification, all the embodiments are described in a related manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the structural embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims

1. A wafer level packaging method of a sensor is characterized by comprising the following steps:

providing a second substrate having a first cavity;

removing the substrate;

providing a third substrate;

2. The wafer level packaging method of the sensor according to claim 1, wherein the detection structure comprises at least a portion of a thermocouple, the thermocouple comprising a first thermoelectric strip and a second thermoelectric strip connected to each other, the first thermoelectric strip and the second thermoelectric strip being stacked or juxtaposed.

3. The wafer-level packaging method of the sensor according to claim 2, wherein the first substrate further comprises a top silicon layer, the top silicon layer is located on the dielectric layer, and the top silicon layer is made of monocrystalline silicon.

4. The wafer-level packaging method for the sensor according to claim 3, wherein the first thermoelectric strip and/or the second thermoelectric strip are formed by patterning top silicon.

5. The wafer level packaging method of the sensor according to claim 2, wherein the material combination of the thermocouple comprises: p-type and n-type single crystal silicon, single crystal silicon and polycrystalline silicon, single crystal silicon and metal, polycrystalline silicon and metal, p-type polycrystalline silicon and n-type polycrystalline silicon, the metal including aluminum, copper, gold, titanium, or tungsten.

6. The wafer level packaging method for the sensor according to claim 1, wherein the method for removing the substrate comprises one or a combination of grinding and etching.

7. The wafer level packaging method of the sensor according to claim 1, further comprising the steps of: forming an electric connection structure, wherein the electric connection structure leads out the electrical property of the detection structure layer, and the forming method of the electric connection structure comprises the following steps: after the substrate is removed, patterning the dielectric layer to form a first through hole, forming a first connecting part, and penetrating through the first through hole to be electrically connected with the detection structure;

bonding the third substrate;

patterning the third substrate, forming a second through hole, forming a second connecting part, and penetrating through the second through hole to be electrically connected with the first connecting part;

after the second connection portion is formed, a third connection portion is formed to electrically connect the second connection portion, and the electrical connection structure includes the first connection portion, the second connection portion, and the third connection portion.

8. The wafer-level packaging method for sensor according to claim 7, wherein the dam is formed at the same time as the first connection portion is formed, the first connection portion and the dam are made of the same material, and the dam material comprises metal or polysilicon.

9. The wafer-level packaging method for sensor according to claim 1, wherein the dam is the same material as the third substrate.

10. The wafer-level packaging method for the sensor according to claim 7, wherein the dam and the electrical connection structure are isolated from each other, the height of the dam comprises 1-20 μm, and the surface of the dam away from the detection structure layer is flush with the surface of the first connection portion away from the detection structure layer.

11. The wafer-level packaging method for the sensor according to claim 1, wherein the third substrate has a third cavity, and the dam is located at the periphery of the third cavity.

12. The wafer-level packaging method for the sensor as claimed in claim 11, wherein the distance from the detection structure layer to the bottom of the third cavity is 10 microns to 200 microns.

13. The wafer level packaging method of the sensor as claimed in claim 2, wherein after forming the thermocouple and before bonding the second substrate and the detection structure layer, the method further comprises: forming a passivation layer on the thermocouple, covering the thermocouple and the first substrate.

14. The wafer-level packaging method of the sensor according to claim 1, wherein a flat layer is disposed on the detection structure layer, and the second substrate is fusion bonded to the flat layer.

15. The wafer level packaging method for the sensor according to claim 2, wherein the thermocouple is a plurality of thermocouples arranged in an array.

16. The wafer-level packaging method of the sensor according to claim 2, wherein the material of the second substrate comprises: optical material, polymeric material or semiconducting material, said semiconducting material being transparent to infrared light.

17. A wafer level package structure of a sensor, comprising:

a second substrate having a first cavity;

a detection structure layer comprising a detection structure at least partially located over the first cavity;

the metal cofferdam is positioned above the dielectric layer;

18. The wafer level package structure of sensor of claim 17, wherein the sensing structure comprises at least a portion of a thermocouple, the thermocouple comprising a first thermoelectric strip and a second thermoelectric strip connected to each other, the first thermoelectric strip and the second thermoelectric strip being stacked or juxtaposed.

19. The wafer-level package structure of sensor of claim 17, wherein the metal dam has the same layer structure as at least a portion of the electrical connection structure.

20. The wafer-level package structure of the sensor of claim 17, wherein a planarization layer is included between the detection structure layer and the second substrate.

21. The wafer level package structure of sensor of claim 17, wherein the detecting structure is a plurality of detecting structures, and the plurality of detecting structures are arranged in an array.

22. The wafer-level package structure of the sensor according to claim 17, wherein a side of the third substrate facing the detection structure is provided with a third cavity.

23. The wafer-level package structure of the sensor of claim 17, wherein the third substrate comprises circuitry therein.