CN114386367B - Simulation method, system and medium of nonlinear delay circuit system - Google Patents
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Abstract
The invention discloses a simulation method, a system and a medium of a nonlinear delay circuit system, wherein the method comprises the following steps: simulating the nonlinear delay circuit system to obtain an output matrix of the nonlinear delay circuit system; calculating the output matrix by using a principal component analysis method to obtain singular value vectors and singular values of the output matrix; constructing a basis function based on the singular value vector and the singular value, and obtaining a state variable function based on the basis of the basis function; constructing a time sequence convolution network model, and obtaining training data of the time sequence convolution network model based on an output matrix and a state variable function; training the time sequence convolution network model based on training data of the time sequence convolution network model; the signal is input to the trained time series convolution network model to output the value of the state variable of the nonlinear delay circuit system. The scheme of the invention avoids repeatedly solving the mathematical model of the nonlinear delay circuit system, reduces the calculation time and improves the calculation speed.
Description
Technical Field
The present invention relates to the field of circuit simulation technologies, and in particular, to a method, a system, and a medium for simulating a nonlinear delay circuit system.
Background
With the continuous increase of the scale and the working frequency of the integrated circuit, the working state of each functional circuit inside the integrated circuit is more and more complex, and in the design stage of the integrated circuit, each module inside the integrated circuit needs to be accurately modeled and subjected to simulation analysis, so that the tape-out failure can be reduced to the maximum extent. The signal integrity analysis in the integrated circuit and the simulation of the output signals of all modules need to be subjected to a large amount of numerical calculation. Especially as the operating frequency of the integrated circuit increases, the propagation delay of the signal needs to be taken into account, which brings great challenges to the design of the integrated circuit.
Nonlinear delay circuitry is one of the most complex blocks of circuitry within an integrated circuit. When the nonlinear delay circuit system is analyzed and simulated, a complex mathematical model needs to be solved, and under the condition of a circuit with a larger scale, the solution is difficult. Most of the current mathematical model processing methods for the nonlinear delay circuit system are numerical methods, the numerical methods are time-consuming in the processing process, the calculation time is often unacceptable, and even the calculation is impossible.
Due to the large number of on-chip interconnects and the increasing operating frequency of chips, the chips need to be subjected to repeated simulation verification before being manufactured into a tape-out chip. Therefore, each circuit module in the chip needs to be accurately modeled, and under the condition of high-speed signals, the transmission delay of the signals needs to be taken into consideration, so that the obtained mathematical model is complex and large in scale, the calculation amount is huge when the simulation analysis is directly carried out on the chip, the chip can meet the design requirement after multiple parameter debugging and simulation analysis in the design stage, and the timeliness of directly using the mathematical model of the original interconnection delay system to carry out analysis and simulation is poor.
Disclosure of Invention
In view of this, the invention provides a simulation method, system and medium for a nonlinear delay circuit system, which avoids repeatedly solving a mathematical model of a large-scale nonlinear delay circuit system, and requires a small amount of computation for each simulation calculation, thereby greatly reducing the simulation analysis time cost of an integrated circuit and improving the research and development efficiency of a chip.
Based on the above object, an aspect of the embodiments of the present invention provides a simulation method for a nonlinear delay circuit system, which specifically includes the following steps:
simulating a nonlinear delay circuit system to obtain an output matrix of the nonlinear delay circuit system;
calculating the output matrix by using a principal component analysis method to obtain singular value vectors and singular values of the output matrix;
constructing a basis function based on the singular value vector and the singular value, and obtaining a state variable function based on the basis of the basis function;
constructing a time sequence convolution network model, and obtaining training data of the time sequence convolution network model based on the output matrix and the state variable function;
training the time sequence convolution network model based on the training data of the time sequence convolution network model;
the signal is input to the trained time series convolution network model to output the value of the state variable of the nonlinear delay circuit system.
In some embodiments, calculating the output matrix using principal component analysis to obtain singular value vectors and singular values of the output matrix includes:
interpolating the output matrix by using a discrete empirical interpolation algorithm to obtain an interpolation matrix;
and carrying out singular value decomposition on the interpolation matrix to obtain a left singular value vector, a singular value and a right singular value vector of the interpolation matrix.
In some embodiments, constructing basis functions based on the singular value vectors and the singular values comprises:
constructing basis functions based on the right singular value vectors and the singular values.
In some embodiments, the expression of the basis function is:
wherein E issquareFor an interpolation matrix, λiIs EsquareSingular value of, ViIs equal to said lambdaiCorresponding toEsquareN is EsquareThe number of singular values of;
the expression of the state variable function is:
wherein, trIs the r < th > time, where r ∈ {1,2, …, m }, x (t)r) Is trThe output value of the state variable of the time instant non-linear delay circuit system,
is EsquareThe mean value vector of (a) is,
q is E selected from nsquareThe number of singular values of (c).
In some embodiments, constructing a time-series convolutional network model comprises:
establishing coefficients at time r
Coefficient of preceding r-k time
The mathematical model in (b) is:
the mathematical model is simulated based on a time-series convolutional network model.
In some embodiments, the output matrix includes output values of all state variables of the nonlinear delay circuitry output after the simulation of the nonlinear delay circuitry.
In some embodiments, deriving training data for the time-series convolutional network model based on the output matrix and the state variable function comprises:
deriving an expression of the coefficient based on the state variable function;
substituting the output values of all state variables in the output matrix into the expression of the coefficient to obtain the values of all the coefficients;
a training data set and a validation data set of the time series convolutional network model are derived based on values of all coefficients.
In some embodiments, simulating a non-linear delay circuitry to obtain an output matrix of the non-linear delay circuitry comprises:
and taking square wave signals as the input of the nonlinear delay circuit system, and simulating the nonlinear delay circuit system to obtain an output matrix of the nonlinear delay circuit system.
In another aspect of the embodiments of the present invention, a simulation system of a nonlinear delay circuit system is further provided, including:
the simulation module is configured to simulate the nonlinear delay circuit system to obtain an output matrix of the nonlinear delay circuit system;
the calculation module is configured to calculate the output matrix by using a principal component analysis method to obtain singular value vectors and singular values of the output matrix;
the calculation module is further configured to construct a basis function based on the singular value vector and the singular value, and obtain a state variable function based on the basis of the basis function;
the building module is configured to build a time sequence convolution network model and obtain training data of the time sequence convolution network model based on the output matrix and the state variable function;
a training module configured to train the time series convolutional network model based on training data of the time series convolutional network model;
an output module configured to input a signal to the trained time series convolutional network model to output a value of a state variable of the nonlinear delay circuitry.
In a further aspect of the embodiments of the present invention, a computer-readable storage medium is also provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.
The invention has at least the following beneficial technical effects: the invention obtains the output matrix of the nonlinear delay circuit system by simulating the nonlinear delay circuit system; calculating the output matrix by using a principal component analysis method to obtain a singular value vector and a singular value of the output matrix; constructing a basis function based on the singular value vector and the singular value, and obtaining a state variable function based on the basis of the basis function; constructing a time sequence convolution network model, and obtaining training data of the time sequence convolution network model based on an output matrix and a state variable function; training the time sequence convolution network model based on training data of the time sequence convolution network model; signals are input into the trained time sequence convolution network model to output the value of the state variable of the nonlinear delay circuit system, so that the problem that the mathematical model of the large-scale nonlinear delay circuit system is solved repeatedly is avoided, the calculation amount required by each simulation calculation is small, the simulation analysis time cost of the integrated circuit is greatly reduced, and the research and development efficiency of the chip is improved.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a block diagram of an embodiment of a simulation method for a non-linear delay circuit system according to the present invention;
FIG. 2 is a diagram illustrating a time series convolution model according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an embodiment of a hole convolution according to the present invention;
FIG. 4 is a diagram illustrating a timing convolution module according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of the state variable output at any time based on the trained time series convolutional network model provided in the present invention;
FIG. 6 is a schematic diagram of a non-linear delay circuitry;
FIG. 7 is a comparison graph of simulation results from a simulation of the non-linear delay circuit system of FIG. 6;
FIG. 8 is a diagram illustrating an embodiment of a simulation system for a nonlinear delay circuit system according to the present invention;
fig. 9 is a schematic structural diagram of an embodiment of a computer-readable storage medium provided in the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In view of the above objects, a first aspect of an embodiment of the present invention provides an embodiment of a simulation method for a nonlinear delay circuit system. As shown in fig. 1, it includes the following steps:
step S10, simulating a nonlinear delay circuit system to obtain an output matrix of the nonlinear delay circuit system;
step S20, calculating the output matrix by using a principal component analysis method to obtain singular value vectors and singular values of the output matrix;
step S30, constructing a basis function based on the singular value vector and the singular value, and obtaining a state variable function based on the basis of the basis function;
step S40, constructing a time sequence convolution network model, and obtaining training data of the time sequence convolution network model based on the output matrix and the state variable function;
step S50, training the time sequence convolution network model based on the training data of the time sequence convolution network model;
and step S60, inputting signals to the trained time sequence convolution network model to output the values of the state variables of the nonlinear delay circuit system.
The mathematical model of a nonlinear interconnect delay circuitry is generally:
wherein the matrix E ∈ Rn×nThe value of (A) is composed of inductance value and capacitance value, Rn×nA real number matrix of n rows by n columns is represented, n is a natural number not containing 0, the function f (x) is a mathematical model of a nonlinear element in the integrated circuit, B belongs to Rn×1Is an input matrix, u (t) is an input, C ∈ R1×nIs an output matrix; unknown variables x (t) ε Rn×1Is the node voltage or branch current in the circuit, n is the order of the circuit system, and tau is the signal transmission delay. In the case of a large scale nonlinear interconnect delay circuitry, the simulation calculation for this equation would be exceptionally complex and time consuming. In the simulation and analysis process of the signal integrity and other performances of the integrated circuit, the mathematical model needs to be solved for many times, so that huge calculation amount is caused.
To solve the above problem, the present embodiment provides a simulation method for a nonlinear delay circuit system, which includes the following specific processes:
in step S10, before the nonlinear delay circuit system is simulated, the time interval of the simulation and the time interval in the time interval are set in advance to obtain the output value of the state variable at a specific time.
For example, a square wave signal y = a square (t, w) with time length t, amplitude ± a and duty ratio w is used as the input of the nonlinear delay circuit system, and the time interval of the simulation is set to [0, 2000 [ ]]The interval point T is 0.01, and the nonlinear delay circuit system is simulated to obtain the corresponding output matrix of the nonlinear delay circuit systemF squareOutput matrixF squareOutput matrix containing values of state variables at all times within a time intervalF square。
Wherein, x (t)j) Is tjAll the state variables x, j and m of the time nonlinear delay circuit system are natural numbers without 0, tjRepresenting the j-th time, with a time of j × T, TmThe representative time is m × T, which represents the mth time. It should be noted that the square wave signal is only an example of the embodiment of the present invention, and the input signal of the nonlinear delay circuit system may include a sine wave, a triangular wave, and other input signals besides the square wave. And outputting the state variables at all the moments in the selected time interval through the steps.
In step S20, F is extracted by principal component analysissquareIs given as the main information.
Principal component analysis method: the multi-index is converted into a small number of comprehensive indexes (namely, principal components), wherein each principal component can reflect most information of the original variable and the contained information is not repeated.
Using principal component analysis to convert matrix FsquareIs related to a set of variables x (t)j) The linear transformation is converted into another group of irrelevant variables, and the new variables are arranged according to the descending order of the variance. The total variance of the variables is kept constant in the mathematical transformation, such that the first variable has the largest variance, called the first principal component, and the second variable has the second largest variance and is uncorrelated with the first variable, called the second principal component. And analogizing in turn, how many new variables have how many principal components after transformation. Sorting the main components from large to small according to the contribution amount of the main components to the variation, namely variation percentage; when the cumulative variation percentage of the first several principal components reaches a certain value (ratio)E.g., 75%, 80%, 85%), the latter principal components are removed to compress the data, increasing the computational speed of the simulation.
The principal component analysis method includes: eigenvalue Decomposition, SVD (Singular Value Decomposition, hereinafter referred to as SVD), NMF (Non-negative Matrix Decomposition), and the like.
This embodiment applies principal component analysis to the output matrix FsquareCalculating to obtain an output matrix FsquareThe singular value vector and the singular value.
Through the steps, the calculation speed of the nonlinear delay circuit system simulation is improved.
In step S30, a basis function is constructed based on the singular value vector and the singular value, and a state variable function is obtained based on the basis function. The step reflects the value of the state variable output by the nonlinear delay circuit system at any moment through the state variable function, so that the value of the state variable output at any moment can be directly obtained through the state variable function after the input signal is input into the nonlinear delay circuit system subsequently, and the calculation speed of the simulation of the nonlinear delay circuit system is accelerated.
In step S40 and step S50, a time series convolutional network model is constructed, and training data of the time series convolutional network model is obtained based on the output matrix and the state variable function; training the time sequence convolution network model based on the training data of the time sequence convolution network model. The time sequence convolution network model is used for representing the relation between input data at the current moment and input data at the previous k moment, and based on the state variable function, the trained time sequence convolution network model can well predict the value of the state variable output by the nonlinear delay circuit system at any moment, so that the simulation accuracy of the nonlinear delay circuit system is ensured.
In step S60, the signal is input to the trained time series convolution network model, so that the value of the state variable of the nonlinear delay circuit system at any time can be obtained, and the mathematical model of the nonlinear delay circuit system is not required to be solved repeatedly, thereby increasing the computation speed of the simulation of the nonlinear delay circuit system and ensuring the accuracy of the simulation of the nonlinear delay circuit system.
Through the embodiment, only one-time simulation solving is needed for the nonlinear delay circuit system, the problem that the mathematical model of the large-scale nonlinear delay circuit system is solved repeatedly is avoided, the calculation amount required by each simulation calculation is small, the simulation analysis time cost of the integrated circuit is greatly reduced, and the research and development efficiency of the chip is improved.
In some embodiments, calculating the output matrix using principal component analysis to obtain singular value vectors and singular values of the output matrix comprises:
interpolating the output matrix by using a discrete empirical interpolation algorithm to obtain an interpolation matrix;
and carrying out singular value decomposition on the interpolation matrix to obtain a left singular value vector, a singular value and a right singular value vector of the interpolation matrix.
In some embodiments, constructing basis functions based on the singular value vectors and the singular values comprises:
constructing basis functions based on the right singular value vectors and the singular values.
In some embodiments, the expression of the basis function is:
wherein E issquareFor an interpolation matrix, λiIs EsquareSingular value of, ViIs equal to said lambdaiCorresponding EsquareA vector of singular values of n is EsquareThe number of singular values of;
the expression of the state variable function is:
wherein, trIs the r < th > time, where r ∈ {1,2, …, m }, x (t)r) Is trTime of day isThe output value of the state variable of the linear delay circuitry,
is EsquareThe mean value vector of (a) is,
q is E selected from nsquareThe number of singular values of (c).
In some embodiments, constructing a time-series convolutional network model comprises:
establishing coefficients at time r
Coefficient of preceding r-k time
The mathematical model in (b) is:
the mathematical model is simulated based on a time-series convolutional network model.
In some embodiments, the output matrix includes output values of all state variables of the nonlinear delay circuitry output after the simulation of the nonlinear delay circuitry.
In some embodiments, deriving training data for the time-series convolutional network model based on the output matrix and the state variable function comprises:
deriving an expression of the coefficient based on the state variable function;
substituting the output values of all state variables in the output matrix into the expression of the coefficient to obtain the values of all the coefficients;
a training data set and a validation data set of the time series convolutional network model are derived based on values of all coefficients.
In some embodiments, simulating the non-linear delay circuitry to obtain an output matrix of the non-linear delay circuitry comprises:
and taking square wave signals as the input of the nonlinear delay circuit system, and simulating the nonlinear delay circuit system to obtain an output matrix of the nonlinear delay circuit system.
The following describes a specific embodiment of the present invention with reference to another specific example.
In this embodiment, the principal component analysis method is performed by applying an output matrix FsquareSingular value decomposition is carried out to obtain an output matrix FsquareSingular values and singular value vectors.
Further, since the output matrix FsquareThe amount of data contained in (1) is very large, and in order to increase the speed of performing singular value decomposition on the output matrix, the discrete empirical interpolation algorithm is first used to perform the singular value decomposition on the output matrix FsquareInterpolation is carried out to obtain an interpolation matrix E based on an output matrixsquare，Esquare= DEIM(Fsquare) Matrix Esquare∈Rn×m。
The specific interpolation process is as follows:
inputting a matrix:
outputting a matrix: esquare
The method comprises the following steps: find the first column vector x (t)1) And its maximum value position [ gamma, z ]1]=max{|x(t1) I where y is the vector x (t)1) Maximum value of, z1Is the maximum value in the vector x (t)1) At the same position in (a).
Step two: take matrix U = [ x (t)1)]Interpolation selection matrix
，
Is at z1Unit vectors with position 1 and other positions 0.
Step three: the following cycle is performed:
a) from p =2 to p = m, m corresponding to the m time instant in the input matrix;
b) solving a matrix equation to obtain a vector c:
NUc=Nx(tp)
c) solving a vector r:
r=x(tp)-Nc
d) find the maximum and its position in the vector r:
[γp,zp] =max{|r|}
d) 
and (5) finishing the circulation to obtain an interpolation selection matrix N.
Solving the interpolation matrix Esquare = NFsquare。
After obtaining the interpolation matrix of the output matrix, the interpolation matrix E is comparedsquareSingular value decomposition is carried out to obtain Esquare=UΣVTWherein U ∈ Rn×nIs a matrix EsquareLeft singular value vector of ∈ Rn×mIs a matrix EsquareSingular value of, VT∈Rm×mIs a matrix EsquareRight singular value vector of (a).
Next, a basis function is constructed using the singular value vector and the singular value:
wherein λ isiAs an interpolation matrix EsquareSingular value of (A)iE is Σ, n is the interpolation matrix EsquareNumber of singular values of, ViAs an interpolation matrix EsquareSingular value vector of, and λiAnd correspond to each other.
The state variable function x (t) at any moment can be obtained by combining the formula (1)r)：
Wherein, trIs the time of the r < th >, where r ∈ {1,2, …, m }, x (t })r) Is trThe output value of the state variable of the time instant non-linear delay circuit system,
is EsquareThe mean value vector of (a) is,
q is E selected from nsquareThe number of singular values of (c).
Analyzing the principle of the nonlinear delay circuit system, it can be known that the output of the nonlinear delay circuit system at the current moment is related to the input of the previous k moments, and based on the output, the function x (t) of the state variable can be obtainedr) Unknown variable (coefficient) of
) Establishing a mathematical model, wherein the mathematical model is as follows:
where k is a natural number excluding 0.
And constructing a time sequence convolution network model. As shown in fig. 2, M in fig. 2 represents the number of time-series convolution modules in order to construct the time-series convolution network model.
The time sequence convolution network model comprises an input layer, at least one time sequence convolution module, a full connection layer and an output layer, wherein the input layer is used for inputting training data
The output layer is used for outputting the training result
。
With reference to fig. 3 and 4, a time-series convolution module is constructed based on the hole convolution and residual connection, where in fig. 3, k represents the convolution kernel size, and d represents the hole parameter (hole interval size), which is used to expand the perception field of the causal network. In fig. 4, Dropout is interpreted as drop and Relu is interpreted as an activation function.
The traditional convolution network model can not directly process sequence modeling (sequence modeling), when processing sequence problems, causal convolution is needed, and the function is to abstract the sequence problems according to the principle that
De-prediction
. The output of each layer of the hole convolution is obtained by the input of the corresponding position of the previous layer and the input of the previous position, if the output layer and the input layer are preceded by a plurality of hidden layers, the more all the inputs of one output correspond to, and the farther the input and the output are apart, the earlier input variable needs to be considered to participate in the operation, so that the timing problem can be processed. However, as the number of layers of convolution increases: the method solves the problems of gradient disappearance, complex training and poor fitting effect, and in order to solve the problem, expanded convolution (scaled) is used for reducing the number of convolution layers and increasing the perception field of the convolution. The extended convolution (filtered convolution) is to make the filter be applicable to the area larger than the length of the filter itself by skipping part of the input, as shown in fig. 3, it can be seen that the perception field of the next layer of neurons in the causal neural network on the historical data of the last neuron is greatly extended, which also improves the modeling capability of the causal convolutional network on the time series speculation task requiring long memory.
The time sequence convolution module is formed by connecting a cavity cause-effect convolution layer, a weight normalization layer, an activation function layer and a Dropout layer, and uses a residual error structure.
The time sequence task can be well modeled based on the constructed time sequence convolution network model. Will be k times before
Obtaining current time r as training data
And then based on the state variable function, obtaining the output value of the state variable at the current moment, wherein the current moment can be freely selected. This makes it possible to obtain an output value of the state variable at any time.
The following is a description of a specific process for constructing training data.
The coefficient is obtained from equation (2)
The value of (c):
wherein the content of the first and second substances,
，x(tj) Output matrix F for simulation output of nonlinear delay circuitrysquareThe value of the state variable in (1).
Obtain all coefficients
After all values of (2), the coefficients are adjusted
All values of (a) are split into a training set and a validation set. For example, by combining coefficients
80% of all values of (a) are split into training sets, leaving 20% as validation sets.
And training the constructed time sequence convolution network based on the training set and the verification set. The optimizer used in the training process is an Adam optimizer, the training epoch number is 50, the loss function is a mean square error function, and a well-trained time sequence convolution network model is obtained.
Good pair coefficient of the trained model
Predicting to obtain the state variable x (t) at any timej) The specific flow is as follows:
and inputting the coefficient of the input at the previous k time related to the output at the current time r +1 into the trained time sequence convolution network model to obtain the coefficient at the r +1 th time, substituting the coefficient at the r +1 th time into a state variable function to obtain the value of the state variable at the r +1 th time, and obtaining the output value of the state variable at any time based on the value. If r +1 is less than or equal to k, the signal just starts to be input into the nonlinear delay circuit system, and after r +1> k, the input coefficient at the previous k moment is input into the trained time sequence convolution network model to start to predict the system.
In fig. 5, when k =5, the coefficient is predicted, and the state variable x (t) at the current time is obtainedj) The flow chart of the value (b) illustrates that the coefficient of the current time r +1 is related to the previous 5 coefficients, and the previous 5 coefficients are input into the trained time sequence convolution network model to obtain the coefficient of the current time r + 1.
Through the embodiment, the calculation amount can be greatly reduced in the simulation process of the nonlinear delay circuit system, repeated solving of a large-scale nonlinear delay circuit system is avoided, the calculation time is reduced under the condition of ensuring the accuracy, and the calculation speed is improved.
The non-linear delay circuit system in fig. 6 is composed of three coupled interconnection lines, and the transmitting end and the receiving end of the non-linear delay circuit system are non-linear circuit devices, so that the whole non-linear delay circuit system is formed. The mathematical model of the nonlinear delay circuit is
The matrix size is E ∈ R1806×1806The function f (x) is a mathematical model of the nonlinear component in FIG. 6, B ∈ R1806 ×1Is an input matrix, u (t) is an input, C ∈ R1×1806Is an output matrix. The input function is sin (2 × pi × t) and the time to solve the mathematical model directly is 1518.31 seconds. The mathematical model constructed using the proposed method of the present invention uses the same input sin (2 x pi t) and the solution time is 53.22 seconds. The solving time is greatly shortened, but the output results of the mathematical model of the nonlinear delay circuit are relatively close, and the output results are shown in fig. 7.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 8, an embodiment of the present invention further provides a simulation system of a nonlinear delay circuit system, including:
a simulation module 110, where the simulation module 110 is configured to simulate a nonlinear delay circuit system to obtain an output matrix of the nonlinear delay circuit system;
a calculation module 120, where the calculation module 120 is configured to calculate the output matrix by using a principal component analysis method to obtain singular value vectors and singular values of the output matrix;
the calculation module 120 is further configured to construct a basis function based on the singular value vector and the singular value, and obtain a state variable function based on the basis of the basis function;
a building module 130, where the building module 130 is configured to build a time sequence convolutional network model, and obtain training data of the time sequence convolutional network model based on the output matrix and the state variable function;
a training module 140, the training module 140 configured to train the time-series convolutional network model based on training data of the time-series convolutional network model;
an output module 150, the output module 150 configured to input a signal to the trained sequential convolutional network model to output a value of a state variable of the nonlinear delay circuitry.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 9, an embodiment of the present invention further provides a computer-readable storage medium 40, where the computer-readable storage medium 40 stores a computer program 410, which when executed by a processor, performs the above method.
The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
The embodiment of the invention also can comprise corresponding computer equipment. The computer device comprises a memory, at least one processor and a computer program stored on the memory and executable on the processor, the processor performing any of the above methods when executing the program.
The memory, as a non-volatile computer-readable storage medium, may be used to store a non-volatile software program, a non-volatile computer-executable program, and modules, such as program instructions/modules corresponding to the simulation method of the nonlinear delay circuit system in the embodiments of the present application. The processor executes various functional applications and data processing of the device by running the non-volatile software programs, instructions and modules stored in the memory, i.e., the simulation method of the nonlinear delay circuit system implementing the above method embodiments.
The memory may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the device, and the like. Further, the memory may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, the memory optionally includes memory located remotely from the processor, and such remote memory may be coupled to the local module via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. The numbers of the embodiments disclosed in the above embodiments of the present invention are merely for description, and do not represent the advantages or disadvantages of the embodiments. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A method for simulating a nonlinear delay circuit system, comprising:
simulating a nonlinear delay circuit system to obtain an output matrix of the nonlinear delay circuit system;
calculating the output matrix by using a principal component analysis method to obtain singular value vectors and singular values of the output matrix;
constructing a basis function based on the singular value vector and the singular value, and obtaining a state variable function based on the basis of the basis function;
constructing a time sequence convolution network model, and obtaining training data of the time sequence convolution network model based on the output matrix and the state variable function;
training the time sequence convolution network model based on the training data of the time sequence convolution network model;
the signal is input to the trained time series convolution network model to output the value of the state variable of the nonlinear delay circuit system.
2. The method of claim 1, wherein computing the output matrix using principal component analysis to obtain singular value vectors and singular values of the output matrix comprises:
interpolating the output matrix by using a discrete empirical interpolation algorithm to obtain an interpolation matrix;
and carrying out singular value decomposition on the interpolation matrix to obtain a left singular value vector, a singular value and a right singular value vector of the interpolation matrix.
3. The method of claim 2, wherein constructing basis functions based on the singular value vectors and the singular values comprises:
constructing basis functions based on the right singular value vectors and the singular values.
4. The method of claim 3, wherein the basis functions are expressed as:
wherein, EsquareFor an interpolation matrix, λiIs EsquareSingular value of, ViIs equal to said lambdaiCorresponding EsquareA vector of singular values of n is EsquareThe number of singular values of;
the expression of the state variable function is:
wherein, trIs the time of the r < th >, where r ∈ {1,2, …, m }, x (t })r) Is trThe output value of the state variable of the time instant non-linear delay circuit system,
is EsquareThe mean value vector of (a) is,
q is E selected from nsquareThe number of singular values of (c).
5. The method of claim 4, wherein constructing a time-series convolutional network model comprises:
establishing coefficients at time r
Coefficient of preceding r-k time
The mathematical model in (b) is:
the mathematical model is simulated based on a time-series convolutional network model.
6. The method of claim 4, wherein the output matrix comprises output values of all state variables of the nonlinear delay circuitry output after the nonlinear delay circuitry is simulated.
7. The method of claim 4, wherein deriving training data for the time-series convolutional network model based on the output matrix and the state variable function comprises:
deriving an expression of the coefficient based on the state variable function;
substituting the output values of all state variables in the output matrix into the expression of the coefficient to obtain the values of all the coefficients;
a training data set and a validation data set of the time series convolutional network model are derived based on values of all coefficients.
8. The method of claim 1, wherein simulating nonlinear delay circuitry to obtain an output matrix of the nonlinear delay circuitry comprises:
and taking square wave signals as the input of the nonlinear delay circuit system, and simulating the nonlinear delay circuit system to obtain an output matrix of the nonlinear delay circuit system.
9. An emulation system for a nonlinear delay circuit system, comprising:
the simulation module is configured to simulate a nonlinear delay circuit system to obtain an output matrix of the nonlinear delay circuit system;
the calculation module is configured to calculate the output matrix by using a principal component analysis method to obtain singular value vectors and singular values of the output matrix;
the calculation module is further configured to construct a basis function based on the singular value vector and the singular value, and obtain a state variable function based on the basis function;
the building module is configured to build a time sequence convolution network model and obtain training data of the time sequence convolution network model based on the output matrix and the state variable function;
a training module configured to train the time series convolutional network model based on training data of the time series convolutional network model;
an output module configured to input a signal to the trained sequential convolutional network model to output a value of a state variable of the nonlinear delay circuitry.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 8.
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