CN114385517A - Method and device for processing address space mapping table - Google Patents

Method and device for processing address space mapping table Download PDF

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Publication number
CN114385517A
CN114385517A CN202111483902.1A CN202111483902A CN114385517A CN 114385517 A CN114385517 A CN 114385517A CN 202111483902 A CN202111483902 A CN 202111483902A CN 114385517 A CN114385517 A CN 114385517A
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address space
space mapping
page
mapping page
encoding
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郑宁
熊中哲
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Ruizhe Hangzhou Technology Co ltd
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Ruizhe Hangzhou Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G06F2212/1044—Space efficiency improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/21—Employing a record carrier using a specific recording technology
    • G06F2212/214—Solid state disk

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  • General Physics & Mathematics (AREA)
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  • Memory System (AREA)

Abstract

The embodiment of the application provides a processing method and a device for an address space mapping table, wherein the method comprises the following steps: acquiring an address space mapping table to be stored, wherein the address space mapping table comprises address mapping from a logic space to a physical space; dividing an address space mapping table into a plurality of address space mapping pages; the address space mapping page is stored by compressing or encoding the address space mapping page. By the method, the address space mapping table is stored after being compressed or encoded in a paging mode, so that the memory occupation of the address space mapping table can be reduced, and the performance of the solid state disk is prevented from being influenced.

Description

Method and device for processing address space mapping table
Technical Field
The present invention relates to the field of computer storage, and in particular, to a method and an apparatus for processing an address space mapping table.
Background
Due to the characteristics of the storage medium of the solid state disk, the solid state disk often needs to maintain an address mapping table from a logical space to a physical space, which is used for recording the physical address of the logical data block actually stored in the solid state disk. In consideration of the practical requirements of upper layer applications, a common solid state disk is often a page size of 4 Kilobytes (KB) as the granularity of address mapping.
With the continuous increase of the capacity of the solid state disk, the address mapping table is also larger and larger. An 8 Terabyte (TB) solid state disk, which requires 8 Gigabytes (GB) of space at a mapping granularity of 4 KB. In consideration of performance, the address mapping table is generally cached in the memory, so that the large-capacity solid state disk also puts higher requirements on the capacity of the memory. If the memory capacity is not enough to accommodate the complete address mapping table, the address mapping table exceeding the memory space limit needs to be stored in other low-speed storage media, and the performance of the solid state disk is greatly affected at this time.
At present, the method for reducing the memory space occupation of the address space mapping table is mainly completed by increasing the mapping granularity of the address mapping table. For example, the 4KB mapping granularity is changed to 8KB, or the mapping is performed in a physical database (block) size of a flash memory (NAND). Although the memory occupation can be reduced by increasing the mapping granularity, when the upper-layer application performs random reading and writing of small blocks of data, the performance of the solid state disk still receives a large influence.
Disclosure of Invention
The embodiment of the application provides a processing method and device for an address space mapping table, so as to solve the problem that in the prior art, when the memory occupation amount of the address space mapping table is reduced, the performance of a solid state disk is reduced.
In a first aspect, an embodiment of the present application provides a method for processing an address space mapping table, where the method includes:
acquiring an address space mapping table to be stored, wherein the address space mapping table comprises address mapping from a logic space to a physical space;
dividing the address space mapping table into a plurality of address space mapping pages;
and storing the address space mapping page by compressing or encoding the address space mapping page.
In an alternative embodiment, the address space mapping page includes a predetermined number of logical block addresses.
In an optional embodiment, the storing the address space mapping page by compressing or encoding the address space mapping page includes:
if the difference value between the compressed or encoded storage space of the address space mapping page and the uncompressed or unencoded storage space of the address space mapping page is smaller than a first threshold value, storing the uncompressed or unencoded address space mapping page;
and if the difference value between the compressed or encoded storage space of the address space mapping page and the uncompressed or unencoded storage space of the address space mapping page is greater than or equal to a first threshold value, storing the compressed or encoded address space mapping page.
In an optional embodiment, the storing the address space mapping page by compressing or encoding the address space mapping page includes:
determining target data in the address space mapping page, wherein the target data comprises repeated data and/or data with a coding rule;
if the proportion of the target data in the address space mapping page is larger than a second threshold value, storing the compressed or encoded address space mapping page;
and if the proportion of the target data in the address space mapping page is less than or equal to a second threshold value, storing the uncompressed or uncoded address space mapping page.
In an optional embodiment, before storing the address space mapping page by compressing or encoding the address space mapping page, the method further includes:
predicting a compression ratio of the address space mapping page under a target compression algorithm;
and if the compression rate is greater than a third threshold value, replacing the target compression algorithm.
In an alternative embodiment, the compressing or encoding includes compressing or encoding the address space mapping page by columns, or compressing or encoding the address space mapping page by rows.
In an alternative embodiment, the compressing or encoding is performed by a solid state drive, a processor, or an acceleration unit.
In a second aspect, an embodiment of the present application provides an apparatus for processing an address space mapping table, where the apparatus includes:
the device comprises an acquisition module, a storage module and a storage module, wherein the acquisition module is used for acquiring an address space mapping table to be stored, and the address space mapping table comprises address mapping from a logic space to a physical space;
the dividing module is used for dividing the address space mapping table into a plurality of address space mapping pages;
and the storage module is used for storing the address space mapping page by compressing or encoding the address space mapping page.
In an alternative embodiment, the address space mapping page includes a predetermined number of logical block addresses.
In an optional implementation manner, the storage module is specifically configured to store the uncompressed or unencoded address space mapping page if a difference between a compressed or encoded storage space of the address space mapping page and an uncompressed or unencoded storage space of the address space mapping page is smaller than a first threshold; and if the difference value between the compressed or encoded storage space of the address space mapping page and the uncompressed or unencoded storage space of the address space mapping page is greater than or equal to a first threshold value, storing the compressed or encoded address space mapping page.
In an optional embodiment, the storage module is specifically configured to determine target data in the address space mapping page, where the target data includes repeated data and/or data with a coding rule; if the proportion of the target data in the address space mapping page is larger than a second threshold value, storing the compressed or encoded address space mapping page; and if the proportion of the target data in the address space mapping page is less than or equal to a second threshold value, storing the uncompressed or uncoded address space mapping page.
In an alternative embodiment, the apparatus further comprises:
the prediction module is used for predicting the compression rate of the address space mapping page under a target compression algorithm; and if the compression rate is greater than a third threshold value, replacing the target compression algorithm.
In an alternative embodiment, the compressing or encoding includes compressing or encoding the address space mapping page by columns, or compressing or encoding the address space mapping page by rows.
In an alternative embodiment, the compressing or encoding is performed by a solid state drive, a processor, or an acceleration unit.
In a third aspect, the present application further provides an electronic device, including: a processor, and a memory;
the memory is for storing a computer program for the processor; the processor is configured to implement any one of the possible methods of the first aspect by executing the computer program.
In a fourth aspect, the present application also provides a computer program product comprising a computer program that, when executed by a processor, performs the method of any of the first aspects.
In a fifth aspect, the present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program of instructions for implementing any one of the possible methods of the first aspect when executed by a processor.
The method and the device for processing the address space mapping table provided by the embodiment of the application firstly obtain the address space mapping table to be stored, wherein the address space mapping table comprises address mapping from a logic space to a physical space. Subsequently, the address space mapping table is divided into a plurality of address space mapping pages. And finally, compressing or encoding the address space mapping page to store the address space mapping page. By the method, the address space mapping table is stored after being compressed or encoded in a paging mode, so that the memory occupation of the address space mapping table can be reduced, and the performance of the solid state disk is prevented from being influenced.
Drawings
In order to more clearly illustrate the technical solutions of the present invention or the prior art, the following briefly introduces the drawings needed to be used in the description of the embodiments or the prior art, and obviously, the drawings in the following description are some embodiments of the present invention, and those skilled in the art can obtain other drawings according to the drawings without inventive labor.
Fig. 1 is a schematic view of an application scenario of a processing method for an address space mapping table according to an embodiment of the present application;
fig. 2 is a schematic flowchart of a processing method for an address space mapping table according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram illustrating a partitioning manner of an address space mapping table according to an embodiment of the present application;
FIG. 4 is a compression method for line compression or encoding according to an embodiment of the present application;
FIG. 5 is a compression method for column compression or encoding according to an embodiment of the present application;
fig. 6 is a flowchart illustrating another processing method for an address space mapping table according to an embodiment of the present application;
fig. 7 is a flowchart illustrating a processing method of an address space mapping table according to another embodiment of the present application;
fig. 8 is a flowchart illustrating a processing method of yet another address space mapping table according to an embodiment of the present application
Fig. 9 is a schematic structural diagram of a processing device of an address space mapping table according to an embodiment of the present application;
fig. 10 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Due to the characteristics of the storage medium of the solid state disk, the solid state disk often needs to maintain an address mapping table from a logical space to a physical space, which is used for recording the physical address of the logical data block actually stored in the solid state disk. In consideration of the practical requirements of upper layer applications, a common solid state disk is often a page size of 4 Kilobytes (KB) as the granularity of address mapping.
With the continuous increase of the capacity of the solid state disk, the address mapping table is also larger and larger. An 8 Terabyte (TB) solid state disk, which requires 8 Gigabytes (GB) of space at a mapping granularity of 4 KB. In consideration of performance, the address mapping table is generally cached in the memory, so that the large-capacity solid state disk also puts higher requirements on the capacity of the memory. If the memory capacity is not enough to accommodate the complete address mapping table, the address mapping table exceeding the memory space limit needs to be stored in other low-speed storage media, and the performance of the solid state disk is greatly affected at this time.
At present, the method for reducing the memory space occupation of the address space mapping table is mainly completed by increasing the mapping granularity of the address mapping table. For example, the 4KB mapping granularity is changed to 8KB, or the mapping is performed in a physical database (block) size of a flash memory (NAND). Although the memory occupation can be reduced by increasing the mapping granularity, when the upper-layer application performs random reading and writing of small blocks of data, the performance of the solid state disk still receives a large influence.
In order to solve the foregoing problems, embodiments of the present application provide a method and an apparatus for processing an address space mapping table, which can divide the address space mapping table into a plurality of address space mapping pages, so as to compress or encode the address space mapping pages and then store the address space mapping pages. By the method, the memory occupation amount of the address space mapping table can be reduced, and the influence on the performance of the solid state disk can be avoided.
An application scenario of the processing method of the address space mapping table according to the embodiment of the present application is described below.
Fig. 1 is a schematic application scenario diagram of a processing method for an address space mapping table according to an embodiment of the present application. As shown in fig. 1, when the solid state disk 102 is accessed in the terminal device 101, the address space mapping table to be stored may be obtained, and the address space mapping table is divided into a plurality of address space mapping pages, so that the address space mapping pages are stored by compressing or encoding the address space mapping pages.
The terminal device 101 may be a mobile phone (mobile phone), a tablet (pad), a computer with a wireless transceiving function, a Virtual Reality (VR) terminal device, an Augmented Reality (AR) terminal device, a wireless terminal in industrial control (industrial control), a wireless terminal in unmanned driving (self driving), a wireless terminal in remote surgery (remote medical supply), a wireless terminal in smart grid (smart grid), a wireless terminal in smart home (smart home), and the like. In the embodiment of the present application, the apparatus for implementing the function of the terminal may be the terminal, or may be an apparatus capable of supporting the terminal to implement the function, such as a chip system, and the apparatus may be installed in the terminal. In the embodiment of the present application, the chip system may be composed of a chip, and may also include a chip and other discrete devices.
The solid state disk 102, also known as a solid state drive, is a hard disk made of an array of solid state electronic memory chips. The embodiment of the application does not limit the type and model of the solid state disk, and any suitable type and model of solid state disk can be adopted.
The following describes in detail the technical solutions of the embodiments of the present application with specific embodiments, taking a terminal device integrated or installed with a relevant execution code as an example. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Fig. 2 is a flowchart illustrating a processing method of an address space mapping table according to an embodiment of the present application, which relates to a process of how to store the address space mapping table. As shown in fig. 2, the method includes:
s201, an address space mapping table to be stored is obtained, and the address space mapping table comprises address mapping from a logic space to a physical space.
In the application, when the solid state disk is accessed in the terminal device, the address space mapping table to be stored can be obtained, so that the address mapping from the logical space to the physical space is stored in the address space mapping table to record the physical address of the logical data block actually stored in the solid state disk.
S202, dividing the address space mapping table into a plurality of address space mapping pages.
In this step, after the terminal device obtains the address space mapping table to be stored, the address space mapping table may be divided into a plurality of address space mapping pages.
It should be understood that, in the embodiment of the present application, there is no limitation on how to divide the address space mapping table, and in some embodiments, the address space mapping table may be divided into a plurality of address space mapping pages according to a preset number of logical block addresses included in each set address space mapping page.
It should be noted that, in the embodiment of the present application, the number of Logical Block Addresses (LBAs) is not limited, and may be 128 Logical Block addresses for example.
For example, fig. 3 is a schematic diagram illustrating a dividing manner of an address space mapping table provided in the embodiment of the present application, as shown in fig. 3, when the address space mapping table is linearly arranged according to LBAs, each 128 consecutive LBAs exist may be divided into one address space mapping page. For example, LBA0 × 00 to LBA0 × 7F are divided into address space mapping page 0, and LBA0 × 80 to LBA0 × FF are divided into address space mapping page 1.
Each LBA corresponds to a Physical Block Address (PBA) and a corresponding Address offset and length, and is used for a solid state disk with a transparent compression function. With continued reference to fig. 1, in a common solid state disk, each LBA in the address mapping table corresponds to one PBA.
And S203, storing the address space mapping page by compressing or encoding the address space mapping page.
In this step, after the terminal device divides the address space mapping table into a plurality of address space mapping pages, the address space mapping pages may be stored by compressing or encoding the address space mapping pages.
The embodiment of the application does not limit how the address space mapping page is stored by compressing or encoding the address space mapping page, and for each address mapping page to be stored, a proper compression or encoding mode can be adopted to reduce the size of the address mapping page.
In some embodiments, if the difference between the compressed or encoded memory space of the address space mapping page and the uncompressed or unencoded memory space of the address space mapping page is less than the first threshold, the uncompressed or unencoded address space mapping page is stored. And if the difference value between the compressed or encoded storage space of the address space mapping page and the uncompressed or unencoded storage space of the address space mapping page is greater than or equal to a first threshold value, storing the compressed or encoded address space mapping page.
It should be noted that, in the embodiment of the present application, the size of the first threshold is not limited, and may be specifically set according to actual situations.
It should be noted that, the embodiment of the present application is not limited to the compression or encoding manner, and for example, a common compression algorithm, such as LZ4, Zlib, etc., may be used, and a common encoding algorithm, such as prefix encoding, run-length encoding, delta encoding, etc., may also be used.
In the application, the address mapping page to be stored can also be pre-judged, so that the address space mapping page with expected income larger than the threshold value is compressed or encoded, otherwise, the address space mapping page is stored in an uncompressed or unencoded mode. By the method, the effect of compressing or encoding the address space mapping page can be improved, and the overhead brought by compression or encoding can be reduced.
In some embodiments, the terminal device may first determine target data in the address space mapping page, where the target data includes repeated data and/or data with a coding rule. And if the proportion of the target data in the address space mapping page is greater than a second threshold value, storing the compressed or encoded address space mapping page. And if the proportion of the target data in the address space mapping page is less than or equal to a second threshold value, storing the uncompressed or uncoded address space mapping page.
It should be understood that the encoding rule of the target data is not limited in the embodiment of the present application, and the target data may be, for example, data in an arithmetic progression with a difference value of 2, such as 1, 3, 5, 7, and 9.
In other embodiments, the terminal device may predict a compression rate of the address space mapping page under the target compression algorithm. And if the compression rate is greater than a third threshold value, replacing the target compression algorithm.
The compression ratio can be understood as a value obtained by dividing the size before compression by the size after compression, and the target-replacing compression algorithm can be a compression algorithm with a lower complexity and a poorer compression effect by a compression algorithm with a higher complexity and a better compression effect. Illustratively, the LZ4 compression algorithm may be replaced with a Zlib compression algorithm.
It should be noted that, in the embodiment of the present application, the sizes of the second threshold and the third threshold are not limited, and may be specifically set according to actual situations.
In some embodiments, the compressing or encoding includes compressing or encoding the address space mapping page by column, compressing or encoding the address space mapping page by row, or performing multiple compression or encoding operations simultaneously and selecting the most space efficient manner as the final manner. For example, fig. 4 is a compression manner of row compression or encoding provided by an embodiment of the present application, and fig. 5 is a compression manner of column compression or encoding provided by an embodiment of the present application.
As shown in fig. 5, when compressing or encoding is performed in columns, the compression or encoding may be performed in terms of data fields (such as PBA, offset, and length), or in terms of bytes, or even in terms of bits, and each data field, byte, or bit column may be compressed or encoded separately, or may be compressed or encoded together after being combined, and each address mapping page may have a respective compression or encoding manner.
In some embodiments, the compression or encoding is performed by a solid state disk, a processor, or an acceleration unit. Accordingly, decompression or decoding may also be performed by a solid state disk, a processor, or an acceleration unit.
When the solid state disk is compressed or encoded, the drive of the solid state disk can run at a host end or in solid state disk equipment; when the driver is compressed or coded by the processor, the driver can run at the host end and can also run in the solid state disk device, when the driver runs at the host end, the processor is the host processor, and when the driver runs in the solid state disk device, the processor is the processor in the device; the acceleration unit may be, for example, a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC) module, or the like.
Optionally, after the address space mapping page is stored, when the driver accesses a certain address space mapping page, after the page is read, necessary decompression or decoding operations may be performed first to recover the original data, and then subsequent operations are performed.
In the application, the address space mapping table is firstly divided according to pages, and then each address control mapping page to be stored is appropriately compressed or encoded, so that the occupation of the memory space is reduced. When a certain address space mapping page needs to be accessed, the page can be read and necessary decompression or decoding operations can be performed. Through compression or encoding, the occupation of the memory space of the whole address space mapping table can be effectively reduced, and therefore the read-write performance of the solid state disk under normal load is ensured.
The processing method of the address space mapping table provided in the embodiment of the present application first obtains the address space mapping table to be stored, where the address space mapping table includes address mapping from a logical space to a physical space. Subsequently, the address space mapping table is divided into a plurality of address space mapping pages. Finally, the address space mapping page is stored by compressing or encoding the address space mapping page. By the method, the address space mapping table is stored after being compressed or encoded in a paging mode, so that the memory occupation of the address space mapping table can be reduced, and the performance of the solid state disk is prevented from being influenced.
On the basis of the above embodiments, the following describes a determination manner of whether the first address space mapping page needs to be compressed or encoded. Fig. 6 is a flowchart illustrating another processing method for an address space mapping table according to an embodiment of the present application, as shown in fig. 6, the method includes:
s301, an address space mapping table to be stored is obtained, and the address space mapping table comprises address mapping from a logic space to a physical space.
S302, the address space mapping table is divided into a plurality of address space mapping pages.
The address space mapping page comprises a preset number of logical block addresses.
S303, if the difference value between the compressed or encoded storage space of the address space mapping page and the uncompressed or unencoded storage space of the address space mapping page is smaller than a first threshold value, the uncompressed or unencoded address space mapping page is stored.
S304, if the difference value between the compressed or encoded storage space of the address space mapping page and the uncompressed or unencoded storage space of the address space mapping page is larger than or equal to a first threshold value, the compressed or encoded address space mapping page is stored.
The technical terms, technical effects, technical features, and alternative embodiments of S301 to S304 can be understood with reference to S201 to S204 shown in fig. 2, and repeated descriptions thereof will not be repeated here.
On the basis of the above embodiments, the following describes a determination manner of whether the second address space mapping page needs to be compressed or encoded. Fig. 7 is a flowchart illustrating a processing method of an address space mapping table according to another embodiment of the present application, as shown in fig. 7, the method includes:
s401, an address space mapping table to be stored is obtained, and the address space mapping table comprises address mapping from a logic space to a physical space.
S402, dividing the address space mapping table into a plurality of address space mapping pages.
The address space mapping page comprises a preset number of logical block addresses.
S403, determining target data in the address space mapping page, wherein the target data comprises repeated data and/or data with a coding rule.
S404, if the proportion of the target data in the address space mapping page is larger than a second threshold value, the compressed or coded address space mapping page is stored.
S405, if the proportion of the target data in the address space mapping page is smaller than or equal to a second threshold value, storing the uncompressed or uncoded address space mapping page.
The technical terms, technical effects, technical features, and alternative embodiments of S401 to S405 can be understood with reference to S201 to S204 shown in fig. 2, and repeated descriptions thereof will not be repeated here.
On the basis of the above-described embodiment, a description is given below of how to determine the target compression algorithm. Fig. 8 is a flowchart illustrating a processing method of another address space mapping table according to an embodiment of the present application, as shown in fig. 8, the method includes:
s501, an address space mapping table to be stored is obtained, and the address space mapping table comprises address mapping from a logic space to a physical space.
S502, the address space mapping table is divided into a plurality of address space mapping pages.
The address space mapping page comprises a preset number of logical block addresses.
S503, predicting the compression rate of the address space mapping page under the target compression algorithm.
And S504, if the compression rate is greater than the third threshold value, replacing the target compression algorithm.
And S505, compressing or encoding the address space mapping page to store the address space mapping page.
The technical terms, technical effects, technical features, and alternative embodiments of S501-S505 can be understood with reference to S201-S204 shown in fig. 2, and repeated descriptions will not be repeated here.
The processing method of the address space mapping table provided in the embodiment of the present application first obtains the address space mapping table to be stored, where the address space mapping table includes address mapping from a logical space to a physical space. Subsequently, the address space mapping table is divided into a plurality of address space mapping pages. Finally, the address space mapping page is stored by compressing or encoding the address space mapping page. By the method, the address space mapping table is stored after being compressed or encoded in a paging mode, so that the memory occupation of the address space mapping table can be reduced, and the performance of the solid state disk is prevented from being influenced.
Those of ordinary skill in the art will understand that: all or part of the steps for implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer readable storage medium, and when executed, the program performs the steps including the method embodiments; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Fig. 9 is a schematic structural diagram of a processing device of an address space mapping table according to an embodiment of the present application. The processing device of the address space mapping table may be implemented by software, hardware, or a combination of the two, and may be, for example, the terminal device or the chip of the terminal device in the foregoing embodiment, so as to execute the processing method of the address space mapping table in the foregoing embodiment. As shown in fig. 9, the processing device 600 of the address space mapping table includes:
an obtaining module 601, configured to obtain an address space mapping table to be stored, where the address space mapping table includes address mappings from logical spaces to physical spaces;
a dividing module 602, configured to divide the address space mapping table into a plurality of address space mapping pages;
the storage module 603 is configured to store the address space mapping page by compressing or encoding the address space mapping page.
In an alternative embodiment, the address space mapping page contains a predetermined number of logical block addresses.
In an optional implementation manner, the storage module 603 is specifically configured to store the uncompressed or unencoded address space mapping page if a difference between the compressed or encoded storage space of the address space mapping page and the uncompressed or unencoded storage space of the address space mapping page is less than a first threshold; and if the difference value between the compressed or encoded storage space of the address space mapping page and the uncompressed or unencoded storage space of the address space mapping page is greater than or equal to a first threshold value, storing the compressed or encoded address space mapping page.
In an optional implementation manner, the storage module 603 is specifically configured to determine target data in the address space mapping page, where the target data includes repeated data and/or data with an encoding rule; if the proportion of the target data in the address space mapping page is larger than a second threshold value, storing the compressed or encoded address space mapping page; and if the proportion of the target data in the address space mapping page is less than or equal to a second threshold value, storing the uncompressed or uncoded address space mapping page.
In an alternative embodiment, the apparatus further comprises:
a prediction module 604 for predicting a compression rate of the address space mapping page under the target compression algorithm; and if the compression rate is greater than a third threshold value, replacing the target compression algorithm.
In an alternative embodiment, the compressing or encoding includes compressing or encoding the address space mapping page by columns, or compressing or encoding the address space mapping page by rows.
In an alternative embodiment, the compression or encoding is performed by a solid state drive, a processor, or an acceleration unit.
It should be noted that the processing apparatus for the address space mapping table provided in the embodiment shown in fig. 9 may be configured to execute the method provided in any of the above embodiments, and the specific implementation manner and the technical effect are similar, and are not described herein again.
Fig. 10 is a schematic structural diagram of an electronic device according to an embodiment of the present application. As shown in fig. 10, the electronic device may include: at least one processor 701 and a memory 702. Fig. 10 shows an electronic device as an example of a processor.
And a memory 702 for storing programs. In particular, the program may include program code including computer operating instructions.
The memory 702 may comprise high-speed RAM memory, and may also include non-volatile memory (non-volatile memory), such as at least one disk memory.
The processor 701 is configured to execute a computer-executable instruction stored in the memory 702 to implement the processing method of the address space mapping table;
the processor 701 may be a Central Processing Unit (CPU), an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits configured to implement the embodiments of the present Application.
Optionally, in a specific implementation, if the communication interface, the memory 702 and the processor 701 are implemented independently, the communication interface, the memory 702 and the processor 701 may be connected to each other through a bus and perform communication with each other. The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended ISA (EISA) bus, or the like. Buses may be classified as address buses, data buses, control buses, etc., but do not represent only one bus or type of bus.
Alternatively, in a specific implementation, if the communication interface, the memory 702 and the processor 701 are integrated into a chip, the communication interface, the memory 702 and the processor 701 may complete communication through an internal interface.
The embodiment of the application also provides a chip which comprises a processor and an interface. Wherein the interface is used for inputting and outputting data or instructions processed by the processor. The processor is configured to perform the methods provided in the above method embodiments. The chip can be applied to a processing device of an address space mapping table.
The present application also provides a computer-readable storage medium, which may include: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, are used, and specifically, the computer-readable storage medium stores program information, and the program information is used in the processing method of the address space mapping table.
The embodiments of the present application further provide a program, which when executed by a processor, is configured to perform the processing method of the address space mapping table provided in the above method embodiments.
Embodiments of the present application further provide a program product, such as a computer-readable storage medium, where instructions are stored in the program product, and when the program product runs on a computer, the program product causes the computer to execute the processing method of the address space mapping table provided in the foregoing method embodiments.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. The procedures or functions according to the embodiments of the invention are brought about in whole or in part when the computer program instructions are loaded and executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wirelessly (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (17)

1. A method for processing an address space mapping table, the method comprising:
acquiring an address space mapping table to be stored, wherein the address space mapping table comprises address mapping from a logic space to a physical space;
dividing the address space mapping table into a plurality of address space mapping pages;
and storing the address space mapping page by compressing or encoding the address space mapping page.
2. The method of claim 1, wherein the address space mapping page contains a preset number of logical block addresses.
3. The method of claim 1, wherein storing the address space mapping page by compressing or encoding the address space mapping page comprises:
if the difference value between the compressed or encoded storage space of the address space mapping page and the uncompressed or unencoded storage space of the address space mapping page is smaller than a first threshold value, storing the uncompressed or unencoded address space mapping page;
and if the difference value between the compressed or encoded storage space of the address space mapping page and the uncompressed or unencoded storage space of the address space mapping page is greater than or equal to a first threshold value, storing the compressed or encoded address space mapping page.
4. The method of claim 1, wherein storing the address space mapping page by compressing or encoding the address space mapping page comprises:
determining target data in the address space mapping page, wherein the target data comprises repeated data and/or data with a coding rule;
if the proportion of the target data in the address space mapping page is larger than a second threshold value, storing the compressed or encoded address space mapping page;
and if the proportion of the target data in the address space mapping page is less than or equal to a second threshold value, storing the uncompressed or uncoded address space mapping page.
5. The method according to any of claims 1-4, wherein before said storing said address space mapping page by compressing or encoding said address space mapping page, said method further comprises:
predicting a compression ratio of the address space mapping page under a target compression algorithm;
and if the compression rate is greater than a third threshold value, replacing the target compression algorithm.
6. The method of any of claims 1-4, wherein the compressing or encoding comprises compressing or encoding the address space mapping page by column or compressing or encoding the address space mapping page by row.
7. The method of any of claims 1-4, wherein the compressing or encoding is performed by a solid state drive, a processor, or an acceleration unit.
8. An apparatus for processing an address space mapping table, the apparatus comprising:
the device comprises an acquisition module, a storage module and a storage module, wherein the acquisition module is used for acquiring an address space mapping table to be stored, and the address space mapping table comprises address mapping from a logic space to a physical space;
the dividing module is used for dividing the address space mapping table into a plurality of address space mapping pages;
and the storage module is used for storing the address space mapping page by compressing or encoding the address space mapping page.
9. The apparatus of claim 8, wherein the address space mapping page contains a preset number of logical block addresses.
10. The apparatus according to claim 8, wherein the storage module is specifically configured to store the uncompressed or unencoded address space map page if a difference between a compressed or encoded storage space of the address space map page and an uncompressed or unencoded storage space of the address space map page is smaller than a first threshold; and if the difference value between the compressed or encoded storage space of the address space mapping page and the uncompressed or unencoded storage space of the address space mapping page is greater than or equal to a first threshold value, storing the compressed or encoded address space mapping page.
11. The apparatus according to claim 8, wherein the storage module is specifically configured to determine target data in the address space mapping page, where the target data includes repeated data and/or data with a coding rule; if the proportion of the target data in the address space mapping page is larger than a second threshold value, storing the compressed or encoded address space mapping page; and if the proportion of the target data in the address space mapping page is less than or equal to a second threshold value, storing the uncompressed or uncoded address space mapping page.
12. The apparatus according to any one of claims 8-11, further comprising:
the prediction module is used for predicting the compression rate of the address space mapping page under a target compression algorithm; and if the compression rate is greater than a third threshold value, replacing the target compression algorithm.
13. The apparatus of any of claims 8-11, wherein the compressing or encoding comprises compressing or encoding the address space mapping page by column or compressing or encoding the address space mapping page by row.
14. The apparatus of any of claims 8-11, wherein the compressing or encoding is performed by a solid state drive, a processor, or an acceleration unit.
15. A computer program product comprising a computer program, characterized in that the computer program realizes the method of any of claims 1-7 when executed by a processor.
16. A computer storage medium, characterized in that it stores a plurality of instructions adapted to be loaded by a processor and to perform the method steps according to any of claims 1-7.
17. An electronic device, comprising: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to perform the method according to any of claims 1-7.
CN202111483902.1A 2021-12-07 2021-12-07 Method and device for processing address space mapping table Pending CN114385517A (en)

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Application Number Priority Date Filing Date Title
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