CN106202213B - FPGA binary file compression and decompression method and device - Google Patents
FPGA binary file compression and decompression method and device Download PDFInfo
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- 230000006835 compression Effects 0.000 title claims abstract description 59
- 238000000034 method Methods 0.000 title claims abstract description 33
- 230000006837 decompression Effects 0.000 title abstract description 24
- 230000009286 beneficial effect Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 3
- 230000006870 function Effects 0.000 description 11
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
- G06F16/10—File systems; File servers
- G06F16/17—Details of further file system functions
- G06F16/174—Redundancy elimination performed by the file system
- G06F16/1744—Redundancy elimination performed by the file system using compression, e.g. sparse files
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
Abstract
The invention is suitable for the technical field of FPGA, and provides a method and a device for compressing and decompressing an FPGA binary file, wherein the compression method comprises the following steps: acquiring an FPGA binary file; traversing the content of the FPGA binary file, classifying the content, and judging classification data and a data area where the classification data is located; adopting a coding storage mode corresponding to the data area to code and store the classified data; and according to a general compression algorithm, integrally compressing the classified data of which the information entropy is smaller than a set value. The invention has the following beneficial effects: 1) analyzing the structural characteristics of the FPGA binary file, and dividing the FPGA binary file into several specific types of data areas. Different encoding modes are adopted for different data areas for compression storage, so that the file storage space is greatly reduced; 2) the method uses the length, the type and the data value for storage, and is particularly effective for application scenes of one-time compression and multiple-time decompression. The decompression speed is far greater than the compression speed, and the decompression effect is improved.
Description
Technical Field
the invention belongs to the technical field of FPGA, and particularly relates to a method and a device for compressing and decompressing an FPGA binary file.
background
data compression is a technical method for reducing the data volume to reduce the storage space and improve the transmission, storage and processing efficiency of the data on the premise of not losing useful information, or for reorganizing the data according to a certain algorithm and reducing the redundancy and storage space of the data. The existing compression algorithm takes general compression as a main stream, and LZMA, GZIP, RAR and the like are general compression algorithms.
However, the current general compression algorithm cannot perform optimized compression according to the data type of the FPGA binary file, which is not beneficial to improving the overall compression ratio and the overall compression performance. The reason is that the current general compression algorithm is oriented to all data fields, and the FPGA binary file cannot be specially processed, so that the overall compression ratio and the overall compression performance of the FPGA binary file are not high.
disclosure of Invention
the embodiment of the invention aims to provide a method for compressing an FPGA binary file, and aims to solve the problems that the conventional general compression algorithm cannot optimize compression according to the data type of the FPGA binary file and is not beneficial to improving the whole compression ratio and the whole compression performance.
The embodiment of the invention is realized in such a way that an FPGA binary file compression method comprises the following steps:
acquiring an FPGA binary file;
traversing the content of the FPGA binary file, classifying the content, and judging classification data and a data area where the classification data is located;
adopting a coding storage mode corresponding to the data area to code and store the classified data;
And according to a general compression algorithm, integrally compressing the classified data of which the information entropy is smaller than a set value.
another object of an embodiment of the present invention is to provide a method for decompressing an FPGA binary file, including:
according to a general decompression algorithm, carrying out integral decompression on classified data with the information entropy smaller than a set value;
decoding and storing the data in the data area by adopting a coding storage mode corresponding to the data area;
restoring the classified contents according to the classification data and the data area where the classification data is located to obtain the contents of the traversal FPGA binary file;
And restoring the FPGA binary file according to the obtained content.
another object of an embodiment of the present invention is to provide an FPGA binary file compression apparatus, including:
The FPGA binary file acquisition module is used for acquiring an FPGA binary file;
The judging module is used for traversing the content of the FPGA binary file, classifying the content and judging classified data and a data area where the classified data is located;
the code storage module is used for coding and storing the classified data by adopting a code storage mode corresponding to the data area;
and the compression module is used for integrally compressing the classified data of which the information entropy is smaller than a set value according to a general compression algorithm.
another object of an embodiment of the present invention is to provide an FPGA binary file decompression apparatus, including:
the integral decompression module is used for integrally decompressing the classified data of which the information entropy is smaller than a set value according to a general decompression algorithm;
the decoding module is used for decoding and storing the data in the data area by adopting a coding storage mode corresponding to the data area;
The content reduction module is used for reducing the classified content according to the classification data and the data area where the classification data is located to obtain the content of the traversal FPGA binary file;
The FPGA binary file restoration module is used for restoring the FPGA binary file according to the obtained content
in the embodiment of the invention, the content of the FPGA binary file is traversed, the content is classified, and classified data and a data area where the classified data is located are judged; adopting a coding storage mode corresponding to the data area to code and store the classified data; and according to a general compression algorithm, integrally compressing the classified data of which the information entropy is smaller than a set value. Therefore, the problem that the conventional general compression algorithm cannot optimize compression according to the data type of the FPGA binary file and is not beneficial to improving the overall compression ratio and the overall compression performance is solved. The beneficial effects are as follows:
1) analyzing the structural characteristics of the FPGA binary file, and dividing the FPGA binary file into several specific types of data areas. Different encoding modes are adopted for different data areas for compression storage, so that the file storage space is greatly reduced;
2) The method uses the length, the type and the data value for storage, and is particularly effective for application scenes of one-time compression and multiple-time decompression. The decompression speed is far greater than the compression speed, and the decompression effect is improved.
Drawings
fig. 1 is a flowchart of an implementation of a method for compressing an FPGA binary file according to an embodiment of the present invention;
fig. 2 is a flowchart of implementing step S102 of the FPGA binary file compression method according to the embodiment of the present invention;
Fig. 3 is a flowchart of implementing step S103 of the FPGA binary file compression method according to the embodiment of the present invention;
Fig. 4 is a flowchart of an implementation of a method for decompressing an FPGA binary file according to an embodiment of the present invention;
FIG. 5 is a flowchart illustrating a preferred implementation of the FPGA binary file compression method in practical applications according to an embodiment of the present invention;
Fig. 6 is a block diagram of an FPGA binary file compression apparatus according to an embodiment of the present invention;
fig. 7 is a block diagram of a structure of an FPGA binary file decompression apparatus according to an embodiment of the present invention.
Detailed Description
in order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
example one
fig. 1 is a flowchart of an implementation of the FPGA binary file compression method according to the embodiment of the present invention, which is detailed as follows:
in step S101, an FPGA binary file is acquired;
in step S102, traversing the content of the FPGA binary file, classifying the content, and determining classification data and a data area where the classification data is located;
Wherein the data area includes: the data processing device comprises a fixed data area, a repeated data area, a sparse data area and a random data area;
the fixed data area is: a data area shared by each FPGA binary file;
the repeated data area is as follows: a data area storing all 0 s or all 1 s;
The sparse data area is: a data area storing four bytes of data;
the random data area is: a data area for storing random data.
In step S103, encoding and storing the classified data by using an encoding storage manner corresponding to the data area;
in step S104, the classified data whose information entropy is smaller than the set value is compressed as a whole according to the general compression algorithm.
the following principles are followed in the process of partitioning:
the maximum length of each block is 0x0 FFF.
(A) bit30-bit31 bits are used to indicate the type of partition;
00: fixed data area;
01: repeating the data region;
10: a sparse data region;
11: and a random data area.
(B) bit28-bit29 bits are used to indicate the length of a data unit 00:
data in units of one byte;
01: data in units of two bytes;
10: data in units of four bytes;
11: data in units of eight bytes is used to indicate the data unit size of the sparse data area and the repeated data area.
the blocks are sequentially arranged, and all the blocks are calculated according to relative positions.
in the embodiment of the invention, the beneficial effects are as follows:
1) analyzing the structural characteristics of the FPGA binary file, and dividing the FPGA binary file into several specific types of data areas. Different encoding modes are adopted for different data areas for compression storage, so that the file storage space is greatly reduced;
2) the method uses the length, the type and the data value for storage, and is particularly effective for application scenes of one-time compression and multiple-time decompression. The decompression speed is far greater than the compression speed, and the decompression effect is improved.
example two
fig. 2 is a flowchart of implementing step S102 of the FPGA binary file compression method according to the embodiment of the present invention, which is detailed as follows:
in step S201, traversing the contents of the FPGA binary file;
in step S202, the content is classified according to the traversed content and the pre-configured data area determination function, and the classification data and the data area where the classification data is located are determined.
EXAMPLE III
the embodiment of the present invention describes an implementation flowchart of a configuration data area determination function, which is detailed as follows:
a configuration data area determination function, specifically including:
Configuring a repeated data area, a sparse data area and a random data area:
and the data area is determined as a repeated data area by taking a single byte as a unit data repetition, taking a double byte as a unit data repetition and taking a four byte as a unit data repetition, and the area which lasts for a first set range.
taking four bytes as a unit, keeping 3 high-order bytes unchanged, changing the data of the 4 th byte, and continuously judging the area with a larger range as a sparse data area;
Judging the region with no rule except the two or the continuous range of the repeated data and the sparse data as a random data region in a second set range;
Configuring a judging function of a sparse data area and a repeated data area:
sparse data less than a set number are sandwiched between the two repeated data areas, and are preferentially stored according to the mode of the sparse data areas;
when the size of the sparse data area is larger than a fixed value N and the sparse data area is larger than 30% of the repeated data, respectively storing the sparse data area and the repeated data area;
the judgment function of the random data area and the sparse data area is configured:
Random data less than a set number is sandwiched between the two sparse data areas, and the random data is converted into sparse data to be stored.
and when the size of the random data area is larger than a fixed value N, respectively storing the random data area and the sparse data area.
and (3) configuring a judging function of the random data area and the repeated data area:
random data less than a set number is sandwiched between the two repeated data areas, and the random data is converted into sparse data to be stored.
And when the size of the random data area is larger than a fixed value N, respectively storing the random data area and the repeated data area.
Example four
fig. 3 is a flowchart of implementing step S103 of the FPGA binary file compression method according to the embodiment of the present invention, which is detailed as follows:
in step S301, when the data area is a fixed data area, no processing is performed;
in step S302, when the data region is a duplicate data region, the location and length of the duplicate data region and the content of the duplicate data are identified according to a duplicate flag;
In step S303, when the data area is a sparse data area, the first three bytes are omitted, only the last byte is saved, and the position and length of the sparse data area are identified according to a sparse flag;
in step S304, when the data area is a random data area, the position and length of the random data area are identified according to the random data flag.
EXAMPLE five
fig. 4 is a flowchart of an implementation of the FPGA binary file decompression method according to the embodiment of the present invention, which is detailed as follows:
in step S401, according to a general decompression algorithm, carrying out integral decompression on classified data of which the information entropy is smaller than a set value;
In step S402, decoding and storing the data in the data area by using the encoding storage manner corresponding to the data area;
in step S403, restoring the classified content according to the classification data and the data area where the classification data is located, to obtain the content of the traversal FPGA binary file;
in step S404, the FPGA binary file is restored according to the obtained content.
EXAMPLE six
fig. 5 is a flowchart illustrating a preferred implementation of the FPGA binary file compression method in practical application according to an embodiment of the present invention, which is detailed as follows:
Reading an FPGA binary file;
scanning a file and classifying data blocks;
Merging and adjusting the data blocks according to categories;
Each data block is classified, coded and stored;
The newly generated file calls the LZMA general compression algorithm for compression.
EXAMPLE seven
fig. 6 is a block diagram of an FPGA binary file compression apparatus according to an embodiment of the present invention, where the apparatus may be implemented in an electronic device. For convenience of explanation, only the portions related to the present embodiment are shown.
an FPGA binary file obtaining module 61, configured to obtain an FPGA binary file;
the judging module 62 is configured to traverse the content of the FPGA binary file, classify the content, and judge the classified data and the data area where the classified data is located;
the code storage module 63 is used for coding and storing the classified data by adopting a code storage mode corresponding to the data area;
And the compression module 64 is used for integrally compressing the classified data of which the information entropy is smaller than the set value according to a general compression algorithm.
as an implementation manner of this embodiment, in the FPGA binary file compressing apparatus, the determining module includes:
the traversal unit is used for traversing the content of the FPGA binary file;
And the judging unit is used for classifying the contents according to the traversed contents and the pre-configured data area judging function, and judging the classified data and the data area where the classified data is located.
as an implementation manner of this embodiment, in the FPGA binary file compressing apparatus, the drawing control layer transfer module further includes:
the FPGA binary file compression method further comprises the following steps:
a configuration data area determination function, specifically including:
configuring a repeated data area, a sparse data area and a random data area:
and the data area is determined as a repeated data area by taking a single byte as a unit data repetition, taking a double byte as a unit data repetition and taking a four byte as a unit data repetition, and the area which lasts for a first set range.
taking four bytes as a unit, keeping 3 high-order bytes unchanged, changing the data of the 4 th byte, and continuously judging the area with a larger range as a sparse data area;
Judging the region with no rule except the two or the continuous range of the repeated data and the sparse data as a random data region in a second set range;
Configuring a judging function of a sparse data area and a repeated data area:
sparse data less than a set number are sandwiched between the two repeated data areas, and are preferentially stored according to the mode of the sparse data areas;
When the size of the sparse data area is larger than a fixed value N and the sparse data area is larger than 30% of the repeated data, respectively storing the sparse data area and the repeated data area;
the judgment function of the random data area and the sparse data area is configured:
random data less than a set number is sandwiched between the two sparse data areas, and the random data is converted into sparse data to be stored.
And when the size of the random data area is larger than a fixed value N, respectively storing the random data area and the sparse data area.
And (3) configuring a judging function of the random data area and the repeated data area:
Random data less than a set number is sandwiched between the two repeated data areas, and the random data is converted into sparse data to be stored.
And when the size of the random data area is larger than a fixed value N, respectively storing the random data area and the repeated data area.
as an implementation manner of this embodiment, in the FPGA binary file compressing apparatus, the encoding storage module includes:
a fixed data area code storage unit, which is used for not processing when the data area is a fixed data area;
the repeated data region coding and storing unit is used for identifying the position and the length of the repeated data region and repeated data content according to the repeated mark when the data region is the repeated data region;
the sparse data area coding storage unit is used for saving the first three bytes when the data area is a sparse data area, only storing the last byte, and identifying the position and the length of the sparse data area according to a sparse mark;
And the random data area coding storage unit is used for identifying the position and the length of the random data area according to a random data mark when the data area is the random data area.
the apparatus provided in the embodiment of the present invention may be applied to the corresponding method embodiment, and details of the implementation process refer to the description of the embodiment described above, which are not described herein again.
Example nine
Fig. 7 is a block diagram of a structure of an FPGA binary file decompression apparatus according to an embodiment of the present invention, where the apparatus may be implemented in an electronic device. For convenience of explanation, only the portions related to the present embodiment are shown.
Referring to fig. 7, the FPGA binary file decompression apparatus includes:
The integral decompression module 71 is used for integrally decompressing the classified data of which the information entropy is smaller than the set value according to the general decompression algorithm;
A decoding module 72, configured to decode and store the data in the data area by using the encoding storage manner corresponding to the data area;
the content restoration module 73 is configured to restore the classified content according to the classification data and the data area where the classification data is located, so as to obtain the content of the traversal FPGA binary file;
and the FPGA binary file restoration module 74 is used for restoring the FPGA binary file according to the obtained content.
the apparatus provided in the embodiment of the present invention may be applied to the corresponding method embodiment, and details of the implementation process refer to the description of the embodiment described above, which are not described herein again.
Through the above description of the embodiments, those skilled in the art will clearly understand that the present invention can be implemented by software plus necessary general hardware. The program may be stored in a readable storage medium, such as a random access memory, a flash memory, a read only memory, a programmable read only memory, an electrically erasable programmable memory, a register, and the like. The storage medium is located in a memory, and a processor reads information in the memory and performs the method according to the embodiments of the present invention in combination with hardware thereof.
the above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (4)
1. an FPGA binary file compression method is characterized by comprising the following steps:
acquiring an FPGA binary file;
traversing the content of the FPGA binary file, classifying the content, and judging classification data and a data area where the classification data is located;
adopting a coding storage mode corresponding to the data area to code and store the classified data;
according to a general compression algorithm, integrally compressing classified data of which the information entropy is smaller than a set value;
the method comprises the following steps of traversing the content of the FPGA binary file, classifying the content, and judging classification data and a data area where the classification data is located, wherein the specific steps are as follows:
traversing the content of the FPGA binary file;
classifying the contents according to the traversed contents and a pre-configured data area judgment function, and judging classified data and a data area where the classified data is located;
the FPGA binary file compression method further comprises the following steps:
a configuration data area determination function, specifically including:
Configuring a repeated data area, a sparse data area and a random data area:
repeating data by taking a single byte as a unit, repeating data by taking double bytes as a unit, and determining the data area by taking four bytes as a unit data repetition as a repeated data area continuously in an area of a first set range;
configuring a judging function of a sparse data area and a repeated data area:
Sparse data less than a set number are sandwiched between the two repeated data areas, and are preferentially stored according to the mode of the sparse data areas;
when the size of the sparse data area is larger than a fixed value N and the sparse data area is larger than 30% of the repeated data, respectively storing the sparse data area and the repeated data area;
The judgment function of the random data area and the sparse data area is configured:
random data less than a set number are clamped between the two sparse data areas, and the random data are converted into sparse data to be stored;
when the size of the random data area is larger than a fixed value N, respectively storing the random data area and the sparse data area;
and (3) configuring a judging function of the random data area and the repeated data area:
random data less than a set number are sandwiched between the two repeated data areas, and the random data are converted into sparse data to be stored;
And when the size of the random data area is larger than a fixed value N, respectively storing the random data area and the repeated data area.
2. The method according to claim 1, wherein the encoding storage mode corresponding to the data area is adopted to encode and store classified data, and specifically:
when the data area is a fixed data area, no processing is carried out;
when the data area is a repeated data area, identifying the position and the length of the repeated data area and repeated data content according to a repeated mark;
When the data area is a sparse data area, the first three bytes are saved, only the last byte is saved, and the position and the length of the sparse data area are identified according to a sparse mark;
And when the data area is a random data area, identifying the position and the length of the random data area according to the random data mark.
3. an FPGA binary file compression device, comprising:
the FPGA binary file acquisition module is used for acquiring an FPGA binary file;
the judging module is used for traversing the content of the FPGA binary file, classifying the content and judging classified data and a data area where the classified data is located;
the code storage module is used for coding and storing the classified data by adopting a code storage mode corresponding to the data area;
the compression module is used for integrally compressing the classified data of which the information entropy is smaller than a set value according to a general compression algorithm;
the determination module includes:
The traversal unit is used for traversing the content of the FPGA binary file;
the judging unit is used for classifying the contents according to the traversed contents and the pre-configured data area judging function, and judging the classified data and the data area where the classified data is located;
the determination unit is further configured to:
A configuration data area determination function, specifically including:
configuring a repeated data area, a sparse data area and a random data area:
repeating data by taking a single byte as a unit, repeating data by taking double bytes as a unit, and determining the data area by taking four bytes as a unit data repetition as a repeated data area continuously in an area of a first set range;
Configuring a judging function of a sparse data area and a repeated data area:
Sparse data less than a set number are sandwiched between the two repeated data areas, and are preferentially stored according to the mode of the sparse data areas;
When the size of the sparse data area is larger than a fixed value N and the sparse data area is larger than 30% of the repeated data, respectively storing the sparse data area and the repeated data area;
the judgment function of the random data area and the sparse data area is configured:
random data less than a set number are clamped between the two sparse data areas, and the random data are converted into sparse data to be stored;
when the size of the random data area is larger than a fixed value N, respectively storing the random data area and the sparse data area;
and (3) configuring a judging function of the random data area and the repeated data area:
random data less than a set number are sandwiched between the two repeated data areas, and the random data are converted into sparse data to be stored;
and when the size of the random data area is larger than a fixed value N, respectively storing the random data area and the repeated data area.
4. the FPGA binary file compression device of claim 3, wherein said code storage module comprises:
a fixed data area code storage unit, which is used for not processing when the data area is a fixed data area;
the repeated data region coding and storing unit is used for identifying the position and the length of the repeated data region and repeated data content according to the repeated mark when the data region is the repeated data region;
the sparse data area coding storage unit is used for saving the first three bytes when the data area is a sparse data area, only storing the last byte, and identifying the position and the length of the sparse data area according to a sparse mark;
and the random data area coding storage unit is used for identifying the position and the length of the random data area according to a random data mark when the data area is the random data area.
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| CN111427857B (en) * | 2020-04-01 | 2022-10-25 | 西安交通大学 | FPGA configuration file compression and decompression method based on partition reference technology |
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| CN115499016A (en) * | 2022-11-15 | 2022-12-20 | 中科声龙科技发展（北京）有限公司 | Method, device and equipment for processing data based on binary system and storage medium |
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