CN114374589A

CN114374589A - PSS cross-correlation algorithm of 5G-NR system based on FPGA

Info

Publication number: CN114374589A
Application number: CN202210027697.6A
Authority: CN
Inventors: 庞军; 王刚
Original assignee: Shenzhen Fanweitai Technology Service Co ltd
Current assignee: Shenzhen Fanweitai Technology Service Co ltd
Priority date: 2022-01-11
Filing date: 2022-01-11
Publication date: 2022-04-19

Abstract

The invention provides a PSS cross-correlation algorithm of a 5G-NR system based on an FPGA, which comprises the following steps: the low-frequency clock is written into a single sampling point in sequence, and a received data stream is stored in a delay line structure consisting of 256 registers, wherein the received data comprises a real part I and an imaginary part Q, and the I and the Q have respective delay line structures; reading out sampling points with the length of 1 symbol by a high-frequency clock according to a staggered sequence, wherein only the back 255 sampling points of the 1 symbol are read out, and the first point is removed; folding and adding the real parts; the imaginary part is doubled and subtracted; time division multiplexing completes the complex multiplication of the local PSS waveform. When the PSS cross-correlation operation is calculated in the FPGA, the consumption of FPGA multiplier and RAM resources is greatly reduced, the capacity of FPGA devices is reduced, and the cost and the equipment power consumption are reduced.

Description

PSS cross-correlation algorithm of 5G-NR system based on FPGA

Technical Field

The invention relates to the technical field of communication, in particular to a PSS cross-correlation algorithm of a 5G-NR system based on an FPGA.

Background

The 5G-NR is a global 5G standard based on a brand-new air interface design of OFDM and is also a very important cellular mobile technology foundation of a new generation, and the 5G technology can realize ultralow time delay and high reliability. In a 5G communication system, a User Equipment (UE) needs to search a cell first to synchronize with a base station when accessing a network. The 5G-NR base station will periodically send a synchronization signal in the downlink for the user terminal UE to detect and synchronize. The Synchronization Signal includes two parts, a Primary Synchronization Signal (PSS) and a Secondary Synchronization Signal (SSS). 5G defines 1008 Physical Cell-IDs, and the value range is 0-1007. The UE must demodulate PSS to obtain N _ ID _2, demodulate SSS to obtain N _ ID _1, and then calculate the Physical Cell-ID information from N _ ID _1 and N _ ID _ 2. And the PSS and the SSS are demodulated, and the accurate frequency offset and time offset can be estimated and synchronized with the time domain and the frequency domain of the base station. The UE can obtain the symbol boundary of the system frame by detecting the PSS sequence, obtain the symbol length, and complete time synchronization at symbol level.

The PSS is a binary pseudo-random sequence comprising 127 frequency domain complex samples occupying subcarriers 57-183. The sub-carrier bandwidth is 4, 15Khz, 30Khz, 120Khz and 240Khz respectively. For the detection of the PSS subcarrier bandwidth, a blind solution is required, the subcarrier bandwidth is tried one by one, and the subcarrier bandwidth is determined as the PSS is successfully synchronized. In addition, the value ranges of N _ ID _2 are 0,1, and 2, which correspond to the three PSS sequences, respectively, for the detection of the PSS sequence type, blind solution is also required, sequence-by-sequence attempts are performed, and the PSS sequence type is also determined when the PSS is successfully synchronized.

For the detection of the PSS signal in the FPGA, the peak value is usually matched through time domain signal cross-correlation operation, so as to find the position of the PSS signal in the received signal, that is, 12 standard PSS reference sequence time domain waveforms are stored in the local RAM of the FPGA, cross-correlation operation is tried to be performed with the received signal one by one, the data involved in the operation are complex, and the complex cross-correlation operation needs to process 4 parallel data streams at the same time. It can be seen that the operation amount is very large, a large number of multipliers and RAM memory resources of the FPGA are consumed, the capacity of the FPGA device is increased, and the cost and the equipment power consumption are increased.

Disclosure of Invention

The invention provides a PSS cross-correlation algorithm of a 5G-NR system based on an FPGA (field programmable gate array) to solve at least one technical problem.

To solve the above problems, as an aspect of the present invention, there is provided a PSS cross-correlation algorithm for a 5G-NR system based on an FPGA, including:

step 1, a low-frequency clock is written into a single sampling point in sequence, and a received data stream is stored in a delay line structure consisting of 256 registers, wherein the received data comprises a real part I and an imaginary part Q, and both the I and the Q have respective delay line structures;

step 2, reading out sampling points with the length of 1 symbol by the high-frequency clock according to a staggered sequence, wherein only the back 255 sampling points of the 1 symbol are read out, and the first point is removed;

step 3, folding and adding the real parts;

step 4, doubling and subtracting the imaginary part;

and 5, completing the complex multiplication of the local PSS waveform by time division multiplexing.

Preferably, in step 1, in each clock cycle, the data at register addresses 1-255 are sequentially shifted, the data at register addresses 0-254 are covered, and the newly entered sampling points are stored in register address 255 to form a delay line structure.

Preferably, in

step

2, 16 points are read out from the delay line Data _ Buff _ I every high frequency clock cycle, wherein 8 points are stored in the register set Data _ I _ invt1, and the other 8 points are stored in the register set Data _ I _ invt 2.

Preferably, the first 15 high frequency clock cycles in each low frequency clock cycle read out 16 points from the delay line respectively; only 15 dots are read for the last high frequency clock cycle in each low frequency clock cycle, 7 dots being placed in the register set Data _ I _ invt2 and one 0 being complemented, 8 dots being placed in the register set Data _ I _ invt 1.

Preferably, in step 2, the Data placed in the register group Data _ I _ invt1 are read out in order of increasing addresses, and the Data placed in the register group Data _ I _ invt2 are read out in order of decreasing addresses.

Preferably, in step 3, the Data of the register set Data _ I _ invt1 are added to the Data of the register set Data _ I _ invt2, respectively.

Preferably, in step 4, the Data of the register set Data _ I _ invt2 is subtracted from the Data of the register set Data _ I _ invt1, respectively.

Preferably, in

step

5, 16 points under the high-frequency clock are input to 1 multiplier in a pipeline manner to realize N-time multiplexing, where N is a frequency multiple of the high-frequency clock relative to the low-frequency clock.

Due to the adoption of the technical scheme, when the PSS cross-correlation operation is calculated in the FPGA, the consumption of FPGA multipliers and RAM resources is greatly reduced, the capacity of FPGA devices is reduced, and the cost and the equipment power consumption are reduced.

Drawings

FIG. 1 is a flow chart of an implementation of the present invention;

FIG. 2 is a delay line structure composed of registers;

FIG. 3 is a schematic block diagram of real 255 point-to-break addition;

FIG. 4 is a schematic block diagram of a 255 point-to-fold subtraction of the imaginary part;

FIG. 5 is a schematic diagram of a digital circuit architecture for performing a 128-point multiplication with 8 multipliers;

FIG. 6 shows the special symmetry of the time domain waveform of the PSS sequence.

Detailed Description

The following detailed description of embodiments of the invention, but the invention can be practiced in many different ways, as defined and covered by the claims.

The embodiment of the invention relates to the technical field of communication, in particular to a method for realizing PSS cross-correlation operation of a 5G-NR system with low resource consumption based on an FPGA.

The invention mainly comprises the following two aspects:

in a first aspect: an approximate algorithm of PSS correlation operation is provided, the unique symmetry of a time domain waveform of a PSS sequence can be fully utilized by removing a first sampling point, 1/2 multipliers are saved, and 1/2 RAM resources are saved.

The synchronization detection of the PSS is actually to perform complex correlation operation on the time domain waveform of the standard PSS reference sequence stored in the RAM of the local FPGA and the signal received by the receiver. It should be noted that the PSS is 127 frequency domain complex sampling points, and the base station performs IFFT on the complex sampling points to transform the complex sampling points to the time domain before transmission, so that the RAM in the local FPGA stores time domain PSS waveform data. Taking 30Khz subcarrier bandwidth as an example, 127 frequency domain complex sampling points of the PSS are transformed to the time domain through IFFT, the sampling rate is 7.68Mhz, 256 time domain sampling points are total, the first sampling point is removed, and the remaining 255 points have conjugate symmetry. The 30Khz sub-carrier bandwidth is used as an example, and is not a limitation to the present invention.

Representing 256-point time domain PSS waveform data stored in a RAM in a local FPGA by the following expression:

real part: PSS _ i (m) m ═ 0,1,2,3.. 255

Imaginary part: PSS _ q (m) m ═ 0,1,2,3.. 255

The signal received by the receiver is a continuous data stream, and it will perform sliding cross-correlation operation with the local PSS waveform, i.e. every period, 256 complex sampling points are taken to perform cross-correlation operation with the local PSS waveform. The signal received by the receiver is represented by the following expression:

real part: DATA _ i (m) m is 0,1,2,3.. 255

Imaginary part: DATA _ q (m) m is 0,1,2,3.. 255

The complex cross-correlation equation is expressed as follows and it can be seen that it requires 4-way 256-point multiplication.

However, after the PSS sequence is transformed to the time domain by the IFFT, the time domain waveform thereof is removed from the first sampling point, and the remaining 255 points can have conjugate symmetry, as shown in fig. 6, that is, the real part 1-127 is equal to the 255-129 point, and the imaginary part 1-127 is opposite to the 255-129 point, as shown in the following expression:

PSS_I(m)＝PSS_I(256-m)m＝1,2,3...127

PSS_Q(m)＝-PSS_Q(256-m)m＝1,2,3...127

based on this characteristic, the 255 point-to-point folding of the real part and the 255 point-to-point folding of the imaginary part of the signal of the receiver can be added and subtracted before the complex correlation operation, so that only 129 sampling points are output. The expression after folding and adding the signal of the receiver in half is as follows:

substituting into the complex correlation operation formula to obtain:

it can be seen that the original 4-way 256-point multiplication operation is changed into 4-way 129-point multiplication operation, and the multiplier consumption is reduced by half. In addition, only 129 points are needed for the PSS sequence participating in the operation, and the RAM resource of the local FPGA can be saved by half.

In a second aspect: and time division multiplexing is carried out on the multiplier by using a high-frequency clock with the sampling rate being N times, and the multiplier is reduced to 1/N of the original value again.

Defining N to be the frequency multiple of the high-frequency clock relative to the low-frequency clock, and inputting N points under the high-frequency clock into 1 multiplier in a pipeline mode, namely improving the working clock frequency of the multiplier and realizing N-time multiplexing.

Referring to fig. 1, fig. 1 shows a flow chart of an implementation of the present invention, which in a preferred embodiment comprises the following steps:

step 1: low frequency clock writing single sampling point in sequence

The sample rate of the received signal is low frequency clock 7.68Mhz and the received data stream is stored in a delay line structure of 256 register registers as shown in fig. 2. In each clock cycle, the data at register addresses 1-255 are sequentially shifted to cover the data at register addresses 0-254, and the newly entered sample points are stored at register address 255 to form a delay line structure. The received data is complex and includes real I and imaginary Q components, both having respective delay line structures.

The real part I-path shift formula is as follows, wherein Data _ in _ I represents the sampling point of the I-path new input, and Data _ Buff _ I is a delay line consisting of 256 registers of the I-path.

for(addr＝1:255)

Data_Buff_I(addr-1)＝Data_Buff_I(addr)

end

Data_Buff_I(255)＝Data_in_I

The imaginary part Q-path shift formula is as follows, wherein Data _ in _ Q represents the sampling point of Q-path new input, and Data _ Buff _ Q is a delay line formed by 256 registers of Q-path.

for(addr＝1:255)

Data_Buff_Q(addr-1)＝Data_Buff_Q(addr)

end

Data_Buff_Q(255)＝Data_in_Q

Step 2: high frequency clock reads out sampling points with 1 symbol length according to staggered sequence

The readout clock is a high frequency clock 122.88Mhz, where the key core is to read out only the last 255 samples of 1 symbol, and remove the first one. 16 points are read out from the delay line Data _ Buff _ I every clock cycle, 8 points are stored in the register set Data _ I _ invt1, and the other 8 points are stored in the register set Data _ I _ invt2, which is composed of 8 independent registers, as shown in fig. 3.

The high frequency clock can be read 16 times (corresponding to t being 0,1,2 … 15) in a 7.68Mhz low frequency clock cycle, and the key core here is that only 15 points are read at the last time, 7 points are placed in the register set Data _ I _ invt2, and 8 points are placed in the register set Data _ I _ invt 1. A total of 255 sample points with register addresses 1-255 are read out, eliminating the first sample point. The high-frequency clock is 16 times of the low-frequency clock, and 16 times of multiplexing is realized.

The key core of the Data placed in the register set Data _ I _ invt1 is to read out the Data in order of increasing addresses, and the total number of 128 sampling points are read out. The address mapping formula is as follows:

Data_I_invt1(a,t)＝Data_Buff_I(addr1)

addr1＝a*16+t+1

a＝0,1,2...7 t＝0,1,2,...15

the key core of the Data stored in the register set Data _ I _ invt2 is to read out the Data in order of decreasing addresses, wherein the total number of 127 sampling points are read out, and finally 0 is complemented to 128 sampling points. The address mapping formula is as follows:

Data_I_invt2(a,t)＝Data_Buff_I(addr2)

Data_I_invt2(7,15)＝0

addr2＝a*16+(15-t)+128

a＝0,1,2...7 t＝0,1,2...15

the same is true for the Q-way.

And step 3: real part fold-in-half addition

As shown in fig. 3, for 255 samples of the real part Data I, the first part Data _ I _ invt1 in step 2 is added to the second part Data _ I _ invt2, and 128 Data are output and stored in a register group Data _ half _ I, which is composed of 8 independent registers.

Data_half_I(a,t)＝Data_I_invt1(a,t)+Data_I_invt2(a,t)

a＝0,1,2...7 t＝0,1,2...15

And 4, step 4: imaginary part fold subtraction

As shown in fig. 4, for 255 sampling points of the imaginary Data Q, the second partial Data _ Q _ invt2 is subtracted from the first partial Data _ Q _ invt1 in

step

2, and 128 Data are output and stored in a register set Data _ half _ Q, where the register set is composed of 8 independent registers.

Data_half_Q(a,t)＝Data_Q_invt1(a,t)-Data_Q_invt2(a,t)

a＝0,1,2...7 t＝0,1,2...15

And 5: time division multiplexing to complete complex multiplication of local PSS waveform

Taking 30Khz subcarrier bandwidth as an example, half (numbered 1-128) of 256 complex points (numbered 0-255) of the local PSS waveform is extracted and stored in the RAM of the FPGA, and the real part I and the imaginary part Q are contained. The data are sequentially read out by a high frequency clock 122.88Mhz, 8 points are read out from the RAM every clock cycle, and the data are put into a register group PSS _ I which is composed of 8 independent registers. The imaginary Q path is also processed the same way.

PSS_I(a,t)＝PSS_RAM_I(addr)

PSS_Q(a,t)＝PSS_RAM_Q(addr)

addr＝a*16+t+1

a＝0,1,2...7 t＝0,1,2,...15

The complex correlation operation is formulated as follows, with a 4-way 128-point multiplication.

Taking II as an example, as shown in fig. 5, 8 multipliers are used to complete 1-way 128-point multiplication, and 16 points under 122.88Mhz high-frequency clock are input to 1 multiplier in pipeline mode, so as to realize 16-fold multiplexing. The 128 points after multiplication are summed to give one point output for the low frequency clock with a sample rate of 7.68 Mhz. And the other 3 paths of QQ, IQ and QI are calculated and output in the same way, so far, the complex correlation operation is completely finished.

Therefore, by adopting the method of the invention, the original 256-point PSS waveform needs to be stored in the RAM, only 128 points need to be stored, and half of RAM resources are saved. The complex multiplication originally requiring 256 × 4 — 1024 multipliers now requires 8 × 4 — 32 multipliers, which are the original 1/32, thereby greatly saving multiplier resources.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A PSS cross-correlation algorithm of a 5G-NR system based on an FPGA is characterized by comprising the following steps:

step 3, folding and adding the real parts;

step 4, doubling and subtracting the imaginary part;

2. The PSS cross-correlation algorithm of FPGA-based 5G-NR system as claimed in claim 1, wherein in step 1, data at register addresses 1-255 are sequentially shifted to cover data at register addresses 0-254, and newly entered sample points are stored at register addresses 255 to form a delay line structure.

3. The PSS cross-correlation algorithm of FPGA-based 5G-NR system as claimed in claim 1, wherein in step 2, 16 points are read out from the delay line Data _ Buff _ I every high frequency clock cycle, 8 points are stored in the register set Data _ I _ invt1, and another 8 points are stored in the register set Data _ I _ invt 2.

4. The FPGA-based 5G-NR system PSS cross-correlation algorithm of claim 3, wherein the first 15 high frequency clock cycles in each low frequency clock cycle read out 16 points from the delay line respectively; only 15 dots are read for the last high frequency clock cycle in each low frequency clock cycle, 7 dots being placed in the register set Data _ I _ invt2 and one 0 being complemented, 8 dots being placed in the register set Data _ I _ invt 1.

5. The PSS cross-correlation algorithm for FPGA-based 5G-NR system as claimed in claim 4, wherein in step 2, the Data put in the register set Data _ I _ invt1 is read out in order of increasing addresses, and the Data put in the register set Data _ I _ invt2 is read out in order of decreasing addresses.

6. The PSS cross-correlation algorithm of FPGA-based 5G-NR system as claimed in claim 4, wherein in step 3, the Data of the register set Data _ I _ invt1 is added to the Data of the register set Data _ I _ invt2 respectively.

7. The PSS cross-correlation algorithm of FPGA-based 5G-NR system as claimed in claim 6, wherein in step 4, the Data of the register set Data _ I _ invt2 is subtracted from the Data of the register set Data _ I _ invt1, respectively.

8. The PSS cross-correlation algorithm of the FPGA-based 5G-NR system of claim 6, wherein in the step 5, 16 points under the high frequency clock are input into 1 multiplier in a pipeline mode to realize N times of multiplexing, wherein N is the frequency multiple of the high frequency clock relative to the low frequency clock.