CN114373748A - Silicon carbide semiconductor device and device integrating diode and field effect transistor - Google Patents

Silicon carbide semiconductor device and device integrating diode and field effect transistor Download PDF

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Publication number
CN114373748A
CN114373748A CN202011103360.6A CN202011103360A CN114373748A CN 114373748 A CN114373748 A CN 114373748A CN 202011103360 A CN202011103360 A CN 202011103360A CN 114373748 A CN114373748 A CN 114373748A
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trench
silicon carbide
carbide semiconductor
semiconductor layer
region
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CN114373748B (en
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洪建中
朱国廷
李传英
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Shanghai Hanqian Technology Co ltd
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Shanghai Hanqian Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The present application relates to silicon carbide semiconductor devices and devices incorporating diodes and field effect transistors. A silicon carbide semiconductor component, especially a monolithic structure integrating a trench type Schottky diode and a trench type metal oxide semiconductor field effect transistor, comprises a semiconductor substrate, a trench type metal oxide semiconductor field effect transistor and a trench type Schottky diode, wherein the Schottky diode is provided with a trench which is vertically arranged and passes through along a first horizontal direction, a metal electrode which is filled in the trench and a plurality of doping regions which are sectionally arranged and extend along a second horizontal direction to surround the trench, the first horizontal direction is substantially orthogonal to the second horizontal direction, the metal electrode forms a Schottky junction on one side wall and one bottom wall in the trench, and current flowing out of the metal electrode is limited between the adjacent doping regions.

Description

Silicon carbide semiconductor device and device integrating diode and field effect transistor
Technical Field
The present invention relates to semiconductor devices, and more particularly to silicon carbide semiconductor devices.
Background
The semiconductor power device generally requires a high Breakdown voltage (Breakdown voltage) and has as small as possible on-resistance, low reverse leakage current, and fast Switching speed to reduce the on-loss (Conduction loss) and Switching loss (Switching loss) during operation. Silicon carbide (SiC for short) has a wide band gap (Bandgap E)g3.26eV), high critical breakdown field strength (2.2MV/cm), and high thermal conductivity (4.9W/cm-K), and is considered to be an excellent material for power switching elements. Under the same breakdown voltage condition, the thickness of a voltage-withstanding layer (Drift layer with low doping concentration) of a power component made of silicon carbide is only one tenth of that of a silicon (Si) power component, and theoretically, the on-resistance can reach one hundred times of that of silicon.
However, due to the wide energy gap of SiC, the Body diode (Body diode) of SiC MOSFET has a threshold voltage of about 3V, which causes large power loss when reverse current flows back during switching and limits the switching speed. In addition, epitaxial Basal plane dislocations (Basal plane dislocations) generated during the deposition of the drift layer may expand into Stacking faults (Stacking faults) due to Recombination of carriers when the body diode is turned on, and may cause failure of the SiC MOSFET in a severe case. Therefore, when a semiconductor manufacturer manufactures a SiC MOSFET, one more Schottky diode (Schottky diode) is designed in parallel to increase the operation speed, reduce the power loss, and avoid the reliability problem caused by the expansion of stacking defects. Similar prior art can be found in U.S. patent nos. US 9,209,293, US 9,246,016, US 10,418,476, US 2018/0358463, etc.
Disclosure of Invention
The present invention relates to a semiconductor device, and more particularly, to a silicon carbide semiconductor device.
The invention discloses a silicon carbide semiconductor component, comprising: a first silicon carbide semiconductor layer having a first conductivity type; a second silicon carbide semiconductor layer having the first conductivity type, the second silicon carbide semiconductor layer disposed on the first silicon carbide semiconductor layer; a third silicon carbide semiconductor layer of a second conductivity type disposed on an upper surface of the second silicon carbide semiconductor layer; a first semiconductor region of the first conductivity type disposed in the third silicon carbide semiconductor layer; a first trench vertically penetrating the first semiconductor region and the third silicon carbide semiconductor layer to the second silicon carbide semiconductor layer and extending in a first horizontal direction; a second trench spaced apart from the first trench, the second trench vertically penetrating through the third silicon carbide semiconductor layer into the second silicon carbide semiconductor layer and extending in the first horizontal direction; a second semiconductor region of the second conductivity type including a plurality of first portions extending in a second horizontal direction and a second portion extending in the first horizontal direction disposed in the second silicon carbide semiconductor layer under the first trench; a gate portion including a gate insulating layer disposed in the first trench and a poly gate buried in the first trench and formed on the gate insulating layer; and a metal electrode in contact with the first semiconductor region and the gate portion, buried in the second trench and electrically contacted with the second semiconductor region and the third silicon carbide semiconductor layer, a sidewall and a bottom wall of the metal electrode forming a schottky junction with the second silicon carbide semiconductor layer in the second trench; the first portion of the second semiconductor region defines a pickup region surrounding the first trench and connected to the second portion and a segment region surrounding the second trench and connected to the pickup region, such that current flowing from the metal electrode is confined between adjacent segment regions.
In one embodiment, the second semiconductor region has an implant depth from a top surface of the third silicon carbide semiconductor layer into the second silicon carbide semiconductor layer.
In one embodiment, the implant depth is between 0.8um and 3 um.
In one embodiment, the second semiconductor region is a strip implant region formed at intervals, and the strip implant regions are separated from each other by a gap.
In one embodiment, the spacing is between 0.5um and 3 um.
In one embodiment, the strip implant region has a width between 0.5um and 1.5 um.
In one embodiment, the second silicon carbide semiconductor layer includes an n-drift layer and an n-type current diffusion layer.
The invention also provides a device of the integrated interval surrounding type groove Schottky diode and the groove type metal oxide semiconductor field effect transistor, which comprises: a semiconductor substrate; a trench MOSFET formed on the semiconductor substrate; and a trench schottky diode formed on the semiconductor substrate, the trench schottky diode having a trench vertically disposed and passing through in a first horizontal direction, a metal electrode filling the trench, and a plurality of doped regions disposed in segments and extending in a second horizontal direction to surround the trench, the first horizontal direction being substantially orthogonal to the second horizontal direction, the metal electrode forming a schottky junction at a sidewall and a bottom wall in the trench, a current flowing from the metal electrode being confined between adjacent ones of the doped regions.
In one embodiment, the doped regions are spaced apart by 0.5um to 3 um.
In one embodiment, the doped region has a width between 0.5um and 1.5 um.
Drawings
Fig. 1A to 1B are schematic perspective views illustrating a three-dimensional structure according to an embodiment of the present invention.
Fig. 2 is a front view of fig. 1B.
Fig. 3 is a schematic top view of fig. 1A.
Fig. 4 is a schematic top view of another embodiment of the present invention.
Fig. 5 is a schematic perspective sectional view taken along a-a in fig. 1A.
Fig. 6A to 6C are schematic perspective sectional views taken along B-B in fig. 1A.
FIG. 7 is a schematic perspective cross-sectional view taken along line C-C of FIG. 1A.
Fig. 8A to 8H are schematic views illustrating a manufacturing process according to an embodiment of the invention.
Detailed Description
The terminology used in the description of the various embodiments herein is for the purpose of describing particular examples only and is not intended to be limiting.
As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise, or the number of referents is not intended to be limited to the particular referent. On the other hand, the terms "comprising" and "including" are intended to be inclusive, meaning that there may be additional components other than the listed components; when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present; when an element described as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present therebetween, or vice versa; additionally, the order of description of the various embodiments should not be construed to imply that operations or steps are necessarily order dependent, and alternative embodiments may perform the steps, operations, methods, etc. in a different order than described herein.
In this context, layers and/or regions are characterized as having a conductivity type, such as n-type or p-type, which refers to the majority carrier species in the layer and/or region, the n-type material including a balanced excess of electrons and the p-type material including a balanced excess of holes. Some materials may be labeled with "+" or "-" (e.g., n +, n-, p +, p-) to indicate a relatively greater (+) or lesser (-) majority carrier concentration as compared to another layer or region, and this notation does not represent a specific concentration of carriers. In the drawings, the thickness of layers and/or regions are exaggerated to make the illustration clearer.
The present invention provides a silicon carbide semiconductor device, and more particularly, to a structure of an integrated segment-surrounded trench Schottky diode and a trench MOSFET (a monolithic integrated trench MOSFET with a segmented depleted Schottky diode), please refer to fig. 1A and 1B, which are schematic diagrams of a three-dimensional structure according to an embodiment of the present invention, and for the sake of easy understanding, fig. 1A omits a portion of the device shown in fig. 1B, and fig. 1B shows a portion of the device shown in a dotted line. The silicon carbide semiconductor device includes a first silicon carbide semiconductor layer 10, a second silicon carbide semiconductor layer 20, a third silicon carbide semiconductor layer 30, a first semiconductor region 40, a second semiconductor region 50, a gate portion 60, and a metal electrode 70.
The first silicon carbide semiconductor layer 10 has a first conductivity type, in this embodiment, the first conductivity type is n-type, the first silicon carbide semiconductor layer 10 is an n + silicon carbide substrate, a buffer layer 11 is provided above the first silicon carbide semiconductor layer 10, a metal drain layer 12 is provided below the first silicon carbide semiconductor layer 10, the second silicon carbide semiconductor layer 20 is provided on the buffer layer 11, the second silicon carbide semiconductor layer 20 includes an n-drift layer 20a and an n-type current diffusion layer 20b, the third silicon carbide semiconductor layer 30 is provided on the n-type current diffusion layer 20b, the third silicon carbide semiconductor layer 30 is a p-type base region provided on an upper surface 21 of the second silicon carbide semiconductor layer 20, the first semiconductor region 40 is formed in the third silicon carbide semiconductor layer 30, the first semiconductor region 40 is an n + source region. The n-drift layer 20a has a doping concentration between 5E14 and 5E16, the n-type current diffusion layer has a doping concentration between 1E16 and 5E18, the p-type base region has a doping concentration between 1E17 and 5E19, and the n + source region has a doping concentration between 1E18 and 5E 20. In one embodiment, the buffer layer 11, the second silicon carbide semiconductor layer 20, and the third silicon carbide semiconductor layer 30 are epitaxially grown to form an epitaxial layer.
The silicon carbide semiconductor device includes a plurality of trenches T formed by an etching process, the trenches T including a first trench T1 and a second trench T2, the first trench T1 and the second trench T2 being spaced apart and extending along a first horizontal direction, which is the Y-axis in the figure in this embodiment, and the first trench T1 vertically penetrates the first semiconductor region 40 and the third silicon carbide semiconductor layer 30 to the second silicon carbide semiconductor layer 20, and the second trench T1 vertically penetrates the third silicon carbide semiconductor layer 30 to the second silicon carbide semiconductor layer 20. The depth and width of the first trench T1 and the second trench T2 may be the same or different according to the choice of application or manufacturing method, for example, the first trench T1 has a depth between 1um and 2.5um and a width between 0.5um and 1.5um, and the second trench T2 has a depth between 1um and 2.5um and a width between 0.5um and 2 um. In addition, in the present embodiment, the first semiconductor region 40 is formed on a portion of the upper surface of the third silicon carbide semiconductor layer 30 by Ion implantation (Ion implantation), as shown in fig. 1A and 1B.
Further referring to fig. 2 and fig. 3, a front view of fig. 1B and a top view of fig. 1A are respectively shown; and FIGS. 5, 6A, and 7, which are schematic perspective cross-sectional views taken along line A-A, B-B, C-C in FIG. 1A, respectively. The second semiconductor region 50 includes a first portion 51 and a second portion 52, the first portion 51 is a spaced apart strip implant region (segmentally implanted) formed in the third silicon carbide semiconductor layer 30 and the second silicon carbide semiconductor layer 20, the first portion 51 extends along a second horizontal direction, which is the X-axis in the figure in the present embodiment. Further, the first portion 51 of each of the second semiconductor regions 50 defines a plurality of pickup regions (pick-up regions)51a and a plurality of segment regions (slice regions)51b, respectively. Wherein the first portion 51 surrounding the first trench T1 is the pickup region 51A, the first portion 51 surrounding the second trench T2 is the fragment region 51b, and the second semiconductor region 50 has an implant depth (in some aspects, the upper surface 31 may correspond to the top surface of the first semiconductor region 40) from an upper surface 31 (see fig. 1A) of the third silicon carbide semiconductor layer 30 into the second silicon carbide semiconductor layer 20, the implant depth being between 0.8um and 3.0 um.
In the embodiment of fig. 1A to 3, a width 511A and a depth 512a of the pickup region 51A are the same as a width 511b and a depth 512b of the segment region 51b, in one embodiment, the width 511A and the width 511b are between 0.5um and 1.5um, and the depth 512a and the depth 512b are between 0.8um and 2.5 um; however, in other embodiments, the width 511a of the pickup region 51a may be different from the width 511b of the segment region 51b, such as in fig. 4, and the width 511b is greater than the width 511a, thereby further limiting leakage. However, depending on the application, the width 511a may be smaller than the width 511b, and the depth 512a of the pickup region 51a may be larger or smaller than the depth 512b, and the doping concentration of the pickup region 51a may be equal to, larger or smaller than that of the segment region 51b, and the doping concentration may be between 1E18 and 5E 20. In addition, the picking regions 51a have a spacing D1 therebetween, the spacing D1 is between 0.5um and 3um, and the fragment regions 51b have a spacing D2 therebetween, the spacing D2 is between 0.5um and 3 um.
The second portion 52 is formed in the region of the second sic semiconductor layer 20 under the first trench T1 and extends along the first horizontal direction, the second portion 52 has a depth 521 from the upper surface 31 to a lowest position, the depth 521 is between 1.3 and 3um, the second portion 52 serves as a p + shield region (p + shield), the second portion 52 has a doping concentration between 1E18 and 5E20, it is understood that the depth 521 of the second portion 52 is greater than the depth 512a of the pickup region 51a and/or the depth 512b of the segment region 51 b. Referring to fig. 1B and fig. 2, a metal silicide layer (metal silicide)80 is formed on the surfaces of the third silicon carbide semiconductor layer 30 and the first semiconductor region 40, and a metal layer 81 is formed on the metal silicide layer 80 and the inner wall surface of the second trench T2, in the present embodiment, the metal silicide layer 80 is nickel silicide (NiSi), the metal layer 81 is an alloy, such as Ti/TiN, and the metal electrode 70 is AuCu. The gate portion 60 includes a gate insulating layer 61 and a Poly gate 62(Poly gate), the gate insulating layer 61 is formed on a portion of the surface of the first semiconductor region 40 and extends longitudinally along the sidewall of the first trench T1 to cover the third silicon carbide semiconductor layer 30 and a portion of the surface of the second silicon carbide semiconductor layer 20, the Poly gate 62 is formed on the gate insulating layer 61, the metal electrode 70 is covered on the upper surface of the gate insulating layer 61 and the metal layer 81 and fills the second trench T2, a sidewall and a bottom wall of the metal layer 81 form a Schottky junction (Schottky junction) with the second silicon carbide semiconductor layer 20 in the second trench T2, and the metal electrode 70 is covered on the metal layer 81.
Referring to fig. 6B and 6C, in the present invention, the inner wall surface of the second trench T2 defined below the upper surface 21 of the second silicon carbide semiconductor layer 20 has a first area a1 (including part of the surface of the segment region 51B), and the schottky junction has a second area a2 (not including part of the surface of the segment region 51B), and the second area a2 is smaller than the first area a 1. Referring back to fig. 3, it can be seen that a first region R1 of the sic Semiconductor device corresponds to a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), and a second region R2 corresponds to a Junction Barrier Schottky diode (JBS). The position where the first semiconductor region 40 is formed in the third silicon carbide semiconductor layer 30 is determined according to the arrangement of the MOSFET.
In the prior art, the leakage of JBS occurs in the first area a1, however, the integrated segment proposed by the present invention encompasses both the trenched Schottky diode and the trenched MOSFET with segmented shorted Schottky diode, the leakage of JBS will be limited to occur only in the second area a 2. Therefore, under the same size condition, the leakage of the component of the invention can be improved, and the reverse diode conducting voltage (Vsd) can be lower; on the other hand, the silicon carbide semiconductor device of the present invention can increase the cell density, i.e., reduce the cell pitch.
Referring to fig. 8A, a semiconductor substrate 90 is provided, a drift layer 90a, a current spreading layer 90b and a base layer 90c are formed in the semiconductor substrate 90, the drift layer 90a and the current spreading layer 90b have a first conductivity type, the base layer 90c has a second conductivity type, in this embodiment, the first conductivity type and the second conductivity type are n-type and p-type, respectively, and the drift layer 90a, the current spreading layer 90b and the base layer 90c are obtained by growth epitaxy. Referring to fig. 8B, a plurality of segment-wise first doped regions 91 extending along a second horizontal direction are implanted on the semiconductor substrate 90, the first doped regions 91 have a depth 911 at least penetrating through the base layer 90c, and the first doped regions 91 are separated from each other by a distance 912, wherein the depth 911 and the distance 912 are as defined in the foregoing embodiments. The first doped region 91 may be predefined to include a plurality of pickup regions 91a and a plurality of segment regions 91b, the pickup regions 91a corresponding to the regions of the MOSFETs, and the segment regions 91b corresponding to the regions of the JBS. Referring to fig. 8C, a source region 90d is formed in a portion of the upper surface area of the base layer 90C, i.e., the area corresponding to the MOSFET, the source region 90d having the first conductivity type.
Referring to fig. 8D, a first trench T1 is etched into the semiconductor substrate 90, the first trench T1 is spaced apart along the second horizontal direction and penetrates along a first horizontal direction substantially perpendicular to the second horizontal direction, and the first trench T1 penetrates vertically to the current spreading layer 90 b. Referring next to fig. 8E, the current spreading layer 90b under the first trench T1 is implanted with a second doped region 92, the second doped region 92 and the first doped region 91 having the same conductivity type. Then, a gate portion is formed in the first trench T1, referring to fig. 8F, a first gate insulating layer 61a is formed on the bottom wall and the sidewall of the first trench T1 and the upper surface of the source region 90d adjacent to the first trench T1, and then a poly gate 62 is formed in the first trench T1 on the first gate insulating layer 61a, referring to fig. 8G. Referring to fig. 8H, a second trench T2 is formed in the semiconductor substrate 90, the second trench T2 and the first trench T1 are spaced apart along the second horizontal direction and penetrate along the first horizontal direction, and the second trench T2 penetrates vertically to the current spreading layer 90 b. Thereafter, the metal silicide layer 80, the metal layer 81, and the metal electrode 70 are formed, as described with reference to fig. 1A and 1B.
According to the above manufacturing method, the first doped region 91 is the first portion 51 of the second semiconductor region 50 and the second doped region 92 is the second portion 52 of the second semiconductor region 50. In the present embodiment, the first doped regions 91 of the mosfet and the junction barrier schottky diode can be ion implanted through the same mask, thereby improving the precision of the process and device configuration.

Claims (10)

1. A silicon carbide semiconductor component, comprising:
a first silicon carbide semiconductor layer having a first conductivity type;
a second silicon carbide semiconductor layer having the first conductivity type, the second silicon carbide semiconductor layer disposed on the first silicon carbide semiconductor layer;
a third silicon carbide semiconductor layer of a second conductivity type disposed on an upper surface of the second silicon carbide semiconductor layer;
a first semiconductor region of the first conductivity type disposed in the third silicon carbide semiconductor layer;
a first trench vertically penetrating the first semiconductor region and the third silicon carbide semiconductor layer to the second silicon carbide semiconductor layer and extending in a first horizontal direction;
a second trench spaced apart from the first trench, the second trench vertically penetrating through the third silicon carbide semiconductor layer into the second silicon carbide semiconductor layer and extending in the first horizontal direction;
a second semiconductor region of the second conductivity type including a plurality of first portions extending in a second horizontal direction and a second portion extending in the first horizontal direction disposed in the second silicon carbide semiconductor layer under the first trench;
a gate portion including a gate insulating layer disposed in the first trench and a poly gate buried in the first trench and formed on the gate insulating layer; and
a metal electrode in contact with the first semiconductor region and the gate portion, buried in the second trench and electrically contacted with the second semiconductor region and the third silicon carbide semiconductor layer, a sidewall and a bottom wall of the metal electrode forming a schottky junction with the second silicon carbide semiconductor layer in the second trench;
the first portion of the second semiconductor region defines a pickup region surrounding the first trench and connected to the second portion and a segment region surrounding the second trench and connected to the pickup region, such that current flowing from the metal electrode is confined between adjacent segment regions.
2. The silicon carbide semiconductor device of claim 1, wherein the second semiconductor region has an implant depth from a top surface of the third silicon carbide semiconductor layer into the second silicon carbide semiconductor layer.
3. The SiC semiconductor device of claim 2, wherein the implant depth is between 0.8um and 3 um.
4. The SiC semiconductor device of claim 1, wherein the second semiconductor region is a strip implant region formed at intervals, the strip implant regions being spaced apart from one another by a spacing.
5. The SiC semiconductor device of claim 4, wherein the spacing is between 0.5um and 3 um.
6. The SiC semiconductor device of claim 5, wherein the strip implant region has a width between 0.5um and 1.5 um.
7. The silicon carbide semiconductor device of claim 1, wherein the second silicon carbide semiconductor layer comprises an n-drift layer and an n-type current spreading layer.
8. An integrated slot-wrap-around trench schottky diode and trench mosfet device, comprising:
a semiconductor substrate;
a trench MOSFET formed on the semiconductor substrate; and
a trench schottky diode formed on the semiconductor substrate, the trench schottky diode having a trench vertically disposed and passing through along a first horizontal direction, a metal electrode filling the trench, and a plurality of doped regions disposed in intervals and extending along a second horizontal direction to surround the trench, the first horizontal direction being substantially orthogonal to the second horizontal direction, the metal electrode forming a schottky junction at a sidewall and a bottom wall in the trench, a current flowing from the metal electrode being confined between adjacent doped regions.
9. The device of claim 8, wherein the doped regions are spaced apart by between 0.5um and 3 um.
10. The device of claim 8, wherein said doped region has a width between 0.5um and 1.5 um.
CN202011103360.6A 2020-10-15 2020-10-15 Silicon carbide semiconductor component and component integrating diode and field effect transistor Active CN114373748B (en)

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