CN114363137A

CN114363137A - Synchronous frame structure suitable for high-speed motion scene and synchronous method thereof

Info

Publication number: CN114363137A
Application number: CN202210033081.XA
Authority: CN
Inventors: 刘畅; 刘皓; 袁声; 王秋实; 张培
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2022-01-12
Filing date: 2022-01-12
Publication date: 2022-04-15
Anticipated expiration: 2042-01-12
Also published as: CN114363137B

Abstract

The invention belongs to the technical field of communication, and relates to a synchronous frame structure suitable for a high-speed motion scene and a synchronous method thereof. The invention provides a synchronous frame structure design, wherein a synchronous frame comprises a first synchronous head, a second synchronous head and a third synchronous head which are sequentially spliced, the first synchronous head, the second synchronous head and the third synchronous head are subjected to DDC _ num times of interpolation, DDC _ num is a positive integer, the first synchronous head is formed by copying and sequentially splicing a first PN sequence with the length of L into Sync1_ num, a second PN sequence with the length of L is used as the second synchronous head, and the third synchronous head is formed by copying and sequentially splicing a third PN sequence with the length of L into Sync3_ num. According to the embodiment, the frequency offset and the time delay within 10.48576ms of [ -400kHz and 400kHz ] can be resisted, the capture probability of more than 99% can be achieved under the signal-to-noise ratio of-25 dB, the method has concealment, is suitable for TDMA Time Division Multiple Access (TDMA) frames, can flexibly allocate time slots to carry out burst communication, and can realize wider frequency offset resistance and time delay resistance through simple and flexible extension.

Description

Synchronous frame structure suitable for high-speed motion scene and synchronous method thereof

Technical Field

The invention belongs to the technical field of communication, and relates to a synchronous frame structure suitable for a high-speed motion scene and a synchronous method thereof.

Background

With the continuous emergence of communication scenes between high-speed moving objects such as a high-speed aircraft and the continuous improvement of the movement speed, the doppler frequency offset existing between a communication transmitter and a receiver is larger and larger, which seriously affects the communication performance, and a solution is urgently needed. The existing frame structure and detection algorithm have the defects of high complexity, easy interception, poor adaptability and poor time delay resistance in a low signal-to-noise ratio environment, and are difficult to adapt to burst communication.

The difficulty in solving the above problems is: under the condition of low signal-to-noise ratio, the accuracy of frequency offset estimation and timing is improved as much as possible in limited transmission signals, the operation complexity is reduced as much as possible, the concealment is improved as much as possible, the method is suitable for TDMA time division multiple access frames, time slots can be flexibly allocated for burst communication, and wider frequency offset resistance and time delay resistance can be realized through simple and flexible expansion.

The significance of solving the problems is that: the synchronous frame structure design and synchronous detection problems of low signal-to-noise ratio large frequency offset burst communication in a high-speed mobile scene are solved, the synchronous performance of a receiving end is improved while the hidden communication is achieved, the communication quality is improved, the expandability is achieved, and a foundation is laid for low signal-to-noise ratio communication and burst communication in a future higher motion scene.

Disclosure of Invention

Aiming at the problems, a synchronous frame structure design and a synchronous detection scheme suitable for low signal-to-noise ratio large frequency offset burst communication in a high-speed mobile scene are provided.

The technical scheme of the invention is as follows: a synchronization frame structure is proposed, and a corresponding synchronization method is presented.

A synchronous frame suitable for a high-speed motion scene comprises a first synchronous head, a second synchronous head and a third synchronous head which are sequentially spliced, wherein the first synchronous head, the second synchronous head and the third synchronous head are subjected to DDC _ num times of interpolation, and DDC _ num is a positive integer;

the first synchronization head is generated in a mode that a first PN sequence with the length of L is copied into Sync1_ num parts and spliced in sequence to obtain a first synchronization head;

the second synchronization head is generated by adopting a second PN sequence with the length of L as the second synchronization head;

the third synchronization head is generated in a mode that a third PN sequence with the length of L is copied into Sync 3-num parts and spliced in sequence to obtain a third synchronization head;

the first PN sequence, the second PN sequence and the third PN sequence are m sequences, and the synchronization frame has the following characteristics:

the frequency deviation resistance performance is [ -Fd _ num × 1.024 × Fs/(DDC _ num × X), Fd _ num × 1.024 × Fs/(DDC _ num × X) ], wherein Fs is sampling frequency, X is the number of sections of the receiving end section matching filter, X > < 1, X is a positive integer, Fd _ num is calculated according to a formula and the actually required frequency deviation resistance performance, and Fd _ num is a positive integer;

sync1_ num is related to Fd _ num, and Sync1_ num > is 3 × Fd _ num + 1;

sync3_ num is related to fine timing and fine frequency offset error, and satisfies Sync3_ num > being 1, Sync3_ num being at least 1 for fine timing and fine frequency offset, when Sync3_ num > being 2, the first PN sequence with length L in the third synchronization head is used as fine timing, and Sync3_ num PN sequences with length L are used as incoherent accumulation precision frequency offset, thereby reducing the fine frequency offset error under low signal-to-noise ratio;

the coarse frequency offset precision d _ f1 is (Fs/DDC _ num)/(X × N), wherein the receiving end matches each segment of the filter in a segmented manner, the length of each segment is X, P segments are obtained, L is P × X, P correlation values are obtained after segment correlation, and N-point FFT is performed on the P correlation values, wherein N > is P;

fine frequency offset precision d _ f2 ═ Fs/DDC _ num)/(X × N × M), where N × M denotes making N × M point FFT after zero padding for P correlation values, M > -1, M is a positive integer;

the delay resistance is 0 to (T _ num-1) L DDC _ num 4 2/Fs, and T _ num is the total search number.

A synchronization method of synchronous frames suitable for high-speed motion scenes comprises the following steps:

s1, acquiring a pseudo code phase synchronization position phase _ temp, a coarse timing position StartIdx _1 and a coarse frequency offset fd _1 by utilizing a PMF-FFT algorithm according to the first synchronization header;

s2, obtaining a coarse timing position StartIdx _2 according to the second synchronization header, the pseudo code phase synchronization position phase _ temp and the coarse frequency offset fd _ 1;

s3, obtaining a fine timing position StartIdx _3 according to the third synchronization header, the pseudo code phase synchronization position phase _ temp, the coarse frequency offset fd _1 and the coarse timing position StartIdx _2, wherein the position is also the optimal sampling point position of DDC _ num times interpolation, and subsequent data can be obtained through sequential down-sampling;

s4, performing incoherent accumulation after down-sampling by using the third synchronization header, the pseudo code phase synchronization position phase _ temp, the coarse frequency offset fd _1 and the fine timing position StartIdx _3 to obtain a fine frequency offset fd _ 2;

s5, obtaining the timing position StartIdx _4 and the frequency offset f _ last of the data frame, and completing synchronization of one frame of data, where StartIdx4 is StartIdx3+ L DDC _ num syncs 3_ num, and f _ last is fd _1+ fd _ 2.

Further, the specific method of step S1 is as follows:

at a receiving end, carrying out coarse timing and coarse frequency offset estimation, finding a first synchronization head within a certain delay range, and estimating coarse frequency offset fd _ 1; the method specifically comprises the following steps:

s11, first, the points of the received signal rx [ (pp-1) × L DDCnum × Fd _ num + 2] - [ (pp-1) × L DDCnum × Fd _ num _1] and the points of the received signal rx [ (pp-1) × L DDCnum × Fd _ num +1] are searched for DDCnum _ num, and the points are sampled continuously from the points of the received signal rx [ (pp-1) [ (pp-L) × L DDCnum × Fd _ num +1] - [ (pp-1) [ (pp-L DDCnum _ Fd _ num + L DDCnum _ num ] and are sampled as a total number of sampling points DDCnum _ DDCnum × 2+ L DDCnum _ DDCnum [ < ddcnu > DDCnum _ DDCnum > - ((1) < ddcng _ ddcnu > ddcnu _ num > ddcnu _ w _ m, < 2;

s12, presetting frequency offsets for Fd _ num × 2 small windows, where the preset frequency offset for each window is denoted as f (qq), 1< ═ qq < (Fd _ num × 2), and when qq is between 1 and Fd _ num, f (qq) (1-Fd _ num + (qq-1) > 2) > 1.024 Fs/(DDC _ num × X); when qq is between Fd _ num +1 and Fd _ num × 2, f (qq) ((qq-Fd _ num-1) × 2) × 1.024 × Fs/(DDC _ num ×);

s13, respectively performing partial matched filtering and FFT on the L point data of each small window win8(qq) and a first synchronous head, recording an amplitude peak value of an FFT result and a peak value position in N-point FFT, wherein each segment of the partial matched filter is X long, P segments are counted, P X is L, P partial correlation values are obtained, N-point FFT is performed on the P partial correlation values, and the value of N is automatically adjusted according to the consideration of complexity and frequency offset estimation precision in practical application;

s14, circularly moving the L point data in each small window by 1 point to the right, namely changing the L-1, L into L,1,2, L-1 according to the original data index;

s15, repeating S13 and S14 until L times of execution, obtaining L PMF-FFT peak values and positions of the peak values in each small window, solving the maximum value Amax _4096 of the L peak values, recording the index position idx _ phase _4096 of the L peak values, and recording the index position idx _ FFT _4096 of the peak values in the N-point FFT;

s16, as stated in S15, obtaining peak value Amax _8win (qq), pseudo code phase idx _ phase _8win (qq), FFT peak index position idx _ FFT _8win (qq)) of Fd _ num 2 small windows, 1 ═ qq ═ 8, finding maximum value Amax and Amax of the respective peak values of Fd _ num 2 small windows at position ss in Fd _ num 2 windows, Amax8 ═ Amax _8win (ss8), 1< 8 ═ Fd _ num 2, recording pseudo code phase idx _ phase8 ═ idx _8win ═ ss), peak value index position in FFT, idx _ FFT _8 ═ FFT _8win (8);

s17, if pp < T _ num, repeating S11-S16, and making pp be pp + 1; if pp ═ T _ num, T _ num Amax8, ss8, idx _ phase8, and idx _ fft8 to Amax8_ sum (pp), idx _ ss8_ sum (pp), idx _ phase8_ sum (pp), idx _ fft8_ sum (pp) are recorded;

s18, obtaining the maximum value from Amax8_ sum (1) to Amax8_ sum (T _ num), and obtaining the maximum value a _ temp and the corresponding index pp5, i.e. a _ temp ═ Amax8_ sum (pp5), 1 ≦ pp5 ≦ T _ num;

s19, based on pp5, obtaining a pseudo code synchronization position phase _ temp ═ idx _ phase8_ sum (pp5), where the position is the pseudo code synchronization position of the PN code with length L, and 1 ═ phase _ temp ═ L;

s110, based on pp5, obtaining a peak position FFT _ temp ═ idx _ FFT8_ sum (pp5) in the FFT (1 ═ FFT _ temp ═ N), which is a position where the peak value in the N-point FFT is located;

s111, obtaining a coarse timing position StartIdx _1_ temp ═ L _ DDC _ num + 2+ (ss8-1) × L _ DDC _ num + (phase _ temp-1) < DDC _ num + (phase _ temp _ num +1+ ss8_ 4), wherein when ss8_4 takes a value of 0 or 1, ss8_4 takes a value of 0 when ss8 takes a value of 1 to Fd _ num, ss8_4 takes a value of 1 when ss8 takes a value of Fd _ num +1 to Fd _ num 2, the coarse timing position StartIdx _1 is always located in the first synchronization header in the transmission frame, and after the receiving end has been subjected to DDC _ num times down sampling, the second synchronization header may appear at the earliest at the first synchronization header DDC _1_ temp _1+ L _ temp _ num + 829 _ DDC _ ctpm + DDC _ ctx _ DDC _ num +1, and DDC _ num + DDC _ wt _ DDC _ num + DDC _ position may be searched from the coarse timing position (pp _ ctx _ DDC _ ctx _ 1) ((pp _ ctpm) ((pp _ ctx _ DDC _ ctx _ ctpm) (+ DDC _ ctx _ 4) ((DDC _ ctx _ DDC _ ctx _ DDC _ ctx _ DDC _ num + DDC _ 4) + DDC _ ctx _ DDC _ 4) + DDC _ num + DDC _ ctx _ pind _ num + DDC _ num + DDC _ 2) after the coarse timing _ DDC _ 2) position) num +1+ ss8_ 4;

s112, if the frequency interval is d _ f, the frequency offset in the small window is fft _ temp2 × d _ f, where d _ f is (Fs/DDC _ num)/(X × N), and when fft _ temp is in the range of 1-N/2, fft _ temp2 is fft _ temp; when fft _ temp is in the range of N/2+1 to N, fft _ temp2 is equal to fft _ temp-N; fs is a sampling frequency, DDC _ num is a sampling decimation multiple, X is a number of segments of the partial matched filter, and N is a number of FFT points, thereby obtaining a coarse frequency offset fd — 1 ═ FFT _ temp2 × d _ f + f (ss8), that is, frequency offset in the window + preset frequency offset of the window itself.

Further, the specific method in step S2 is as follows:

searching the position of a second synchronization head according to the obtained StartIdx _1 and the coarse frequency offset estimation fd _ 1; the method specifically comprises the following steps:

s21, performing frequency offset compensation on the [ StartIdx _1] - [ StartIdx _1+ L DDC _ num _ Sync1_ num ] of the received rx signal by using the coarse frequency offset fd _1 obtained in step S1 to obtain rx 2;

s22, performing DDC _ num multiple down-sampling on [1] - [ L × DDC _ num × Sync1_ num ] points of rx2, accumulating DDC _ num samples that are consecutive in one chip as one point, obtaining L × Sync1_ num points, and obtaining Sync1_ num small windows win14_0(tt) with L points as one small window (1 ═ Sync1_ num);

s23, performing DDC _ num times downsampling on [2] - [ L × DDC _ num × Sync1_ num +1] points of rx2 to obtain L × Sync1_ num points, and taking the L points as a small window to obtain a Sync1_ num small window win14_1(uu), where 1< (uu) < ═ Sync1_ num;

s24, after passing through step S1, the Sync header at this time is pseudo code synchronized, and PMF-FFT operation in step S1 is performed once for Sync1_ num × 2 small windows of win14_0 and win14_1, to obtain Sync1_ num 2 FFT peaks fftM (vv) and corresponding peak positions fftM _ l (vv), 1 ═ vv ═ Sync1_ num 2, where 1 ═ vv ═ Sync1_ num represents data of Sync1_ num windows of win14_0, and Sync1_ num +1 ═ vv ═ Sync1_ num 2 represents data of Sync1_ num windows of win14_ 1;

s25, finding maximum value fftM _ max of Sync1_ num × 2 FFT peak values fftM (vv), and recording that the maximum value appears in vv28 windows, that is, fftM _ max ═ fftM (vv28) (1< ═ vv28< ═ Sync1_ num × 2), and recording corresponding peak value position fftM _ L _ max ═ fftM _ L (vv 28);

s26, the start chip of the second Sync header appears at StartIdx2 ═ StartIdx1+ (vv14-1) × L × DDC _ num + vv28_1, where vv14 ═ vv28, vv28_1 ═ 0 when vv28 takes a value from 1 to Sync1_ num, and vv14 ═ vv28-Sync1_ num, and vv28_1 ═ 1 when vv28 takes a value from Sync1_ num +1 to Sync1_ num.

Further, the specific method in step S3 is as follows:

s31, the position where the third sync header appears is StartIdx3_ temp ═ StartIdx2+ L ═ DDC _ num;

s32, considering that there may be an error of 1 chip when pseudo code synchronization is performed in step S1, the search is extended from the position forward and backward by one chip, and the earliest possible position of the third synchronization header is obtained as StartIdx3_ temp2 ═ StartIdx3_ temp-DDC _ num;

s33, taking the [ StartIdx3_ temp ] to the [ StartIdx3_ temp + L _ DDC _ num + 3_ DDC _ num-1] point of the received rx signal, and performing frequency offset compensation by using the coarse frequency offset fd _1 obtained in the step S1 to obtain rx 3;

s34, taking the [ ww ] to [ L × DDC _ num + ww-1] points (1 ═ ww ═ DDC _ num × 3) of rx3, and performing DDC _ num times downsampling to obtain DDC _ num × 3 group data win12(ww), each group of L points;

s35, because the pseudo code synchronization has been determined in steps S1 and S2, and the first sync header, the second sync header, and the third sync header all use PN sequences with the same length L, the sync header at this time is already pseudo code synchronization, and PMF-FFT operation in step S1 is performed once for each DDC _ num × 3 group of data of win12, to obtain DDC _ num × 3 FFT peaks fftM3(ww) and corresponding peak positions fftM _ L3(ww), 1 ═ ww ═ DDC _ num × 3;

s36, finding the maximum value fftM3_ max of DDC _ num × 3 FFT peak values fftM3(vv), and recording the maximum value appearing in the ww12 group, that is, fftM3_ max ═ fftM3(ww12) (1< ═ ww12< ═ DDC _ num × 3), and recording the corresponding peak position fftM3_ L _ max ═ fftM3_ L (ww 12);

s37, and the optimal sampling point position StartIdx3 ═ StartIdx3_ temp2+ ww12-1, 1 ═ ww12 ═ DDC _ num in the start chip where the third sync header appears.

Further, the specific method in step S4 is as follows:

fine frequency offset estimation is performed by using the third synchronization header, and the optimal sampling point position in the start chip of the third synchronization header is already found through step S3;

s41, taking the [ StartIdx3] to [ StartIdx3+ L DDC _ num Sync3_ num-1] points of the received rx signal, and performing frequency offset compensation by using the coarse frequency offset fd _1 obtained in the step S1 to obtain rx 4;

s42, performing DDC _ num times downsampling on rx4 to obtain L × Sync3_ num point data, dividing the L points into Sync3_ num groups according to the index order, wherein each group of L points is denoted as win16(xx), and 1< ═ xx < (Sync 3_ num);

s43, after multiplying the value of N by M, PMF-FFT computation in step S1 is performed on each of the Sync3_ num sets of data of win16, that is, N points FFT are changed into N points FFT, so as to obtain a Sync3_ num set FFT computation result FFT4(xx), where 1< ═ xx < ═ Sync3_ num and each set result is N points;

s44, obtaining Sync3_ num FFT computation results FFT4(xx), performing incoherent accumulation to obtain results FFT4_ sum (xx) at point N × M, obtaining maximum value FFT4_ sum _ max, and recording that the maximum value appears at the yy point, where 1 ═ yy ═ N × M;

s45, if the frequency interval is d _ f2, the frequency offset in the small window is yy × d _ f2, where d _ f2 is (Fs/DDC _ num)/(X × N × M), Fs is the sampling frequency, DDC _ num is the downsampling decimation multiple, X is the number of segments of the partial matched filter, N is the number of FFT points at the time of coarse frequency offset, and N × M is the number of FFT points at the time of fine frequency offset, so as to obtain the fine frequency offset of fd _2 — yy × d _ f2, where M points may be selected according to the actual accuracy requirement of fine frequency offset.

Further, the specific method in step S5 is as follows:

s51, the data start position StartIdx4 ═ StartIdx3+ L ═ DDC _ num ═ Sync3_ num, and this position is also the optimal sampling point position from which the down-sampling of data can be performed;

s52, frequency offset f _ last ═ fd _1+ fd _ 2.

So far, the whole sync frame completes pseudo code synchronization, timing synchronization and frequency offset estimation, and can resist the time delay of 0 to (T _ num-1) × DDC _ num × 4 × 2/Fs and the frequency offset of [ -Fd _ num × 1.024 × Fs/(DDC _ num × X), Fd _ num × 1.024 [ -Fs/(DDC _ num × X) ], coarse frequency offset accuracy d _ f1 ═ Fs/DDC _ num)/(X N), and fine frequency offset accuracy d _ f2 ═ Fs/DDC _ num)/(X × M), so that the time delay resistance and frequency offset resistance of a wider range can be realized by flexibly expanding the lengths of the sync header 1, the sync header 2 and the sync header 3 in the frame and the search length of the receiving end.

The invention has the advantages that the synchronization problem of large frequency deviation and low signal-to-noise ratio communication is solved under the single carrier system, the frequency deviation of hundreds of kHz and even more can be resisted, the anti-frequency deviation performance can be continuously expanded through the flexible expansion frame structure, the capture probability of 99 percent is reached under-25 dB, and the invention can be suitable for burst communication.

Drawings

FIG. 1 is a diagram of a synchronous frame and transmission frame structure according to an embodiment of the present invention

FIG. 2 is a flowchart of step three in the synchronization algorithm flow provided by the embodiment of the present invention

FIG. 3 is a schematic diagram of step three in the synchronization algorithm flow provided by the embodiment of the present invention

FIG. 4 is a flowchart of step four in the synchronization algorithm flow provided by the embodiment of the present invention

FIG. 5 is a schematic diagram of step four in the synchronization algorithm flow provided in the embodiment of the present invention

Fig. 6 is a flowchart of step five in the synchronization algorithm flow provided in the embodiment of the present invention

FIG. 7 is a schematic diagram of step five in the synchronization algorithm flow provided by the embodiment of the present invention

FIG. 8 is a flowchart of step six in the synchronization algorithm flow provided by the embodiment of the present invention

FIG. 9 is a schematic diagram of step six in the synchronization algorithm flow provided in the embodiment of the present invention

FIG. 10 is a diagram illustrating a seventh step in the synchronization algorithm flow according to an embodiment of the present invention

FIG. 11 is a diagram of the performance of capturing synchronization frames under different SNR according to an embodiment of the present invention

FIG. 12 is a diagram of coarse frequency offset error of a synchronization frame at a signal-to-noise ratio of-24 dB, according to an embodiment of the present invention

FIG. 13 is a diagram of fine frequency offset error of a synchronization frame under a-24 dB signal-to-noise ratio according to an embodiment of the present invention

FIG. 14 is a diagram of a coarse frequency offset error of a synchronization frame at a signal-to-noise ratio of-15 dB according to an embodiment of the present invention

FIG. 15 is a diagram of a fine frequency offset error of a synchronization frame under a-15 dB signal-to-noise ratio according to an embodiment of the present invention

FIG. 16 is a diagram of a coarse frequency offset error of a synchronization frame at a signal-to-noise ratio of 0dB according to an embodiment of the present invention

FIG. 17 is a fine frequency offset error diagram of a synchronization frame under a signal-to-noise ratio of 0dB according to an embodiment of the present invention

FIG. 18 is a diagram of a coarse frequency offset error of a synchronization frame at a signal-to-noise ratio of 20dB according to an embodiment of the present invention

FIG. 19 is a fine frequency offset error diagram of a synchronization frame under a signal-to-noise ratio of 20dB according to an embodiment of the present invention

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to one embodiment. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. The technical scheme of the invention is described in detail in the following with reference to the accompanying drawings and embodiments:

the specific implementation process of the embodiment is as follows:

the method comprises the following steps: generating PN sequence 1, PN sequence 2 and PN sequence 3 with L being 4096 length, wherein the three sequences are m sequences with 4096 length, which are respectively recorded as m4096_1, m4096_2 and m4096_3, and generating polynomials are respectively:

m4096_1 generating a polynomial: [ 001100001111 ];

m4096_2 generating a polynomial: [ 010101001101 ];

m4096_3 generating a polynomial: [ 000001010011 ];

step two: as shown in fig. 1, 14 copies of m4096_1 are copied and sequentially spliced, then 1 copy of m4096_2 is spliced, then 16 copies of m4096_3 are spliced, and 4 times of interpolation is performed on the data to form a synchronous frame of a sending end;

wherein:

(1) taking Fd _ num as 4, Fs as 50MHz, DDC _ num as 4, X as 32, and the frequency deviation resistance is [ -400kHz,400kHz) ];

(2) sync1_ num > 3 × Fd _ num +1, and Sync1_ num > 14;

(3) sync3_ num is 16, the first PN sequence with length 4096 in the Sync header 3 is used for fine timing, after the fine timing is finished, 16 PN sequences with length 4096 are used for incoherent accumulation refined frequency offset, and the error of the refined frequency offset under low signal-to-noise ratio is reduced;

(4) coarse frequency offset precision d _ f1 ═ Fs/DDC _ num)/(X × N ═ 1524Hz, where X ═ 32 length per segment of the receiving-end segmented matched filter, P ═ 128 segment altogether, L ═ 4096 ═ P ═ X128 ═ 32, P ═ 128 correlation values are obtained after segment correlation, and N ═ 256 FFT is performed on P ═ 128 correlation values;

(5) fine frequency offset accuracy d _ f2 ═ Fs/DDC _ num)/(X × N × M) ═ 95Hz, where M is 16, and N × M indicates that N × M ═ 4096-point FFT is performed after zero padding is performed on P correlation values in step two (4);

(6) the time delay resistance is 0 to (T _ num-1) L DDC _ num 4 2/Fs, namely 0 to 10.48576 ms;

step three: searching a synchronization header 1 within a delay range of 0-10.48576 ms as in the process shown in fig. 2, performing coarse timing StartIdx _1 after searching the synchronization header 1 as shown in fig. 3 at a receiving end for the above synchronization frame, and estimating a coarse frequency offset fd _ 1;

(1) firstly, 4 times of down-sampling (1 & ltpp & gt & lt 5 & gt) is carried out on the [ (pp-1 & gt 65536 & lt 2 & gt +65535] points and the [ (pp-1 & gt 65536 & lt 2 & gt +65536+1] points of the received signal rx, and continuous 4 sampling points in one chip are accumulated to be used as one point, for example, when the pp & lt 1 & gt, the 1 & gt, 2,3 and 4 points are accumulated to be used as the accumulated 1 & gt point, the 5 & gt, 6 & lt, 7 & gt and 8 points are accumulated to be used as the accumulated 2 & gt point, the accumulated 16384 & lt 2 points are obtained, and the 4096 points are used as a small window to obtain 8 qwin 8 (1 & lt q & gt) (1 & ltq & lt 8 & gt);

(2) presetting frequency deviation f (1) — 300kHz, f (2) — 100kHz, f (3) — 100kHz, f (4) — 300kHz, f (5) — 300kHz, f (6) — 100kHz, f (7) — 100kHz, f (8) — 300kHz, and denoted as f (qq) ((1) < ═ qq) — (8) for 8 small windows respectively;

(3) 4096 point data of each small window win8(qq) (1< ═ qq < ═ 8) is subjected to partial matched filtering and FFT (namely PMF-FFT) with the synchronization head 1 respectively, amplitude peak values of FFT results and peak positions in N-point FFT are recorded, wherein each section of the partial matched filter is X in length and P sections are calculated together, wherein P X is L is 4096, P partial correlation values are obtained, N-point FFT is carried out on the P partial correlation values, wherein N > is P, and the value of N can be automatically adjusted according to the consideration of complexity and frequency offset estimation precision in practical application;

(4) 4096 point data within each small window is circularly shifted right by 1 point, namely from 1,2, 3.., 4095,4096 to 4096,1, 2.., 4094,4095 according to the original data index;

(5) repeating (3) and (4) until L4096 times (3) and (4) are performed, each small window gets L4096 PMF-FFT peaks and the position where each peak appears, finding the maximum value Amax _4096 of 4096 peaks, recording the index position idx _ phase _4096 where the peak appears in 4096 peaks, and recording the index position idx _ FFT _4096 where the peak appears in N-point FFT;

(6) according to the method described in (5), peak values Amax _8win (qq), pseudo code phases idx _ phase _8win (qq), FFT peak index positions idx _ FFT _8win (qq) (1< ═ qq < ═ 8), maximum values Amax of the respective peak values of 8 small windows and positions ss where Amax appears in8 small windows are obtained, then Amax8 Amax _8win (ss8) (1< > ss8< ═ 8), pseudo code phases idx _ phase8 and idx _ phase _8win (ss), and index positions idx _ FFT8 idx _ FFT _8win (ss) where the peak values appear in N-point FFT are recorded;

(7) if pp <5, (1) (2) (3) (4) (5) (6) are repeated, and pp + 1; if pp5, 5 Amax8, ss8, idx _ phase8, and idx _ fft8 to Amax8_ sum (pp), idx _ ss8_ sum (pp), idx _ phase8_ sum (pp), idx _ fft8_ sum (pp) (1< ═ pp < (5));

(8) obtaining the maximum value from Amax8_ sum (1) to Amax8_ sum (5), and obtaining the maximum value A _ temp and the corresponding index pp5, namely A _ temp is Amax8_ sum (pp5) (1< ═ pp5< ═ 5);

(9) based on the position pp5 in (8), a pseudo code synchronization position phase _ temp ═ idx _ phase8_ sum (pp5) is obtained, which is the pseudo code synchronization position of the PN code with L4096 length (1 ═ phase _ temp ═ L);

(10) based on the position pp5 in the step (8), obtaining a peak position FFT _ temp ═ idx _ FFT8_ sum (pp5) (1 ═ FFT _ temp ═ N), which is the position where the peak value in the N-point FFT is located;

(11) based on (7) (8) (9), the coarse timing position StartIdx _1_ temp ═ p5-1) × (65536 × 2+ (ss8-1) × 16384+ (phase _ temp-1) × 4+1+ ss8_4, wherein when the value of ss8_4 is 0 or 1, if and only if the value of ss8 is between 1 and 4, ss8_4 is 0, and if the value of ss8 is between 5 and 8, ss8_4 is 1, the coarse timing position StartIdx _1_ temp is always located in the synchronization header 1 in the transmission frame, after the receiving end performs 4 times of down-sampling, the sync header 2 may appear at the StartIdx _1_ temp + L × 4 position at the earliest, 14 small windows of L4096 points searched backwards from the StartIdx _1_ temp + L × 4 position can certainly search the sync header 2, that is, the coarse timing position is StartIdx _1 ═ StartIdx _1_ temp +4096 ═ 4 ═ (pp5-1) × 65536 × 2+ ss8 × 16384+ (phase _ temp-1) × 4+1+ ss8_ 4;

(12) based on (2), (3) and (10), if the frequency interval is d _ f, the frequency offset in the small window is fft _ temp2 × d _ f, where d _ f is (Fs/DDC _ num)/(X × N), and when fft _ temp is in the range of 1-N/2, fft _ temp2 is fft _ temp; when fft _ temp is in the range of N/2+1 to N, fft _ temp2 is equal to fft _ temp-N; fs is a sampling frequency, DDC _ num is a sampling decimation multiple, X is a number of segments of the partial matched filter, and N is a number of FFT points, to obtain a coarse frequency offset fd _1 ═ FFT _ temp2 × d _ f + f (ss8), that is, frequency offset in the window + preset frequency offset of the window itself;

step four: searching for a synchronization header 2 in the flow shown in fig. 4, for the above synchronization frame, at a receiving end, after finding out a synchronization header 1 in a time delay range of 0-10.48576 ms through step three shown in fig. 5, the synchronization header 2 may appear at the StartIdx _1 position at the earliest, estimating fd _1 for subsequent data coarse frequency offset, and then finding out a position StartIdx _2 of the synchronization header 2;

(1) performing frequency offset compensation on the [ StartIdx _1] - [ StartIdx _1+4096 × 4 × 14] points of the received signal rx by using the coarse frequency offset fd _1 obtained in the step three to obtain rx 2;

(2) sampling [1] - [4096 × 4 × 14] points of rx2 by a factor of 4, accumulating 4 consecutive sampling points in one chip as one point, for example, accumulating 1 st, 2 nd, 3 th, and 4 th points as the accumulated 1 st point, accumulating 5 th, 6 th, 7 th, and 8 th points as the accumulated second point, and obtaining 4096 × 14 points and obtaining 14 small windows win14 — 0(tt) (1< ═ tt < (14)) with 4096 points as one small window;

(3) sampling [2] th to [4096 × 4 × 14+1] th points of rx2 by a factor of 4, accumulating 4 consecutive sampling points in one chip as one point, accumulating 2 nd, 3 rd, 4 th, and 5 th points of rx2 as the accumulated 1 st point, accumulating 6 th, 7 th, 8 th, and 9 th points as the accumulated 2 nd point, accumulating to obtain 4096 × 14 points, and obtaining 14 small windows win14 — 1(uu) (1< ═ uu < (14)) with 4096 points as one small window;

(4) since pseudo code synchronization has been determined in three steps, and the sync header 1 and the sync header 2 both use PN sequences of the same length L, the sync header at this time is already pseudo code synchronization, and PMF-FFT operation of (3) in three steps is performed once for each of 28 small windows win14_0 and win14_1, resulting in 28 FFT peaks fftM (vv) and corresponding peak positions fftM _ L (vv) (1< vv28, where 1< vv > -14 represents data of 14 windows win14_0, and 15< vv < > 28 represents data of 14 windows win14_ 1);

(5) finding out the maximum value fftM _ max of 28 FFT peak values fftM (vv) and recording that the maximum value appears in a vv 28-th window, that is, fftM _ max ═ fftM (vv28) (1 ═ vv28 ═ 28), and recording the corresponding peak value position fftM _ L _ max ═ fftM _ L (vv 28);

(6) the method comprises the steps that the starting chip of the sync head 2 appears at a StartIdx2 ═ StartIdx1+ (vv14-1) × 4096 × 4+ vv28_1, wherein when vv28 takes a value of 1-14, vv14 ═ vv28, vv28_1 ═ 0, when vv28 takes a value of 15-28, vv14 ═ vv28-14, and vv28_1 ═ 1;

step five: searching for the sync header 3 according to the flow shown in fig. 6, and for the above sync frame, at the receiving end, searching for the position of the sync header 3 and the best sampling point StartIdx _3 of the 4 sampling points of each chip in the sync header 3 through step four shown in fig. 7;

(1) as can be seen from the format of the sync frame, the sync header 3 appears at the position StartIdx3_ temp ═ StartIdx2+4096 ═ 4;

(2) considering that there may be an error of 1 chip (4 sampling points) when pseudo code synchronization is performed in step three, the search is extended from this position both forward and backward by one chip (4 points), so the earliest possible position of the sync header 3 is StartIdx3_ temp2 ═ StartIdx3_ temp-4;

(3) taking the [ StartIdx3_ temp ] to [ StartIdx3_ temp +4096 × 4+11] points of the received rx signal, and performing frequency offset compensation by using the coarse frequency offset fd _1 obtained in the step three to obtain rx 3;

(4) taking [ ww ] to [4096 × 4+ ww-1] points (1< ═ ww < ═ 12) of rx3, and performing 4-time down-sampling to obtain 12 groups of data win12(ww), wherein each group has 4096 points;

(5) since pseudo code synchronization has been determined in step three and step four, and the sync header 1, sync header 2, and sync header 3 all use PN sequences with the same length L, the sync header at this time is already pseudo code synchronization, and PMF-FFT operation of step three (3) is performed on 12 groups of data of win12, resulting in12 FFT peaks fftM3(ww) and corresponding peak positions fftM _ L3(ww) (1< ═ ww < (12));

(6) finding the maximum value fftM3_ max of 12 FFT peak values fftM3(vv) and recording the maximum value appearing in the ww12 group, that is, fftM3_ max ═ fftM3(ww12) (1< ═ ww12< ═ 12), and recording the corresponding peak position fftM3_ L _ max ═ fftM3_ L (ww 12);

(5) the best sample point position StartIdx3 in the start chip where the sync header 3 appears is StartIdx3_ temp2+ ww12-1(1< ═ ww12< ═ 12);

step six: performing fine frequency offset estimation in the flow shown in fig. 8, performing fine frequency offset estimation fd _2 on the synchronization frame at the receiving end by using the synchronization header 3 as shown in fig. 9, and already finding the best sampling point position StartIdx3 in the start chip of the synchronization header 3 through step five;

(1) taking the [ StartIdx3] to [ StartIdx3+4096 × 4 × 16-1] points of the received rx signal, and performing frequency offset compensation by using the coarse frequency offset fd _1 obtained in the step three to obtain rx 4;

(2) down-sampling rx4 by 4 times to obtain 4096 × 16 point data, dividing the data into 16 groups in the order of index, and recording each group of 4096 points as win16(xx) (1< ═ xx < (16));

(3) since the pseudo code synchronization has been determined in the third step, the fourth step and the fifth step, and the sync header 1, the sync header 2 and the sync header 3 all use PN sequences with the same length L, the sync header at this time is already pseudo code synchronization, and after the value of N is enlarged by M times, PMF-FFT operation in step three (3) is performed on each of 16 sets of data of win16 (i.e., N-point FFT is changed into N-M-point FFT), so as to obtain 16 sets of FFT calculation results FFT4(xx) (1< × xx < > 16), where each set of results is N-M points;

(6) calculating the modulus of 16 FFT calculation results FFT4(xx), then performing incoherent accumulation to obtain the result FFT4_ sum (xx) of N × M points, calculating the maximum value FFT4_ sum _ max, and recording the maximum value appearing at the yy point (1 ═ yy ═ N × M);

(7) setting the frequency interval as d _ f2, obtaining the frequency offset in the small window as yy X d _ f2, where d _ f2 is (Fs/DDC _ num)/(X N X M), Fs is the sampling frequency, DDC _ num is the down-sampling decimation multiple, X is the number of segments of the partial matched filter, N is the number of FFT points at the time of coarse frequency offset, and N M is the number of FFT points at the time of fine frequency offset, to obtain the fine frequency offset as fd _2 y X d _ f2, where M can be selected according to the actual accuracy requirement of fine frequency offset;

step seven: at the receiving end, as shown in fig. 10, the start position StartIdx4 and the frequency offset f _ last of the data frame after the synchronization frame is obtained are used for the synchronization frame;

(1) the data start position StartIdx4 ═ StartIdx3+ L ═ DDC _ num · Sync3_ num, and this position is also the optimal sampling point position from which downsampling of data can be performed;

(2) frequency offset f _ last is fd _1+ fd _ 2;

therefore, the whole synchronous frame completes pseudo code synchronization, timing synchronization and frequency offset estimation, can resist 0-10.48576 ms time delay and [ -400kHz,400kHz ] frequency offset, achieves capture probability of more than 99% under 25dB with coarse frequency offset precision d _ f1 being 1524Hz and fine frequency offset precision d _ f2 being 95Hz, and achieves anti-delay characteristic and anti-frequency offset characteristic in a wider range by flexibly expanding the lengths of a synchronous head 1, a synchronous head 2 and a synchronous head 3 in the frame and the search length of a receiving end.

Simulation result

The simulation results are further analyzed with reference to fig. 11 to 15, the simulation of the present invention is based on matlab2018.2 software, the simulation conditions of fig. 11 are-400 kHz with fixed frequency offset, signal-to-noise ratio range-25 dB to-24 dB, step interval 0.1dB, each signal-to-noise ratio environment is tested 1000 times, sampling frequency Fs is 50MHz, interpolation and extraction multiple DDC _ num is 4, PN sequence length L is 4096, a PMF segment matching filter is divided into P-128 segments, length X of each segment is 32, FFT is 256 points N, M is 16 in fine frequency offset, FFT is 4096 points N, 1000 points are simulated under each signal-to-noise ratio, and fig. 11 shows that the proposed synchronous frame structure design and corresponding synchronization method can achieve a capture probability of 99% or more for-400 kHz under-25 dB.

As can be seen from fig. 12 to 13, under a fixed-24 dB signal-to-noise ratio, the frequency offset range is-400 kHz to 400kHz, the step interval is 1kHz, and the above Fs, L, P, X, N, and M parameters are still used for simulation, so that a coarse frequency offset error and a fine frequency offset error can be obtained, the theoretical errors are all 0.5, and a certain deterioration can be caused by excessive noise at this time, and 16 times of incoherent accumulation used in step six in the embodiment can be extended to more times of incoherent accumulation to reduce errors.

As can be seen from fig. 14 to 15, under a fixed-15 dB signal-to-noise ratio, the frequency offset range is-400 kHz to 400kHz, the step interval is 1kHz, and the above Fs, L, P, X, N, and M parameters are still used for simulation, so that a coarse frequency offset error and a fine frequency offset error can be obtained, theoretical errors are all 0.5, and a certain deterioration is caused by a larger noise at this time, which is improved when compared with-24 dB, and the error can be reduced by expanding the 16 times of incoherent accumulation used in step six in the embodiment to more times of incoherent accumulation.

As can be seen from fig. 16 to 17, under a fixed 0dB signal-to-noise ratio, the frequency offset range is-400 kHz to 400kHz, the step interval is 1kHz, and the above Fs, L, P, X, N, and M parameters are still used for simulation, so that a coarse frequency offset error and a fine frequency offset error can be obtained, where the theoretical errors are all 0.5, and are affected by noise at this time, and a certain deterioration occurs, and there is a great improvement when compared with-24 dB and-15 dB, and the coarse frequency offset approaches the theoretical errors, and 16 times of incoherent accumulation used in the sixth step in the embodiment can be extended to more times of incoherent accumulation to reduce the errors.

As can be seen from fig. 18 to 19, under a fixed 0dB signal-to-noise ratio, the frequency offset range is-400 kHz to 400kHz, the step interval is 1kHz, and the Fs, L, P, X, N, and M parameters are still used for simulation, so that a coarse frequency offset error and a fine frequency offset error can be obtained, the theoretical errors are all 0.5, and a certain deterioration is caused by the noise at this time, which is greatly improved when compared with-24 dB, -15dB, and 0dB, and the coarse frequency offset and the fine frequency offset approach the theoretical errors, and 16 times of incoherent accumulation used in the sixth step in the embodiment can be extended to more times of incoherent accumulation to reduce the errors.

The above procedures and simulations show that the synchronization frame structure and the corresponding synchronization scheme of the present invention solve the synchronization frame structure design and synchronization detection problems suitable for low signal-to-noise ratio large frequency offset burst communication in a high-speed mobile scene, use the PN code to enhance the concealment of synchronization, have very good synchronization performance at the receiving end, have expandability, and lay the foundation for low signal-to-noise ratio communication and burst communication in a higher motion scene in the future.

Claims

1. A synchronous frame suitable for a high-speed motion scene is characterized by comprising a first synchronous head, a second synchronous head and a third synchronous head which are sequentially spliced, wherein the first synchronous head, the second synchronous head and the third synchronous head are subjected to DDC _ num times of interpolation, and DDC _ num is a positive integer;

sync1_ num is related to Fd _ num, and Sync1_ num > is 3 × Fd _ num + 1;

2. The synchronization method for the sync frame of high-speed motion scene as claimed in claim 1, comprising the steps of:

3. The method for synchronizing sync frames of high-speed moving scenes as claimed in claim 2, wherein the specific method of step S1 is:

4. The method for synchronizing the sync frame of the high-speed motion scene as claimed in claim 3, wherein the step S2 is specifically performed by:

5. The method for synchronizing the sync frame of the high-speed moving scene as claimed in claim 4, wherein the step S3 is specifically performed by:

6. The method for synchronizing the sync frame of the high-speed moving scene as claimed in claim 5, wherein the step S4 is specifically performed by:

7. The method for synchronizing the sync frame of the high-speed moving scene as claimed in claim 6, wherein the step S5 is specifically performed by:

s52, frequency offset f _ last ═ fd _1+ fd _ 2.

The whole synchronous frame completes pseudo code synchronization, timing synchronization and frequency offset estimation, and can resist the time delay of 0 to (T _ num-1) DDC _ num 4 2/Fs and the frequency offset of [ -Fd _ num 1.024 Fs/(DDC _ num X), Fd _ num 1.024 Fs/(DDC _ num X) ], the coarse frequency offset precision d _ f1 ═ F (Fs/DDC _ num)/(X) and the fine frequency offset precision d _ f2 (Fs/DDC _ num)/(X) so as to realize the time delay characteristic and the immunity characteristic of wider range by flexibly expanding the lengths of the synchronous head 1, the synchronous head 2 and the synchronous head 3 in the frame and the search length of a receiving end.