CN114362756A - Analog-to-digital conversion device, successive approximation type analog-to-digital converter, and electronic apparatus - Google Patents
Analog-to-digital conversion device, successive approximation type analog-to-digital converter, and electronic apparatus Download PDFInfo
- Publication number
- CN114362756A CN114362756A CN202210028414.XA CN202210028414A CN114362756A CN 114362756 A CN114362756 A CN 114362756A CN 202210028414 A CN202210028414 A CN 202210028414A CN 114362756 A CN114362756 A CN 114362756A
- Authority
- CN
- China
- Prior art keywords
- transistor
- gate
- voltage
- sampling signal
- analog
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
Abstract
The utility model relates to an analog-to-digital conversion device, successive approximation type analog-to-digital converter and electronic equipment, the device includes first transistor, second transistor, a plurality of electric capacity, a plurality of switches, first comparator, successive approximation logic SAR control module, charge pump, the source electrode of first transistor and the source electrode of second transistor are used for receiving first reference voltage, the grid of first transistor and the grid of second transistor receive the sampling signal, the charge pump is used for raising the pressure of sampling signal under the condition that the mains voltage that produces the sampling signal is less than first preset voltage and the sampling signal is the high level, SAR control module is used for controlling the conducting state of each switch to obtain the conversion voltage according to the comparative result of comparator. The embodiment of the disclosure can avoid voltage overshoot in analog-to-digital conversion, prevent electric leakage, improve the conversion precision of the analog-to-digital conversion device, and boost the sampling signal through the charge pump, thereby improving the sampling rate of the analog-to-digital conversion device.
Description
Technical Field
The present disclosure relates to the field of integrated circuit technologies, and in particular, to an analog-to-digital conversion apparatus, a successive approximation type analog-to-digital converter, and an electronic device.
Background
An ADC (analog-to-digital converter) is used to convert an analog signal of nature into a digital signal that can be recognized by a machine, wherein a SAR ADC (successive approximation analog-to-digital converter) is widely used with advantages of low power consumption and small area, however, the analog-to-digital conversion speed and accuracy of the current SAR ADC are increasingly unable to meet the requirements.
Disclosure of Invention
According to an aspect of the present disclosure, there is provided an analog-to-digital conversion apparatus for performing analog-to-digital conversion on an input voltage to obtain a converted voltage, the apparatus including a first transistor, a second transistor, a plurality of capacitors, a plurality of switches, a first comparator, a successive approximation logic SAR control module, and a charge pump, wherein,
a source of the first transistor and a source of the second transistor are configured to receive a first reference voltage, a gate of the first transistor and a gate of the second transistor are connected to the charge pump to receive a sampling signal, a drain of the first transistor is connected to a first end of each capacitor and a positive input terminal of the first comparator, and a drain of the second transistor is connected to a negative input terminal of the first comparator, wherein the sampling signal is configured to control a conduction state of the first transistor and the second transistor,
the charge pump is used for boosting the sampling signal under the condition that the power supply voltage for generating the sampling signal is lower than a first preset voltage and the sampling signal is at a high level,
the second ends of the capacitors are respectively connected with corresponding switches, the switches are used for connecting any one of the input voltage, the second reference voltage and the ground voltage into the second end of the corresponding capacitor,
the output end of the first comparator is connected to the SAR control module, and the SAR control module is used for controlling the conducting state of each switch and obtaining the conversion voltage according to the comparison result of the first comparator.
In one possible implementation, the charge pump includes a voltage detection module and a voltage boost module, wherein,
the voltage detection module is used for: and under the conditions that the power supply voltage is lower than the first preset voltage and the sampling signal is at a high level, controlling the boosting module to boost the input sampling signal so as to output the boosted sampling signal.
In one possible implementation, the voltage detection module includes a voltage divider circuit, a second comparator, a nand gate, a first not gate, a conversion capacitor, a third transistor, a fourth transistor, and a fifth transistor, wherein,
the first end of the voltage division circuit is connected with the power supply voltage, the second end of the voltage division circuit is grounded, the output end of the voltage division circuit is connected with the negative input end of the second comparator and outputs a voltage division signal,
a second preset voltage is input to the positive input end of the second comparator, the second preset voltage is obtained according to the first preset voltage, the output end of the second comparator is connected to the first input end of the NAND gate,
the second input end of the nand gate is used for accessing the sampling signal, the output end of the nand gate is connected with the input end of the first not gate, the grid of the third transistor and the grid of the fifth transistor,
the output end of the first not gate is connected to the first end of the conversion capacitor, the second end of the conversion capacitor is connected to the source electrode of the third transistor, the drain electrode of the fourth transistor and the power supply end of the boosting module, the drain electrode of the third transistor is connected to the gate electrode of the fourth transistor and the drain electrode of the fifth transistor, the source electrode of the fourth transistor is connected to the power supply voltage, and the source electrode of the fifth transistor is grounded.
In one possible implementation, the boost module includes a second not gate, a third not gate, a fourth not gate, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor, wherein,
an input end of the second not gate is used for inputting the sampling signal, an output end of the second not gate is connected to a gate of the sixth transistor and an input end of the third not gate, a power supply end of the second not gate is connected to the power supply voltage,
a source of the sixth transistor, a source of the ninth transistor, the second not gate, the third not gate, and a ground terminal of the fourth not gate are grounded,
a drain of the sixth transistor is connected to a source of the seventh transistor and a gate of the eighth transistor,
a gate of the seventh transistor is connected to the source of the eighth transistor, the input terminal of the fourth not-gate, and the drain of the ninth transistor, a drain of the seventh transistor is connected to the drain of the eighth transistor and the power source terminal of the fourth not-gate, and is configured to receive a second power source voltage,
the output end of the third not gate is connected with the grid electrode of the ninth transistor, the power supply end of the third not gate is connected with the power supply voltage,
and the output end of the fourth NOT gate is used for outputting the boosted sampling signal.
In one possible implementation, the third transistor and the fourth transistor are PMOS transistors, and the fifth transistor is an NMOS transistor.
In one possible implementation, the sixth transistor and the ninth transistor are NMOS transistors, and the seventh transistor and the eighth transistor are PMOS transistors.
In one possible implementation, the first transistor and the second transistor are NMOS transistors.
According to an aspect of the present disclosure, a successive approximation type analog-to-digital converter is provided, and the successive approximation type analog-to-digital converter includes the analog-to-digital conversion device.
According to an aspect of the present disclosure, there is provided an electronic device including the successive approximation type analog-to-digital converter.
The embodiment of the disclosure realizes the control of the voltage input of the analog-digital conversion device through the first transistor and the second transistor, can avoid voltage overshoot in analog-digital conversion, prevent electric leakage, and improve the conversion precision of the analog-digital conversion device, and can improve the sampling rate of the analog-digital conversion device by boosting the sampling signal through the charge pump under the condition that the power voltage generating the sampling signal is lower than the first preset voltage and the sampling signal is at a high level.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure.
Fig. 1 shows a schematic diagram of an analog-to-digital conversion apparatus according to an embodiment of the present disclosure.
Fig. 2 shows a schematic diagram of a charge pump according to an embodiment of the present disclosure.
Fig. 3 shows a schematic diagram of a boost module according to an embodiment of the present disclosure.
Detailed Description
Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
In the description of the present disclosure, it is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, as used herein, refer to an orientation or positional relationship indicated in the drawings, which is solely for the purpose of facilitating the description and simplifying the description, and does not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and, therefore, should not be taken as limiting the present disclosure.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present disclosure, "a plurality" means two or more unless specifically limited otherwise.
In the present disclosure, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integral; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate.
The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, and may mean including any one or more elements selected from the group consisting of A, B and C.
Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.
Referring to fig. 1, fig. 1 is a schematic diagram illustrating an analog-to-digital conversion apparatus according to an embodiment of the disclosure.
The device is used for performing analog-to-digital conversion on an input voltage VIN to obtain a conversion voltage, and as shown in fig. 1, the device comprises a first transistor Q1, a second transistor Q2, a plurality of capacitors (capacitors C1-Cn, n is a positive integer), a plurality of switches (switches S1-Sn, n is a positive integer), a first comparator Cmp1, a successive approximation logic SAR control module 20, and a charge pump 10, wherein,
a source of the first transistor Q1 and a source of the second transistor Q2 are configured to receive a first reference voltage VCM, a gate of the first transistor Q1 and a gate of the second transistor Q2 are connected to the charge pump 10 to receive a sampling signal Sa, a drain of the first transistor Q1 is connected to a first end of each capacitor and a positive input of the first comparator Cmp1, a drain of the second transistor Q2 is connected to a negative input of the first comparator Cmp1, wherein the sampling signal Sa is configured to control a conduction state of the first transistor Q1 and the second transistor Q2,
the charge pump 10 is used for boosting the sampling signal Sa when the power supply voltage VDD for generating the sampling signal Sa is lower than a first preset voltage Vref1 and the sampling signal Sa is at a high level,
the second terminals of the capacitors are respectively connected to corresponding switches, the switches are used for connecting any one of the input voltage VIN, the second reference voltage VREF and the ground voltage GND to the second terminals of the corresponding capacitors,
the output end of the first comparator Cmp1 is connected to the SAR control module 20, and the SAR control module 20 is configured to control the on-state of each switch and obtain the switching voltage according to the comparison result of the first comparator Cmp 1.
The embodiment of the disclosure realizes the control of the voltage input of the analog-digital conversion device through the first transistor and the second transistor, can avoid voltage overshoot in analog-digital conversion, prevent electric leakage, and improve the conversion precision of the analog-digital conversion device, and can improve the sampling rate of the analog-digital conversion device by boosting the sampling signal through the charge pump under the condition that the power voltage generating the sampling signal is lower than the first preset voltage and the sampling signal is at a high level.
The sampling rate in the disclosed embodiments is an important measure of the ADC, which in SAR ADCs refers to the rate from sampling an analog input signal to converting out a digital code.
The related art uses Transmission gates to control the voltage input of the analog-to-digital conversion device, for example, two Transmission gates (CMOS Transmission gates) are used to replace the first transistor Q1 and the second transistor Q2, however, the scheme of sampling the Transmission gates in the related art may cause leakage, and the embodiment of the present disclosure uses the first transistor Q1 and the second transistor Q2 to prevent leakage, so as to improve the conversion accuracy, which is described in the following exemplary description.
Assuming that the first transistor Q1 and the second transistor Q2 are replaced by transmission gates, in this case, the transmission gates receive the sampling signal Sa and its inverted signal Sab, and if the input sampling signal Sa is high and the inverted signal Sab is low, the transmission gates are opened, and all capacitors are connected to one plate VCMVoltage (e.g., value 1/2VREF, where VREF is the reference voltage for the ADC) while the first comparator Cmp1 negative terminal is also tied in VCMVoltage, another capacitor plate connected to input voltage VINWill VINIn the form of an electric charge in the capacitor. Taking N-bit SAR ADC as an example, the charge quantity Q of the sampling phase1As shown in equation 1, where N is a positive integer.
Q1＝2NC·(VCM-VIN) Equation 1
During the first charge redistribution, a prejudgment is firstly carried out, the lower electrode plate of the capacitor at the highest position is connected to VREF in a preset mode, the rest positions are still kept grounded, and the following formula 2 and formula 3 can be obtained according to the charge conservation:
Q1＝Q2＝2N-1C·(VX-VREF)+2N-1·C·VXequation 2
Wherein Q is2Representing the amount of charge after redistribution of charge, C representing the charge of the capacitor, VXRepresenting the voltage at the positive input of the first comparator Cmp 1.
If a transmission gate switch is adopted, V is converted due to charge in the working process of the SAR ADCXAn overshoot in the voltage value may occur. VINAt VDD, due to overshoot VXWill be lower than GND to cause NMOS leakage, VINAt GND, due to overshoot VXHigher than VDD results in PMOS leakage, which will cause charge leakage on the existing capacitor, losing the accuracy of the ADC.
Therefore, the first transistor Q1 and the second transistor Q2 are adopted in the embodiment of the disclosure, and the first reference voltage VCM can be set (the embodiment of the disclosure does not limit the generation manner of the first reference voltage VCM, for example, VDD can be divided by a voltage dividing circuit, which can be set according to actual situations and needs) to be larger than 1/2VDD, so that even though overshoot is generated, V is setXThe voltage is not lower than the ground, and no leakage occurs. However, the inventor has found that the conduction capability of such switches (the first transistor Q1 and the second transistor Q2) at low voltage and low temperature becomes very weak, which results in that the sampling time is increased to sample the analog input signal, and the sampling rate is reduced, especially when the previous signal is converted to GND and the next signal is converted to VDD and V is converted to VXFor example, for a sampling process when the VDD voltage is 2.7V, the sampling time may reach 7ms, which is quite long, and the analog-to-digital conversion precision is reduced, therefore, the present disclosure boosts the sampling signal by the charge pump under the condition that the power voltage for generating the sampling signal is lower than the first preset voltage and the sampling signal is at a high level,the sampling rate of the analog-to-digital conversion apparatus can be increased.
The embodiments of the present disclosure do not limit the specific implementation manners of the charge pump, the SAR control module, and other devices, and those skilled in the art can implement the functions according to actual situations and needs by using related technologies.
For example, the SAR control module may be implemented by a processing component, which in one example includes but is not limited to a single processor, or discrete components, or a combination of a processor and discrete components. The processor may comprise a controller having functionality to execute instructions in an electronic device, which may be implemented in any suitable manner, e.g., by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic components. Within the processor, the executable instructions may be executed by hardware circuits such as logic gates, switches, Application Specific Integrated Circuits (ASICs), programmable logic controllers, and embedded microcontrollers.
For example, the SAR control module may output a switch control signal 201 to control the on-state of each switch (S1-Sn), the switch control signal 201 may include n bits, each bit corresponds to each switch, the embodiment of the present disclosure does not limit the specific manner and timing for the SAR control module to generate the switch control signal 201, a person skilled in the art may refer to related technologies according to actual situations and needs, the embodiment of the present disclosure does not limit the implementation manner of each switch, the switch may be a multiplexer MUX, or may be another type of switch, the embodiment of the present disclosure does not limit the size of n, and a person skilled in the art may determine the number of bits of analog-to-digital conversion. Of course, the analog-to-digital conversion apparatus may further include other modules and devices, for example, a digital-to-analog converter DAC (for example, VREF is generated according to a preset reference voltage and a digital signal output by the SAR control module), and the like, which is not limited in the embodiment of the present disclosure.
Referring to fig. 2, fig. 2 shows a schematic diagram of a charge pump according to an embodiment of the disclosure.
In one possible implementation, as shown in fig. 2, the charge pump 10 may include a voltage detection module 110 and a voltage boost module 120, wherein,
the voltage detection module 110 is configured to: when the power voltage VDD is lower than the first preset voltage Vref1 and the sampling signal Sa is at a high level, the voltage boost module 120 is controlled to boost the input sampling signal Sa to output a boosted sampling signal Sa (i.e., Sa _ pump).
The embodiments of the present disclosure do not limit the specific implementation manners of the voltage detection module and the voltage boost module, and those skilled in the art can select related technologies to implement the voltage detection module and the voltage boost module according to actual situations and needs as long as the corresponding functions can be implemented.
In one possible implementation, as shown in fig. 2, the voltage detection module 110 may include a voltage divider circuit 1110, a second comparator Cmp2, a NAND gate NAND, a first NOT gate NOT1, a transfer capacitor Ct, a third transistor Q3, a fourth transistor Q4, and a fifth transistor Q5, wherein,
a first end of the voltage dividing circuit 1110 is connected to the power voltage VDD, a second end of the voltage dividing circuit 1110 is grounded, an output end of the voltage dividing circuit 1110 is connected to a negative input end of the second comparator Cmp2, and outputs a divided voltage signal,
a second preset voltage Vref2 is input to a positive input terminal of the second comparator Cmp2, the second preset voltage Vref2 is obtained according to the first preset voltage Vref1, an output terminal of the second comparator Cmp2 is connected to a first input terminal of the NAND gate NAND,
a second input terminal of the NAND gate NAND is configured to receive the sampling signal Sa, an output terminal of the NAND gate NAND is connected to the input terminal of the first NOT gate 1, the gate of the third transistor Q3, and the gate of the fifth transistor Q5,
an output end of the first NOT gate 1 is connected to a first end of the conversion capacitor Ct, a second end of the conversion capacitor Ct is connected to a source of the third transistor Q3, a drain of the fourth transistor Q4 and a power supply end of the voltage boost module 120, a drain of the third transistor Q3 is connected to a gate of the fourth transistor Q4 and a drain of the fifth transistor Q5, a source of the fourth transistor Q4 is connected to the power supply voltage VDD, and a source of the fifth transistor Q5 is grounded.
For example, the voltage dividing circuit 1110 may include a plurality of voltage dividing resistors, each of which is connected in series between the power supply voltage VDD and ground, and a desired voltage dividing signal is obtained by selecting a suitable output node.
The specific magnitudes of the first preset voltage and the second preset voltage are not limited in the embodiments of the present disclosure, and the relationship between the first preset voltage and the second preset voltage is not limited, and those skilled in the art can set the voltages according to actual situations and needs.
For example, assuming that the first preset voltage is 2.8V, the second preset voltage may be set to be 1.2V (or other voltages) smaller than the first preset voltage, and the sizes of the resistors of the voltage divider circuit and the output nodes are reasonably selected, where the second preset voltage may be generated by the bandgap voltage reference circuit with zero temperature coefficient, and for example, when the VDD voltage is smaller than 2.8V, the negative input terminal of the comparator will be smaller than 1.2V through voltage division by the resistors, and the output of the comparator will generate a high level. When the sampling signal Sa is low, the node 1 is low, the fifth transistor Q5 is turned on (turned on), the third transistor Q3 is turned off, the node 3 is low, the fourth transistor Q4 is turned on, the node 2 is charged to VDD, and the third transistor Q3 is turned off.
Illustratively, when the sampling signal Sa is at a high level, the node 1 is at a high level, the fifth transistor Q5 is turned off, the third transistor Q3 is turned on, the nodes 2 and 3 are charged to 2 × VDD due to the conservation of charge, and the fourth transistor Q4 is turned off. Illustratively, the node 2 is always the highest voltage, VDD or 2 × VDD, and the embodiment of the disclosure can use the voltage output by the node 2 as the power source of the high voltage of the boost module, so as to reduce the circuit area and save the cost.
For example, the sampling signal Sa outputs an Sa _ pump signal through the boost circuit, and a digital signal with a power domain close to 2VDD to 0 is output, so that according to the embodiment of the present disclosure, the boosted sampling signal Sa, that is, the Sa _ pump signal, is used as the sampling signals of the first transistor and the second transistor, which can reduce the switch on resistance, reduce the sampling time, and improve the sampling rate.
For example, after the voltage is boosted by the charge pump, the power domain of the sampling signal Sa may be increased from 2.4V to 0 to approximately 4.8V to 0 in the embodiment of the present disclosure.
Referring to fig. 3, fig. 3 is a schematic diagram illustrating a boosting module according to an embodiment of the disclosure.
In one possible implementation, as shown in fig. 3, the boost module 120 includes a second NOT gate NOT2, a third NOT gate NOT3, a fourth NOT gate NOT4, a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8, and a ninth transistor Q9, wherein,
an input end of the second NOT gate NOT2 is used for inputting the sampling signal Sa, an output end of the second NOT gate NOT2 is connected to a gate of the sixth transistor Q6 and an input end of the third NOT gate NOT3, a power supply end of the second NOT gate NOT2 is connected to the power supply voltage VDD,
the sources of the sixth transistor Q6, the ninth transistor Q9, the second NOT2, the third NOT3 and the fourth NOT4 are grounded,
the drain of the sixth transistor Q6 is connected to the source of the seventh transistor Q7, the gate of the eighth transistor Q8,
a gate of the seventh transistor Q7 is connected to the source of the eighth transistor Q8, the input terminal of the fourth NOT gate NOT4, and the drain of the ninth transistor Q9, a drain of the seventh transistor Q7 is connected to the drain of the eighth transistor Q8 and the power source terminal of the fourth NOT gate NOT4, and is configured to receive a second power voltage VDD2,
an output end of the third NOT gate NOT3 is connected to the gate of the ninth transistor Q9, a power supply end of the third NOT gate NOT3 is connected to the power supply voltage VDD,
an output terminal of the fourth NOT gate NOT4 is configured to output the boosted sampling signal Sa (i.e., Sa _ pump).
Illustratively, the second power voltage VDD2 may be a voltage output from the second end of the converted voltage, i.e., the node 2.
Through the boost module, the boost processing of the sampling signal can be efficiently and quickly realized in the embodiment of the disclosure.
In one possible implementation, the third transistor Q3 and the fourth transistor Q4 are PMOS transistors, and the fifth transistor Q5 is an NMOS transistor.
In one possible implementation, the sixth transistor Q6, the NMOS transistor of the ninth transistor Q9, the seventh transistor Q7, and the eighth transistor Q8 are PMOS transistors.
In one possible implementation, the first transistor Q1 and the second transistor Q2 are NMOS transistors.
Of course, the above selection of each transistor is exemplary, the specific type of the transistor is not limited in the embodiments of the present disclosure, and those skilled in the art can select the transistor according to actual situations and needs.
The analog-digital conversion device provided by the embodiment of the disclosure has higher conversion precision and sampling rate, and through the above devices, the gate voltage of the NMOS sampling switch can be increased from VDD to VDD close to 2VDD or VDD of other multiples when SAR ADC samples at low voltage and low temperature.
Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (9)
1. An analog-to-digital conversion device is used for performing analog-to-digital conversion on an input voltage to obtain a conversion voltage, and comprises a first transistor, a second transistor, a plurality of capacitors, a plurality of switches, a first comparator, a successive approximation logic SAR control module and a charge pump, wherein,
a source of the first transistor and a source of the second transistor are configured to receive a first reference voltage, a gate of the first transistor and a gate of the second transistor are connected to the charge pump to receive a sampling signal, a drain of the first transistor is connected to a first end of each capacitor and a positive input terminal of the first comparator, and a drain of the second transistor is connected to a negative input terminal of the first comparator, wherein the sampling signal is configured to control a conduction state of the first transistor and the second transistor,
the charge pump is used for boosting the sampling signal under the condition that the power supply voltage for generating the sampling signal is lower than a first preset voltage and the sampling signal is at a high level,
the second ends of the capacitors are respectively connected with corresponding switches, the switches are used for connecting any one of the input voltage, the second reference voltage and the ground voltage into the second end of the corresponding capacitor,
the output end of the first comparator is connected to the SAR control module, and the SAR control module is used for controlling the conducting state of each switch and obtaining the conversion voltage according to the comparison result of the first comparator.
2. The apparatus of claim 1, wherein the charge pump comprises a voltage detection module and a boost module, wherein,
the voltage detection module is used for: and under the conditions that the power supply voltage is lower than the first preset voltage and the sampling signal is at a high level, controlling the boosting module to boost the input sampling signal so as to output the boosted sampling signal.
3. The apparatus of claim 2, wherein the voltage detection module comprises a voltage divider circuit, a second comparator, a NAND gate, a first NOT gate, a conversion capacitor, a third transistor, a fourth transistor, and a fifth transistor, wherein,
the first end of the voltage division circuit is connected with the power supply voltage, the second end of the voltage division circuit is grounded, the output end of the voltage division circuit is connected with the negative input end of the second comparator and outputs a voltage division signal,
a second preset voltage is input to the positive input end of the second comparator, the second preset voltage is obtained according to the first preset voltage, the output end of the second comparator is connected to the first input end of the NAND gate,
the second input end of the nand gate is used for accessing the sampling signal, the output end of the nand gate is connected with the input end of the first not gate, the grid of the third transistor and the grid of the fifth transistor,
the output end of the first not gate is connected to the first end of the conversion capacitor, the second end of the conversion capacitor is connected to the source electrode of the third transistor, the drain electrode of the fourth transistor and the power supply end of the boosting module, the drain electrode of the third transistor is connected to the gate electrode of the fourth transistor and the drain electrode of the fifth transistor, the source electrode of the fourth transistor is connected to the power supply voltage, and the source electrode of the fifth transistor is grounded.
4. The apparatus of claim 2, wherein the boost module comprises a second NOT gate, a third NOT gate, a fourth NOT gate, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, wherein,
an input end of the second not gate is used for inputting the sampling signal, an output end of the second not gate is connected to a gate of the sixth transistor and an input end of the third not gate, a power supply end of the second not gate is connected to the power supply voltage,
a source of the sixth transistor, a source of the ninth transistor, the second not gate, the third not gate, and a ground terminal of the fourth not gate are grounded,
a drain of the sixth transistor is connected to a source of the seventh transistor and a gate of the eighth transistor,
a gate of the seventh transistor is connected to the source of the eighth transistor, the input terminal of the fourth not-gate, and the drain of the ninth transistor, a drain of the seventh transistor is connected to the drain of the eighth transistor and the power source terminal of the fourth not-gate, and is configured to receive a second power source voltage,
the output end of the third not gate is connected with the grid electrode of the ninth transistor, the power supply end of the third not gate is connected with the power supply voltage,
and the output end of the fourth NOT gate is used for outputting the boosted sampling signal.
5. The apparatus of claim 3, wherein the third transistor and the fourth transistor are PMOS transistors and the fifth transistor is an NMOS transistor.
6. The apparatus of claim 4, wherein the NMOS transistors of the sixth transistor and the ninth transistor, and wherein the seventh transistor and the eighth transistor are PMOS transistors.
7. The apparatus of any of claims 1-6, wherein the first transistor and the second transistor are NMOS transistors.
8. A successive approximation analog to digital converter, characterized in that it comprises an analog to digital conversion arrangement according to any of claims 1-7.
9. An electronic device, characterized in that the electronic device comprises a successive approximation analog-to-digital converter according to claim 8.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210028414.XA CN114362756B (en) | 2022-01-11 | 2022-01-11 | Analog-to-digital conversion device, successive approximation type analog-to-digital converter, and electronic apparatus |
| PCT/CN2022/088782 WO2023134053A1 (en) | 2022-01-11 | 2022-04-24 | Analog-to-digital conversion apparatus, successive-approximation-register analog-to-digital converter, and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210028414.XA CN114362756B (en) | 2022-01-11 | 2022-01-11 | Analog-to-digital conversion device, successive approximation type analog-to-digital converter, and electronic apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114362756A true CN114362756A (en) | 2022-04-15 |
| CN114362756B CN114362756B (en) | 2022-10-11 |
Family
ID=81108992
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210028414.XA Active CN114362756B (en) | 2022-01-11 | 2022-01-11 | Analog-to-digital conversion device, successive approximation type analog-to-digital converter, and electronic apparatus |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN114362756B (en) |
| WO (1) | WO2023134053A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023134053A1 (en) * | 2022-01-11 | 2023-07-20 | 上海晟矽微电子股份有限公司 | Analog-to-digital conversion apparatus, successive-approximation-register analog-to-digital converter, and electronic device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7961132B1 (en) * | 2010-02-03 | 2011-06-14 | Linear Technology Corporation | Sampling switch and controller |
| CN102843136A (en) * | 2012-09-15 | 2012-12-26 | 复旦大学 | Method for correcting offset of high-speed high-precision large-range low-power-consumption dynamic comparator |
| CN106330182A (en) * | 2016-10-19 | 2017-01-11 | 上海晟矽微电子股份有限公司 | Comparator module and successive approximation analog-to-digital converter |
| CN111326203A (en) * | 2018-12-17 | 2020-06-23 | 北京兆易创新科技股份有限公司 | Circuit for controlling voltage ripple |
| CN111711452A (en) * | 2020-07-21 | 2020-09-25 | 桂林电子科技大学 | Active-passive noise shaping successive approximation ADC |
| CN112398479A (en) * | 2020-09-30 | 2021-02-23 | 西安电子科技大学 | High-speed high accuracy SAR ADC circuit of single channel |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7821441B2 (en) * | 2008-12-19 | 2010-10-26 | Silicon Laboratories Inc. | SAR analog-to-digital converter having variable currents for low power mode of operation |
| US10972118B1 (en) * | 2020-04-23 | 2021-04-06 | Silicon Laboratories Inc. | Successive-approximation analog-to-digital converter gain calibration using floating capacitors |
| CN111865320B (en) * | 2020-07-30 | 2024-02-09 | 楚天龙股份有限公司 | Low-power-consumption successive approximation type analog-to-digital converter |
| CN114362756B (en) * | 2022-01-11 | 2022-10-11 | 上海晟矽微电子股份有限公司 | Analog-to-digital conversion device, successive approximation type analog-to-digital converter, and electronic apparatus |
-
2022
- 2022-01-11 CN CN202210028414.XA patent/CN114362756B/en active Active
- 2022-04-24 WO PCT/CN2022/088782 patent/WO2023134053A1/en unknown
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7961132B1 (en) * | 2010-02-03 | 2011-06-14 | Linear Technology Corporation | Sampling switch and controller |
| CN102843136A (en) * | 2012-09-15 | 2012-12-26 | 复旦大学 | Method for correcting offset of high-speed high-precision large-range low-power-consumption dynamic comparator |
| CN106330182A (en) * | 2016-10-19 | 2017-01-11 | 上海晟矽微电子股份有限公司 | Comparator module and successive approximation analog-to-digital converter |
| CN111326203A (en) * | 2018-12-17 | 2020-06-23 | 北京兆易创新科技股份有限公司 | Circuit for controlling voltage ripple |
| CN111711452A (en) * | 2020-07-21 | 2020-09-25 | 桂林电子科技大学 | Active-passive noise shaping successive approximation ADC |
| CN112398479A (en) * | 2020-09-30 | 2021-02-23 | 西安电子科技大学 | High-speed high accuracy SAR ADC circuit of single channel |
Non-Patent Citations (1)
| Title |
|---|
| PRAKASH HARIKUMAR等: "Design of a sampling switch for a 0.4-V SAR ADC using a multi-stage charge pump", 《 2014 NORCHIP》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023134053A1 (en) * | 2022-01-11 | 2023-07-20 | 上海晟矽微电子股份有限公司 | Analog-to-digital conversion apparatus, successive-approximation-register analog-to-digital converter, and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114362756B (en) | 2022-10-11 |
| WO2023134053A1 (en) | 2023-07-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105391451B (en) | Switching method when a kind of gradual approaching A/D converter and its analog-to-digital conversion | |
| CN105007079B (en) | The fully differential increment method of sampling of gradual approaching A/D converter | |
| TWI434517B (en) | Method and apparatus for evaluating weighting of elements of dac and sar adc using the same | |
| WO2013002957A2 (en) | Two-stage analog-to-digital converter using sar and tdc | |
| CN103595412B (en) | The capacitor array of the little area of low-power consumption and repositioning method thereof and logic control method | |
| CN104967451A (en) | Successive approximation type analog-to-digital converter | |
| US9041575B2 (en) | Analog-to-digital conversion apparatus and method capable of achieving fast settling | |
| CN110012677A (en) | Condenser type gradually-appoximant analog-digital converter | |
| CN107437941B (en) | Charge compensation circuit and analog-to-digital converter | |
| CN114362756B (en) | Analog-to-digital conversion device, successive approximation type analog-to-digital converter, and electronic apparatus | |
| CN109150181A (en) | A kind of self-alignment 12bit SAR ADC structure and method for self-calibrating | |
| CN106301376B (en) | Low-power-consumption successive approximation type analog-to-digital converter with adjustable comparator bias current | |
| US20240069073A1 (en) | Multi-level voltage detector | |
| Sekimoto et al. | A power scalable SAR-ADC in 0.18 µm-CMOS with 0.5 V nano-watt operation | |
| CN209913801U (en) | Switch circuit and capacitance resistance hybrid SAR ADC | |
| CN112187265A (en) | Mixed type analog-digital converter and signal transceiver for electric power special communication network | |
| WO2012081960A1 (en) | Dual- function successive approximation analog to digital converter (sa-adc) | |
| US20040257257A1 (en) | A/D converter and A/D conversion method | |
| EP1349283A2 (en) | A/D converter circuit | |
| CN104734721B (en) | Low-power consumption Radix-4 charge redistribution type DAC and switching method | |
| Zhang et al. | SAR ADC using single-capacitor pulse width to analog converter based DAC | |
| CN111817553B (en) | On-chip charge pump circuit | |
| CN214799459U (en) | Successive approximation type analog-to-digital conversion device | |
| CN110071722B (en) | Voltage scaling type successive approximation digital-to-analog conversion circuit | |
| Jeong et al. | A 0.16 mm2 12b 30MS/s 0.18 μm CMOS SAR ADC based on low-power composite switching |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |