CN114362743A - Level conversion circuit for converting from high level to low level - Google Patents
Level conversion circuit for converting from high level to low level Download PDFInfo
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- CN114362743A CN114362743A CN202210016599.2A CN202210016599A CN114362743A CN 114362743 A CN114362743 A CN 114362743A CN 202210016599 A CN202210016599 A CN 202210016599A CN 114362743 A CN114362743 A CN 114362743A
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Abstract
The present invention provides a level shift circuit for shifting from a high level to a low level, the level shift circuit comprising: a voltage dividing circuit configured to divide an input voltage to output an output voltage from an output node; a speed-up circuit configured to rapidly switch the output voltage on switching of the input voltage by rapidly switching a first transistor on through a first capacitor; a clamp protection circuit configured to prevent the output voltage from jumping up when the input voltage switches.
Description
Technical Field
The present disclosure relates generally to level shifting circuits, and more particularly, to level shifting circuits for shifting from a high level to a low level.
Background
With the continuous development of the integrated circuit industry, the chip technology is continuously updated, the system complexity is continuously improved, and the logic communication between chips in the same system is more and more indispensable. However, the logic levels of different chips are not completely consistent, and the common devices in the chips are also divided into high-voltage devices and low-voltage devices, so that when the two chips are communicated, the input logic level and the output level are different, the chip cascade application cannot be directly carried out, the high-level directly drives the low-voltage devices to cause circuit damage, and at the moment, the level conversion circuit is required to realize logic driving. And as the frequency of the current signal is continuously increased, the speed requirement of the level conversion circuit is also increased increasingly.
Disclosure of Invention
Technical problem
The conventional Level Shift circuit can realize the transmission from low Level to high Level, but for the high Level driving low Level circuit, the existing Level Shift device in the market generally has large packaging size and high cost. In addition, depending on the magnitude of the voltage-dividing resistance value, there is a possibility that problems of leakage and an increase in circuit area and an increase in cost occur. Meanwhile, when the circuit has a large parasitic capacitance, the problem of too long level conversion time may also occur, even the circuit cannot convert to the target level, resulting in error code.
Solution scheme
An embodiment of the present invention provides a level shift circuit for shifting from a high level to a low level, the level shift circuit including: a voltage dividing circuit configured to divide an input voltage to output an output voltage from an output node; a speed-up circuit configured to rapidly switch the output voltage on switching of the input voltage by rapidly switching a first transistor on through a first capacitor; a clamp protection circuit configured to prevent the output voltage from jumping up when the input voltage switches.
An embodiment of the present invention provides a level shift circuit for shifting from a high level to a low level, wherein the voltage dividing circuit includes N voltage dividing diodes connected in series between an input node receiving the input voltage and a ground node, where N is a natural number equal to or greater than 2.
An embodiment of the present invention provides a level shift circuit for shifting from a high level to a low level, wherein the voltage divider circuit further includes M resistors connected in series to the N voltage divider diodes to perform fine adjustment on the voltage divider circuit, where M is a natural number greater than or equal to 0.
An embodiment of the present invention provides a level shift circuit for shifting from a high level to a low level, wherein any one point of the N voltage-dividing diodes and the M resistors may be used as the output node.
An embodiment of the present invention provides a level shift circuit for shifting from a high level to a low level, wherein one end of the first capacitor is connected to the input node, and the other end is connected to a gate terminal of the first transistor.
An embodiment of the present invention provides a level shift circuit for shifting from a high level to a low level, wherein a source and a drain of the first transistor are connected to the output node and a ground node, respectively, and a gate thereof is connected to one end of the first capacitor.
An embodiment of the present invention provides a level shift circuit for shifting from a high level to a low level, wherein the speed-up circuit further includes a first resistor connected between the output node and a gate terminal of the first transistor.
An embodiment of the present invention provides a level shift circuit for shifting from a high level to a low level, wherein a resistance value of the first resistor is larger than a first threshold value.
An embodiment of the present invention provides a level shift circuit for shifting from a high level to a low level, wherein the clamp protection circuit includes a second transistor and a second capacitor, wherein a gate of the second transistor is connected to a gate of the first transistor through the second capacitor, and is configured to generate a pull-down signal instantaneously when the gate of the first transistor jumps up when the level is switched from low to high.
An embodiment of the present invention provides a level shift circuit for shifting from a high level to a low level, wherein the clamp protection circuit further includes a second resistor, wherein the second resistor is connected between a gate of the second transistor and a ground node, and functions as a bias resistance to prevent leakage of current of the second transistor at a normal operation.
An embodiment of the present invention provides a level shift circuit for shifting from a high level to a low level, wherein the clamping protection circuit further includes a clamping diode, wherein a positive terminal of the clamping diode is grounded and a negative terminal thereof is connected to a gate of the second transistor to clamp a gate terminal of the second transistor.
Embodiments of the present invention provide a level shift circuit for shifting from a high level to a low level, wherein an equivalent parasitic capacitance for a subsequent low level logic circuit is further included between the output node and a ground node.
Technical effects
The present disclosure generally provides a level shift circuit for shifting from a high level to a low level, which effectively reduces the chip area of the existing circuit without increasing additional power consumption, and simultaneously, an acceleration circuit and a clamp protection circuit are added to the level shift circuit, so as to achieve fast response of a logic level from high to low and from low to high, and prevent a low-voltage transistor in a rear-stage low-level logic chip from being damaged. The cascade application among chips with different levels in a multi-chip complex system is met.
Drawings
The above and other aspects, features and advantages of particular embodiments of the present disclosure will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a signal flow diagram showing a level shifting circuit for shifting from a high level to a low level;
fig. 2 is a diagram showing a level conversion circuit including a separate resistance voltage division circuit;
fig. 3 is a signal change simulation diagram showing a level conversion circuit including a separate resistance voltage division circuit;
FIG. 4 is a circuit schematic illustrating a level shifting circuit according to an embodiment of the present disclosure;
FIG. 5 is a signal variation simulation diagram illustrating a level shifting circuit according to an embodiment of the present disclosure; and is
Fig. 6 is a diagram showing a signal change simulation not including a clamp circuit level shifter circuit.
Detailed Description
Before proceeding with the following detailed description, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document. The terms "include" and "comprise," as well as derivatives thereof, mean inclusion without limitation. The term "or" is inclusive, meaning and/or. The phrase "associated with … …" and derivatives thereof means including, included within … …, interconnected, contained within … …, connected or connected with … …, coupled or coupled with … …, in communication with … …, mated, interwoven, juxtaposed, proximate, bound or bound with … …, having an attribute, having a relationship or having a relationship with … …, and the like. The term "controller" refers to any device, system, or part thereof that controls at least one operation. Such a controller may be implemented in hardware, or a combination of hardware and software and/or firmware. The functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. The phrase "at least one of, when used with a list of items, means that a different combination of one or more of the listed items can be used and only one item in the list may be required. For example, "at least one of A, B, C" includes any one of the following combinations: A. b, C, A and B, A and C, B and C, A and B and C.
Definitions for other specific words and phrases are provided throughout this patent document. Those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.
In this patent document, the application combination of transform blocks and the division levels of sub-transform blocks are only for illustration, and the application combination of transform blocks and the division levels of sub-transform blocks may have different manners without departing from the scope of the present disclosure.
Figures 1 through 6, discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged system or device.
Fig. 1 is a signal flow diagram showing a level conversion circuit for converting from a high level to a low level.
IN fig. 1, the devices IN the high-level logic circuit are, for example, high-voltage transistors with a voltage resistance of 3.6V, and generate a voltage signal CTRL _ IN to enter the logic level conversion circuit. The logic level conversion circuit generates a voltage signal CTRL _ OUT after performing high-to-low conversion on the level, and the voltage signal CTRL _ OUT enters a low-level logic circuit. The devices in the low-level logic circuit are low-voltage transistors with a withstand voltage of 1.8V, for example.
Fig. 2 is a diagram showing a level conversion circuit including a separate resistance voltage division circuit.
As shown in fig. 2, a level shift circuit for shifting from a high level to a low level, which is simple at present, generally performs level shift by means of resistance voltage division, and such a circuit includes voltage dividing resistors R1 and R2 connected in series, and further includes a parasitic capacitor Cp connected in parallel with the voltage dividing resistor R2. In this way, the voltage division accuracy is high, but when the values of the voltage division resistors R1 and R2 are selected to be small, the leakage current is large, and the power consumption of the circuit is increased; when the values of the voltage dividing resistors R1 and R2 are selected to be larger, the circuit area is increased, and the cost is increased. Meanwhile, the voltage jump speed can be limited by simply adopting resistance voltage division. For example, when it is necessary to drive a circuit with a large parasitic capacitor Cp, the level shift time may be long.
Fig. 3 is a signal change simulation diagram showing a level conversion circuit including a separate resistance voltage division circuit.
In fig. 3, simulation results of such a circuit configuration are shown. When the CTRL _ IN voltage jumps from 3.6V to 0V, the corresponding time for CTRL _ OUT to jump from 1.8V to 0V is long and can only jump to 1.5V for a short time. Thus, such circuits may experience bit errors at high speed level transitions.
Fig. 4 is a circuit schematic of a level shifting circuit according to an embodiment of the present disclosure.
In fig. 4, a level conversion circuit according to an embodiment of the present disclosure includes a voltage division circuit 101, an acceleration circuit 102, and a clamp protection circuit 103.
According to an embodiment of the present disclosure, the voltage dividing circuit 101 includes: resistors R11 and R21, voltage-dividing diodes D11, D12, D13, D21, D22 and D23. The input voltage CTRL _ IN enters the voltage dividing circuit 101 of the level shift circuit through the input node, wherein the diodes D11, D12, D13 and the diodes D21, D22, D23 are connected IN series between the input node and the ground node, and the 6 diodes are identical IN size, so that the CTRL _ IN is divided IN equal proportion. Resistors R11 and R21 may also be connected in series between D13 and D23 for voltage fine tuning, according to embodiments of the present disclosure. After being divided by the diode and the resistor in series, an output voltage is output from an output node between the resistor R11 and the resistor R21. According to an embodiment of the present disclosure, the level of the input voltage CTRL _ IN is 3.6V, and the level of the output voltage CTRL _ OUT is 1.8V.
The acceleration circuit 102 includes: a signal transfer capacitor C1, a bias resistor R1, and a PMOS transistor MP 1. The capacitor C1, the transistor MP1, and the resistor R1 together constitute an acceleration circuit of the level shift circuit. One end of the capacitor C1 is connected to the input node, and the other end is connected to the gate end of the MP 1; one end of the resistor R1 is connected to the output node, and the other end is connected to the gate end of the MP 1; transistor MP1 has a source connected to the output node and a drain connected to ground. In addition, the resistance of the bias resistor R1 is large (up to thousands of ohms or tens of kiloohms). When the transistor works normally, a direct current voltage signal is provided for the gate terminal of the MP1, so that the MP1 tube is turned off, and no electric leakage is generated. When the logic level is switched from high to low, the level of CTRL _ IN jumps from 3.6V to 0V, the capacitor C1 is connected between the input node and the gate terminal of MP1, so that the gate terminal of MP1 is pulled down rapidly IN a short time, MP1 is opened instantaneously, and the source terminal voltage of MP1 is pulled down to the ground IN an accelerated manner, i.e. the output voltage CTRL _ OUT of the level shift circuit jumps from 1.8V to 0 rapidly.
The clamp protection circuit 103 includes: a signal transfer capacitor C2, a bias resistor R2, a clamping diode D0 and an NMOS transistor MN 1.
The capacitor C2, the transistor MN1, the resistor R2 and the diode D0 jointly form a clamping protection circuit. One end of the capacitor C2 is connected with the gate end of the MP1, and the other end is connected with the gate end of the MN 1; one end of the resistor R2 is connected to the gate terminal of MN1, and the other end is grounded; the positive terminal of the diode D0 is grounded, and the negative terminal is connected to the gate terminal of the MN 1; the gate terminal of MN1 is connected with C2, R2 and D0, the drain terminal is connected with the gate terminal of MP1, and the source terminal is grounded. The resistor R2 is a bias resistor, and provides a dc voltage signal to the gate terminal of MN1 during normal operation, so that the MN1 transistor is turned off and no leakage occurs. When the logic level is switched from low to high, the level of CTRL _ IN jumps from 0V to 3.6V, and due to the introduction of the speed-up circuit, the output voltage CTRL _ OUT generates an up-skip pulse, which is momentarily larger than 1.8V, and thus may damage the transistor MP1 and the subsequent low-level logic circuit. After the clamp protection circuit is added, when the level is switched from low to high, the capacitor C2 is connected with the gate ends of the MP1 and the MN1, and the MN1 can generate a pull-down signal instantly when the gate end of the MP1 jumps over, so that a low-voltage transistor is prevented from being damaged. Because the capacitor C2 can also generate a coupling signal, the gate terminal of the MN1 can generate a negative voltage state, the positive terminal of the diode D0 is grounded, the negative terminal of the diode D0 is connected to the gate terminal of the MN1, the gate terminal of the MN1 is clamped, and the transistor MN1 is protected.
According to an embodiment of the present disclosure, the level shifter circuit may further include a parasitic capacitance Cp, which is an equivalent parasitic capacitance of an input terminal of the subsequent stage low level logic circuit that the CTRL _ OUT signal needs to drive.
According to the embodiment of the disclosure, after the CTRL _ IN signal is divided by the resistor and the diode, the high-level voltage of the dc operating point is changed from 3.6V to 1.8V.
Fig. 5 is a signal variation simulation diagram of a level shift circuit including a clamp circuit according to an embodiment of the present disclosure.
In fig. 5, simulation results of a level conversion circuit including a clamp circuit are shown. When the voltage signal CTRL _ IN generated by the high-level logic circuit jumps from high level 3.6V to low level 0V, the capacitor C1 is charged and discharged IN a transient state, and since the resistance of the bias resistor R1 is large, the gate terminal of the transistor MP1 is pulled down rapidly IN the transient state, that is, the output voltage CTRL _ OUT of the level shift circuit jumps from 1.8V to 0V rapidly. At this time, the NMOS transistor MN1 in the clamp protection circuit is in an off state, and does not affect the pull-down speed of the circuit.
When the output signal CTRL _ IN of the high-level logic circuit jumps from low level 0V to high level 3.6V, as shown by a reference point M3 IN fig. 5, the capacitor C2 is connected to the gate terminals of MP1 and MN1, and MN1 will generate a pull-down signal instantaneously when the gate terminal of MP1 jumps over, thereby preventing the low-voltage transistor from being damaged. Because the capacitor C2 can also generate a coupling signal, the gate terminal of the MN1 can generate a negative voltage state, the positive terminal of the diode D0 is grounded, the negative terminal of the diode D0 is connected to the gate terminal of the MN1, the gate terminal of the MN1 tube is clamped, and the transistor MN1 is protected. This achieves a fast response of the output signal CTRL _ OUT without overshoot when CTRL _ IN transitions from low to high.
Fig. 6 is a signal change simulation diagram showing a level conversion circuit including no clamp circuit.
In fig. 6, simulation results of a level conversion circuit including no clamp circuit are shown. When the output signal CTRL _ IN of the high-level logic circuit jumps from low level 0V to high level 3.6V, without the clamp protection circuit capacitor C2, the transistor MN1, the resistor R2, and the diode D0, when the logic level switches from low to high, the output voltage CTRL _ OUT will generate an up-jump to 2.1V due to the introduction of the speed-up circuit, as shown by the labeled point M0 IN fig. 6, and the voltage is momentarily greater than 1.8V. Since the level shift circuit and the subsequent low-level logic circuit both use low-voltage transistors, the voltage overshoot may damage the circuits.
The text and drawings are provided as examples only to aid in understanding the present disclosure. They should not be construed as limiting the scope of the disclosure in any way. While certain embodiments and examples have been provided, it will be apparent to those skilled in the art, based on the disclosure herein, that changes can be made in the embodiments and examples shown without departing from the scope of the disclosure.
The present disclosure generally provides a level shift circuit for shifting from a high level to a low level, which effectively reduces the chip area of the existing circuit without increasing additional power consumption, and simultaneously, an acceleration circuit and a clamp protection circuit are added to the level shift circuit, so as to achieve fast response of a logic level from high to low and from low to high, and prevent a low-voltage transistor in a rear-stage low-level logic chip from being damaged. The cascade application among chips with different levels in a multi-chip complex system is met.
Although the present disclosure has been described with exemplary embodiments, various changes and modifications may be suggested to one skilled in the art. The present disclosure is intended to embrace such alterations and modifications as fall within the scope of the appended claims.
None of the description in this specification should be read as implying that any particular element, step, or function is an essential element which must be included in the claim scope. The scope of patented subject matter is defined only by the claims.
Claims (12)
1. A level shifting circuit for shifting from a high level to a low level, the level shifting circuit comprising:
a voltage dividing circuit configured to divide an input voltage to output an output voltage from an output node;
a speed-up circuit configured to rapidly switch the output voltage on switching of the input voltage by rapidly switching a first transistor on through a first capacitor;
a clamp protection circuit configured to prevent the output voltage from jumping up when the input voltage switches.
2. The voltage conversion circuit of claim 1, wherein the voltage divider circuit comprises N voltage divider diodes connected in series between an input node receiving the input voltage and a ground node, where N is a natural number greater than or equal to 2.
3. The voltage conversion circuit of claim 2, wherein the voltage divider circuit further comprises M resistors connected in series into the N voltage divider diodes to fine tune the voltage divider circuit, wherein M is a natural number greater than or equal to 0.
4. The voltage conversion circuit of claim 3, wherein any one of the N voltage-dividing diodes and the M resistors serves as the output node.
5. The voltage conversion circuit according to claim 1, wherein one terminal of the first capacitor is connected to the input node, and the other terminal is connected to a gate terminal of the first transistor.
6. The voltage conversion circuit according to claim 1, wherein a source and a drain of the first transistor are connected to the output node and a ground node, respectively, and a gate thereof is connected to one end of the first capacitor.
7. The voltage conversion circuit of claim 1, wherein the speed-up circuit further comprises a first resistor connected between the output node and a gate terminal of the first transistor.
8. The voltage conversion circuit of claim 7, wherein a resistance value of the first resistor is greater than a first threshold.
9. The voltage conversion circuit of claim 1, wherein the clamp protection circuit comprises a second transistor and a second capacitor,
wherein the gate of the second transistor is connected to the gate of the first transistor through a second capacitor and is configured to generate a pull-down signal instantaneously when the gate of the first transistor overshoots when the level is switched from low to high.
10. The voltage conversion circuit of claim 9, wherein the clamp protection circuit further comprises a second resistor,
wherein the second resistor is connected between a gate of the second transistor and a ground node, and functions as a bias resistor to prevent leakage of current when the second transistor operates normally.
11. The voltage conversion circuit of claim 9, wherein the clamp protection circuit further comprises a clamp diode,
the positive end of the clamping diode is grounded, and the negative end of the clamping diode is connected to the grid electrode of the second transistor so as to clamp the grid electrode end of the second transistor.
12. The voltage conversion circuit of claim 1, wherein an equivalent parasitic capacitance for a subsequent stage low level logic circuit is further included between the output node and a ground node.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210016599.2A CN114362743A (en) | 2022-01-07 | 2022-01-07 | Level conversion circuit for converting from high level to low level |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210016599.2A CN114362743A (en) | 2022-01-07 | 2022-01-07 | Level conversion circuit for converting from high level to low level |
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| CN114362743A true CN114362743A (en) | 2022-04-15 |
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| CN202210016599.2A Pending CN114362743A (en) | 2022-01-07 | 2022-01-07 | Level conversion circuit for converting from high level to low level |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024109210A1 (en) * | 2022-11-21 | 2024-05-30 | 华润微集成电路(无锡)有限公司 | Logic level conversion circuit and system |
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- 2022-01-07 CN CN202210016599.2A patent/CN114362743A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024109210A1 (en) * | 2022-11-21 | 2024-05-30 | 华润微集成电路(无锡)有限公司 | Logic level conversion circuit and system |
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