CN113067575A

CN113067575A - Level shifter, integrated circuit including the same, and signal conversion method

Info

Publication number: CN113067575A
Application number: CN202110251770.3A
Authority: CN
Inventors: 林宛彦; 余宗欣
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2020-04-24
Filing date: 2021-03-08
Publication date: 2021-07-02
Also published as: US20240088897A1; TW202207631A

Abstract

A level shifter, an integrated circuit including the level shifter, and a signal conversion method are provided. The level shifter includes a transistor network and a self-timing circuit. The transistor network is configured to receive a signal at a first node in a first voltage domain and generate a corresponding signal at a second node in a second voltage domain during a transition period. The self-timing circuit is to receive a start signal based on a signal at a first node and to generate a voltage conversion accelerator signal to pull up a second node before expiration of a conversion period.

Description

Level shifter, integrated circuit including the same, and signal conversion method

Technical Field

The present disclosure relates generally to integrated circuit signal processing, and more particularly to an integrated circuit level shifter.

Background

The following are not uncommon: logic portions (e.g., logic cells) of an integrated circuit operate in a first voltage range (e.g., a low voltage domain, which may perform logic operations at low voltages to maximize power performance of the device, including extending battery life), and other portions (e.g., input/output cells) of the integrated circuit operate in a different voltage range, possibly a higher voltage (e.g., a high voltage domain, which uses a voltage range for proper interaction with circuitry external to the integrated circuit).

Disclosure of Invention

The present disclosure provides a level shifter including a transistor network and a self-timing circuit. The transistor network is configured to receive a signal at a first node in a first voltage domain and generate a corresponding signal at a second node in a second voltage domain during a transition period. The self-timing circuit is to receive a start signal based on a signal at a first node and to generate a voltage conversion accelerator signal, where the voltage conversion accelerator signal is to pull up a second node before a conversion period expires.

The present disclosure further provides a method for converting a signal from a first voltage domain to a second voltage domain, comprising: receiving a signal at a first node of a transistor network in a first voltage domain and generating a corresponding signal at a second node in a second voltage domain for a transition period; providing a start signal to a self-timing circuit based on a signal at a first node; and generating a voltage conversion accelerator signal using the self-timing circuit, wherein the voltage conversion accelerator signal is used to pull up the second node before the conversion period expires.

The present disclosure further provides an integrated circuit including a logic circuit, an input/output circuit, and a level shifter. The logic circuit is used for operating in a first voltage domain. The input/output circuit is configured to operate in a second voltage domain, wherein the second voltage domain has a higher maximum voltage than the first voltage domain. The level shifter includes a transistor network and a self-timing circuit. The transistor network is configured to receive a signal at a first node in a first voltage domain and generate a corresponding signal at a second node in a second voltage domain during a transition period. The self-timing circuit is to receive a start signal based on a signal at a first node and to generate a voltage conversion accelerator signal, where the voltage conversion accelerator signal is to pull up a second node before a conversion period expires.

Drawings

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the features are not drawn to scale in accordance with standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a schematic diagram of a series of level shifters according to some embodiments;

FIG. 2 is a schematic diagram of an integrated circuit utilizing multiple level shifters to convert a signal from a reference voltage domain to an input-output voltage domain in accordance with some embodiments;

FIG. 3 is a block diagram of a level shifter responsive to a self-timing circuit to shift a signal from a first voltage level to a second voltage level, in accordance with some embodiments;

FIG. 4 is a block diagram of exemplary details of a level shifter responsive to a self-timing circuit, according to some embodiments;

FIG. 5 is a schematic diagram of the logical operation of generating a voltage translation accelerator signal according to some embodiments;

FIG. 6 is a schematic diagram of a level shifter according to one embodiment;

FIG. 7 is a schematic diagram of a level shifter according to another embodiment;

FIG. 8 is a schematic diagram of a self-timing circuit that is disabled during a pull-down operation according to an embodiment;

fig. 9 is a flow diagram of a method of converting a signal from a first voltage domain to a second voltage domain according to an embodiment.

[ notation ] to show

102 integrated circuit

104 core logic

106 output/output circuit

108,110,112,302,402,602,702 level shifter

202 high side logic

204 low side logic

304,306,404,406,502,504,620,624,740,744,802 self-timing circuit

408,412,604,606,608,610,612,614,616,618,622,626,704,706,708,710,712,714,716,718,720,722,724,726,728,732,734,736,742,746,M_NA,M_NB,MN_pull,M_P1,M_PA,M_PB,MP_pullTransistor

410,414, C, D start signal

719,721,804,A,A1,A2,A₁,A₂,A_NNode B, B1, B2, Z, ZN

730,738,806 logic circuit

902,904,906 steps

BB3D Voltage conversion Accelerator Signal

I, IN, Q, QN, ZQ, ZQB signals

N_ctrl,P_ctrlControl signal

VDD, VDDA, VDDB, VDDN, VSS, VSSA, VSSB, VSSN voltage

Δ Vp, Δ Vn, trans-pressure

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

As previously mentioned, it is not uncommon for logic portions (e.g., logic cells) of an integrated circuit to operate in a first voltage domain and other portions (e.g., input/output portions) of the integrated circuit to operate in different voltage domains. The present disclosure describes systems and methods associated with level shifting devices (level shifting devices), some embodiments having self-timing circuit portions for protecting the level shifting circuits from damage while also improving the speed of level shifting operations. The level shifter includes an overdrive level shifter that shifts the signal to a voltage domain with a signal separation greater than the transistor rating (e.g., 0V to 1.8V domain using 1.2V rated transistors). A level shifter provides signal level conversion between the voltage domains. For example, the level shifter may be used to convert a low voltage domain signal representing the logic cell output to a high voltage domain signal output from the integrated circuit so that the output signal can be sensed by the connected external circuitry. Alternatively, the level shifter may be used to convert a high voltage domain input signal of the integrated circuit into a low voltage domain of the logic cell so as not to damage the logic cell. However, level shifters introduce a potential bottleneck in the integrated circuits, wherein the latency of the level shifter implementation limits the speed of operation (e.g., integrated circuit I/O operations may be limited by the level switching speed). Also, efforts to speed up the operation of the level shifter may result in circuit damaging voltage overshoots.

FIG. 1 is a schematic diagram of a series of level shifters including a self-timed level shifter at a second level according to some embodiments. Integrated circuit 102 includes core logic 104, and core logic 104 performs basic functions of integrated circuit 102, such as receiving data, processing the data, and outputting resultant data. The core logic 104 operates in a reference voltage domain, where the high voltage in the reference voltage domain is VDD and the low voltage is VSS. Although core logic 104 typically operates at a low voltage level (e.g., a reference voltage domain of 0.0V to 0.5V), other circuits of integrated circuit 102 may operate at a higher voltage level. For example, the output/output circuit 106 interfacing with external components of the integrated circuit 102 may operate in a higher voltage domain (e.g., a high voltage domain of 0.0V to 1.8V). The higher voltage domain may help meet external circuit specifications or may help mitigate the effects of signal attenuation during data transmission of the integrated circuit 102 through the output/output circuit 106.

Level shifters I108, II 110,. and N112 are used to convert signals from the reference voltage domain of core logic 104 to the high voltage domain of I/O circuitry 106, or alternatively, to convert signals from the high voltage domain of I/O circuitry 106 to the reference voltage domain of core logic 104. In some embodiments, such conversion is performed in multiple steps. A multistage level shifter is particularly useful when the voltage width of the input/output circuit (e.g., 1.8V-0.0V — 1.8V) is greater than the rated value of the transistors in the level shifters 108,110,112 (e.g., the transistors are rated at a maximum of 1.2V). The use of transistors having relatively low voltage ratings to produce transitions from or to high voltage width voltage domains is referred to herein as level shifters to overdrive. In some embodiments, this is accomplished by operating each level shifter 108,110,112 over an intermediate voltage domain having a voltage width that is no greater than the nominal voltage of the transistor (e.g., high voltage VDDA-low voltage VSSA < 1.2V; high voltage VDDB-low voltage VSSB < 1.2V; high voltage VDDN-low voltage VSSN <1.2V), where the high-side logic and the low-side logic can provide appropriately spaced high-voltage domain signals at input/output circuit 106.

In some embodiments, one or more of the level shifters 108,110,112 may be self-timed level shifters. The self-timed level shifter includes a self-timing module to supplement pull-up operations on certain target nodes within the level shifter to expedite the operations. The level shifter may become a bottleneck for input/output operations of the integrated circuit, and the level shifter experiences performance degradation (e.g., in some cases, such as-40 degrees celsius or less, and further, such as in excess of +125 degrees celsius), the self-timing module may alleviate the problem of input/output performance degradation.

FIG. 2 is a schematic diagram of an integrated circuit 102 utilizing multiple level shifters to convert a signal from a reference voltage domain to an input-output voltage domain in accordance with some embodiments. The integrated circuit 102 includes core logic 104, the core logic 104 operating in a reference voltage domain (VDD VSS). The first set of level shifters 108 is used to convert the signal from the reference voltage domain to the first voltage domain (VDDA VSSA, e.g., 1.2V 0.0V). The level shifter II 110 is used to convert the signal from the first voltage domain to the second voltage domain (VDDB-VSSB, e.g., 3.0V-1.8V). The high side logic 202 and the low side logic 204 are configured to interface between the input/output circuit 106 (e.g., a post driver and an input/output pad (pad)), wherein the input/output circuit 106 operates in a high voltage domain (VDDB VSS, e.g., 3.0V 0.0V). The high side logic 202 is configured to apply a high voltage level (VDDB) of the high voltage domain to the input/output circuit 106 when a high voltage signal is output to the pad. The low side logic 204 is configured to apply a high voltage domain low voltage level (VSS) to the input/output circuit 106 when a low voltage signal is output to the pad. In the embodiment of FIG. 2, the level shifter II 110 includes a self-timing block (as indicated in FIG. 1 by the dashed outline) to improve performance speed while minimizing voltage overshoot that may damage the transistors of the level shifter II 110.

FIG. 3 is a block diagram of a level shifter 302, according to some embodiments, the level shifter 302 responsive to a self-timing circuit to shift a signal from a first voltage level to a second voltage level. The level shifter 302 receives the differential input signal I, IN in the first voltage domain and converts (shifts) the input signal I, IN to the second voltage domain to output the output signal Q, QN. For example, IN a first voltage domain (VDD-VSS), a rising signal is received at input signal I and a corresponding falling signal is received at input signal IN; on the other hand, in the second voltage domain (VDDA VSSA), the level shifter 302 provides a rising signal transition at the output signal Q and a falling signal transition at the output signal QN. To speed up the generation of the output at the output signal Q, QN of the second voltage domain, the self-timing circuit a 304, the self-timing circuit B306 provide a voltage transformation accelerator signal (voltage transformation accelerator signals) to pull up a particular circuit node within the level shifter that will rise faster than it would otherwise be charged (e.g., a node within the level shifter that is charged based on a signal at the input signal I, IN or at another node). For example, when the input signal I rises, the self-timing circuit a 304 accelerates the pull-up of the node, which helps generate a corresponding rising signal at the output signal Q. Also, when the input signal IN rises, the self-timing circuit B306 accelerates the pull-up of the node, which helps generate a corresponding rising signal at the output signal QN, as further described herein.

Fig. 4 is a block diagram of exemplary details of a level shifter 402 responsive to a self-timing circuit, according to some embodiments. Level shift of FIG. 4The bit cell 402 converts the signal from the first voltage domain (VDDA VSSA) to the second voltage domain (VDDB VSSB). Transistor (M) of level shifter 402_PA、M_NA、M_PB、M_NB) Rated voltage of not more than V_Rated(e.g., V)_Rated1.2V), wherein the difference between the maximum voltage of the second voltage domain and the minimum voltage of the first voltage domain is close to or larger than V_Rated(e.g., VDDB-VDDA 3.0V-1.2V 1.8V>V_Rated1.2V). The level shifter 402 is responsive to self-timing circuits A404, B406. the self-timing circuits A404, B406 provide voltage conversion accelerator signals to pull up specific circuit nodes within the level shifter that will rise faster than if they were charged differently, transistor M_PA、M_NA、M_PB、M_NBIs dimensioned (e.g. transistor M)_PARelative to the transistor M_NAIn the illustration of FIG. 4, transistor M_PAIs about transistor M_NA1/4 for the size of (d); also for example, transistor M_PARelative to the transistor M_PBIn the example of fig. 7, the transistor 716 is about 1/4 the size of the transistor 718) to avoid overshoot that causes damage to the transistors within the level shifter 402 (e.g., cross voltages Δ Vp, Δ Vn)>V_Rated)。

Specifically, IN the example of fig. 4, node a is charged high and node B is pulled down when input signal I undergoes a rising transition and input signal IN undergoes a corresponding falling transition, where node B pull down will typically be faster than node a charge high. Specifically, the node B is charged by turning on the first charging transistor 408 through a first start signal 410, which is the maximum value of the voltage of the node B and the low voltage VSSB, expressed as Max (B, VSSB), wherein the first start signal 410 is pulled down when the node B is pulled down by the input signal IN. The conduction of the first start signal 410 causes current to flow from the voltage source (VDDB) to the output node Z and node a. Node a supports a high voltage at output node Z, and to accelerate the charging of node a, the self-timing circuit a 404 receives the first start signal 410 and provides a voltage conversion accelerator signal to node a to accelerate the pull-up of node a (i.e., the pull-up speed of node a is faster than otherwise would be possible without using the self-timing circuit a 404 to pull-up node a).

Conversely, when the input signal IN undergoes a rising transition and the input signal I undergoes a corresponding falling transition, node B is charged high and node a is pulled down, wherein node a will typically be charged higher than node B. Specifically, the node A is charged by turning on the second charge transistor 412 via the second start signal 414 (which is the maximum of the voltage of the node A and the low voltage VSSB, expressed as Max (A, VSSB)), wherein the second start signal 414 is pulled down when the node A is pulled down by the input signal I. Conduction of the second start signal 414 causes current to flow from the voltage source (VDDB) to the output node ZN and node B. To accelerate the charging of node B, the self-timing circuit B406 receives the second start signal 414 and provides a voltage conversion accelerator signal to node B to accelerate the pull-up of node B.

In the illustration of FIG. 4, the level shifter 402 comprises a network of transistors (

transistors

408, 412, M)_PA、M_NA、M_PB、M_NB) The transistor network is configured to receive a signal at a first node IN a first voltage domain (e.g., a falling transition at the input signal IN) and generate a corresponding signal at a second node IN a second voltage domain (e.g., a rising transition at the node a) during a transition period. The self-timing circuit 404 is configured to receive a start signal (start signal 410) based on a signal at a first node (e.g., pull down node B via input signal IN) and generate a voltage conversion accelerator signal (from the self-timing circuit 404 to node a), wherein the voltage conversion accelerator signal is configured to pull up a second node (node a) prior to expiration of a conversion period to accelerate generation of a corresponding signal at the second node (e.g., the pull-up of node a may be faster than the pull-up of the voltage conversion accelerator signal without the use of the self-timing circuit 404). In the illustration of fig. 4, the level shifter 402 also includes transistors 416, 418.

In one illustration, the transistor network is further configured to receive a signal (e.g., a falling transition at the input signal I) at a third node in the first voltage domain and generate a corresponding signal (e.g., a rising transition at the node B) at a fourth node in the second voltage domain. The second self-timing circuit 406 is configured to receive a second start signal (start signal 414) based on a signal at a third node (e.g., pull down node a through input signal I) and generate a second voltage conversion accelerator signal (from the second self-timing circuit 406 to node B), wherein the voltage conversion accelerator signal is configured to pull up a fourth node (node B).

FIG. 5 is a schematic diagram of the logical operation of generating a voltage translation accelerator signal, according to some embodiments. In a first example, the self-timing circuit 502 receives one or more signals (node A) from other locations of the level shifter₁、A₂、...、A_NThe signal of (d). Logic operation decision control transistor MP in self-timing circuit 502_pullControl signal P of_ctrlThe state of (1). In the first example, the control signal P is at a low level_ctrlConducting transistor MP_pullCausing current to flow from voltage source VDDB to the pull-up node.

In a second example, the self-timing circuit 504 receives one or more signals (node A) from other locations of the level shifter₁、A₂、...、A_NThe signal of (d). Logic operation decision control transistor MN in self-timing circuit 504_pullControl signal N_ctrlThe state of (1). In the second example, the control signal N is at a high level_ctrlConducting transistor MN_pullCausing current to flow from the node to ground, pulling the node down. In the first and second examples described above, the logic operation of the self-timing circuits 504 and 506 may be modified to generate accelerator signals to assist in desired circuit operation (e.g., accelerate the pull-up or pull-down of a particular node).

Fig. 6 is a schematic diagram of a level shifter 602 according to an embodiment. The level shifter 602 includes a transistor network (

transistors

604, 606,. and.618) for receiving an input signal IN at a first node IN a first voltage domain and for receiving an input signal I at a third node IN the first voltage domain, and for shifting the input signal IN and the input signal I to a second voltage domain. The level shifter 602 includes a first circuit path from the input signal I, through the first transistor 606 and the second transistor 610, to the output node Z, where the second node a is between the first transistor 606 and the second transistor 610. The level shifter 602 includes a second circuit path from the input signal IN, through the third transistor 604 and the fourth transistor 608, to the output node ZN, where the fourth node B is between the third transistor 604 and the fourth transistor 608. The first control sub-circuit includes a transistor 612 and a transistor 614 controlled by a first start signal B1, wherein a low level signal at the first start signal B1 is used to pull up the output node Z and the second node A, wherein. The first start signal B1 is set to Max (B, VSSB). The second control sub-circuit includes a transistor 616 and a transistor 618 controlled by a second start signal A1, wherein a low signal at the second start signal A1 is used to pull up the output node ZN and the fourth node B. The second start signal a1 is set to Max (a, VSSB).

The first self-timing circuit 620 is configured to receive the first start signal (B1) and the signal at the output node ZN, and generate the voltage conversion accelerator signal (signal at node a 2) to pull up the second node a before a time period that it would take for the transistor network (

transistors

604, 606,.., 618) to pull up the second node a without the first self-timing circuit 620 accelerating the generation of the signal at the second node a. Specifically, the logical operation of the gates (evaluates) at the first self-timing circuit 620! The NAND of ZN | B1 (i.e., the complement of the signal at output node ZN (|)) and first start signal B1 provides a voltage conversion accelerator signal to node pull-up transistor 622, which is used to discharge current to second node a to accelerate charging of second node a and its corresponding output node Z.

The second self-timing circuit 624 is configured to receive the second start signal (a1) and the signal at the output node Z, and generate the second voltage conversion accelerator signal (the signal at node B2) to pull up the fourth node B before a time period that it would take for the transistor network (

transistors

604, 606,..., 618) to pull up the fourth node B without the second self-timing circuit 624 accelerating the generation of the signal at the fourth node B. Specifically, the logic operation is operated by the logic gate at the second self-timing circuit 624! Z | a1 to provide a second voltage conversion accelerator signal to node pull-up transistor 626, which is used to discharge current to fourth node B to accelerate charging of fourth node B and its corresponding output node ZN.

IN an exemplary operation, the third node at the input signal I receives the up-conversion signal and the first node at the output signal IN receives the down-conversion signal. The transistor network (

transistors

604, 606,.. 618) is used to generate a corresponding signal (rising signal) at the second node a for a transition period of time (e.g., 0.5 nanoseconds (ns)). The pull-down signal at the first node at the input signal IN is used to pull down the fourth node B. Whether the first start signal (B1) is pulled down is determined based on the arithmetic expression Max (B, VSSB), wherein the fourth node B is pulled down toward the voltage source VSSA based on the logical arithmetic expression A2! ZN | B1 to change the output of the logic function at node a2 in the first timing circuit 420 to a low level. The low first voltage transition accelerator signal turns on the node pull-up transistor 622, causing current to flow to the second node A, thereby accelerating the transition from low to high at the second node A (and corresponding output node Z) (e.g., the transition time is 0.2ns instead of 0.5ns without the first self-timing circuit 620). Based on the second node A transitioning to a high level, it is determined whether to pull up the second start signal (A1) based on the operation expression Max (A, VSSB), which controls the second control sub-circuits 616 and 618 to pull down the output node ZN.

Fig. 7 is a schematic diagram of a level shifter 702 according to another embodiment. The level shifter 702 includes a transistor network (

transistors

704, 706,. and 722) for receiving an input signal I at a first node IN a first voltage domain and an input signal IN at a third node IN the first voltage domain, and for shifting the input signal I and the input signal IN to a second voltage domain. The level shifter 702 includes a first circuit path from the input signal I, through

transistors

704, 706, 708, 718, 716 to the output node Z, where the second node 719 is between the

transistors

716 and 718. The level shifter 702 includes a second circuit path from the input signal IN, through the

transistors

710, 712, 714, 722, 720, to the output node ZN, wherein a fourth node 721 is between the

transistors

720 and 722. The first control sub-circuit comprises

transistors

724, 726, 728 controlled by a first start signal D, wherein a low signal at the first start signal D is used to pull up the output node Z and the second node 719. Wherein the first start signal D is set to Max (B, VSSB) at the logic circuit 730. The second control sub-circuit includes

transistors

732, 734, 736 controlled by a second start signal C, wherein a low level signal at the second start signal C is used to pull up the output node ZN and the fourth node 721. The second start signal C is set to Max (a, VSSB) at the logic circuit 738.

The first self-timing circuit 740 is configured to receive the first start signal (D) and the signal at the output node ZN, and generate the voltage conversion accelerator signal to pull up the second node 719 before a time period that it would take for the transistor network (

transistors

704, 706,.., 722) to pull up the second node 719 without the first self-timing circuit 740 accelerating the generation of the signal at the second node 719. Specifically, the logic operation formula is operated by the logic gate at the first self-timing circuit 740! D | ZN to provide a voltage conversion accelerator signal to the node pull-up transistor 742, which is used to discharge current to the second node 719 to accelerate charging of the second node 719 and its corresponding output node Z.

The second self-timing circuit 744 is configured to receive the second start signal (C) and the signal at the output node Z, and generate the second voltage conversion accelerator signal to pull up the fourth node 721 before a time period that it would take for the transistor network (

transistors

704, 706,.., 722) to pull up the fourth node 721 without the second self-timing circuit 744 accelerating the generation of the signal at the fourth node 721. Specifically, the logic operation is operated by the logic gate at the second self-timing circuit 744! C | Z to provide a second voltage converting accelerator signal to node pull-up transistor 746, which is used to discharge current to fourth node 721 to accelerate charging of fourth node 721 and its corresponding output node ZN.

transistors

704, 706,. and 722) is used to generate a corresponding rising transition signal at the second node 719. The pull-down signal at the first node at the input signal IN is used to pull down the fourth node 721. Whether or not to pull down the first start signal (D) is determined based on the operation Max (B, VSSB) at the logic circuit 738, which is based on the logic operation! D | ZN to change the output of the logic function at the first timing circuit 740 to a low level. The low first voltage transition accelerator signal turns on the node pull-up transistor 742, causing current to flow to the second node 719, thereby accelerating the transition from low to high at the second node 719 (and corresponding output node Z). Based on the second node a transitioning to a high level, it is determined whether to pull up the second start signal (C) that controls the

transistors

732, 734, 736 of the second control sub-circuit to pull down the output node ZN based on the operational expression Max (a, VSSB).

As described above, the pull-down operation within the level shifter may be faster than the pull-up operation, which in embodiments contributes to the improvement provided by the self-timing circuit described herein. And in some embodiments the use of self-timing circuitry during pull-down operations can result in temporary shorts, causing undesirable power consumption. Fig. 8 is a schematic diagram of a self-timing circuit 802 that is disabled during a pull-down operation according to an embodiment. Specifically, self-timing circuit 802 generates voltage-translated accelerator signal BB3D, which voltage-translated accelerator signal BB3D controls node pull-up transistor M_P1Node pull-up transistor M_P1A current may be provided to node 804. Because the node 804 is generally capable of switching fast enough when the node 804 and corresponding output node Z are pulled down so that the operation does not become a bottleneck for the performance of the level shifter, and because temporary shorting from VDDB to VSSB during such pull down switching may cause undesirable power consumption, the self-timing circuit 802 is used to generate a voltage conversion accelerator signal based on the input signal ZQNumber BB3D, wherein the input signal ZQ is used to disable the node pull-up transistor M during the pull-down operation of the node 804_P1. Specifically, the logic circuit 806 includes an SR latch (SR-latch) for storing the final states of the output nodes Z and ZN to output the signals ZQ and ZQB, respectively. When the final state of the output node Z is high, the logic circuit 806 disables the node pull-up transistor M by causing the voltage conversion accelerator signal to remain high_P1。

Fig. 9 is a flow diagram of a method of converting a signal from a first voltage domain to a second voltage domain according to an embodiment. Although the flow chart is described with reference to the above structure, it should be understood that the method of fig. 9 is applicable to many other structures. The method of FIG. 9 includes step 902: receiving a signal at a first node (node at the input signal IN) of a transistor network (

transistors

604, 606, 608, 610, 612, 614, 616, 618) IN a first voltage domain (VDDA-VSSA) and generating a corresponding signal at a second node (node a) IN a second voltage domain (VDDB-VSSB) during a transition period; step 904: providing a start signal (B1) to a self-timing circuit (620) based on a signal at a first node (from a node at an input signal IN to node B); and step 906: a self-timing circuit (620) is used to generate a voltage conversion accelerator signal (signal at node a 2), wherein the voltage conversion accelerator signal (signal at node a 2) is used to pull up the second node before the expiration of the conversion period to accelerate generation of the corresponding signal at the second node (node a).

The use of various processes as described herein may provide a number of advantages. For example, the subject matter herein may use sized transistors to provide high speed level shifter operation without causing voltage overshoot to avoid damage to the level shifter transistors due to voltage overshoot.

According to aspects of the present disclosure, a level shifter is disclosed that includes a transistor network and a self-timing circuit. The transistor network is configured to receive a signal at a first node in a first voltage domain and generate a corresponding signal at a second node in a second voltage domain during a transition period. The self-timing circuit is to receive a start signal based on a signal at a first node and to generate a voltage conversion accelerator signal, where the voltage conversion accelerator signal is to pull up a second node before a conversion period expires. In some embodiments, the self-timing circuit includes a logic gate that determines when to generate the voltage conversion accelerator signal. In some embodiments, the transistor network is to receive a signal at a third node in the first voltage domain and to generate a corresponding signal at a fourth node in the second voltage domain; the second self-timing circuit receives a second start signal based on a signal at the third node and generates a second voltage conversion accelerator signal that is used to pull up the fourth node. In some embodiments, the level shifter is an overdrive level shifter, the transistor network is rated to a nominal voltage, and a difference between a maximum voltage and a minimum voltage in the second voltage domain is greater than the nominal voltage. In some embodiments, the first circuit path includes a first transistor and a second transistor, the second node is between the first transistor and the second transistor, and a size of the first transistor is relative to a size of the second transistor to prevent a voltage across the first transistor from overshooting a threshold amount during the level shift operation. In some embodiments, the self-timing circuit generates the voltage conversion accelerator signal based on the start signal and the output node signal level. In some embodiments, the start signal is based on the signal at the first node and a reference voltage of the level shifter. In some embodiments, the reference voltage of the level shifter is a low voltage higher than the first voltage domain. In some embodiments, the voltage conversion accelerator signal controls a node pull-up transistor that discharges current to the second node based on the voltage conversion accelerator signal. In some embodiments, an output node is associated with the second node, and a self-timing circuit is used to disable the node pull-up transistor when the output node transitions from a low level to a high level.

According to some other aspects of the present disclosure, a method of converting a signal from a first voltage domain to a second voltage domain is disclosed, comprising: receiving a signal at a first node of a transistor network in a first voltage domain and generating a corresponding signal at a second node in a second voltage domain for a transition period; providing a start signal to a self-timing circuit based on a signal at a first node; and generating a voltage conversion accelerator signal using the self-timing circuit, wherein the voltage conversion accelerator signal is used to pull up the second node before the conversion period expires. In some embodiments, the method further comprises: receiving a signal at a third node in the first voltage domain and generating a corresponding signal at a fourth node in the second voltage domain; and generating a second voltage conversion accelerator signal using a second self-timing circuit, the second voltage conversion accelerator signal to pull up the fourth node. In some embodiments, the first node is located in a first level shift path, the first level shift path including a series of a plurality of transistors between the first node and the first output node, the fourth node also being located in the first level shift path; the third node is located in a second level shift path that includes a second series of a plurality of transistors between a second node, which is also located in the second level shift path, and a second output node. In some embodiments, when the first node is switched from a high level to a low level, the fourth node is pulled down through a transistor on the first level switching path; the control node is shifted to a low level based on the fourth node being pulled down, and the start signal is shifted to a low level based on the control node. In some embodiments, the voltage conversion accelerator signal is generated based on the start signal and a voltage at the first output node. In some embodiments, the control node selects a reference voltage or a voltage at the fourth node for the second voltage domain. In some embodiments, the node pull-up transistor is disabled when an output node associated with the second node transitions from a low level to a high level.

According to yet other aspects of the present disclosure, an integrated circuit is disclosed that includes logic circuitry, input/output circuitry, and a level shifter. The logic circuit is used for operating in a first voltage domain. The input/output circuit is configured to operate in a second voltage domain, wherein the second voltage domain has a higher maximum voltage than the first voltage domain. The level shifter includes a transistor network and a self-timing circuit. The transistor network is configured to receive a signal at a first node in a first voltage domain and generate a corresponding signal at a second node in a second voltage domain during a transition period. The self-timing circuit is to receive a start signal based on a signal at a first node and to generate a voltage conversion accelerator signal, where the voltage conversion accelerator signal is to pull up a second node before a conversion period expires. In some embodiments, the level shifter further comprises a high side logic element to select a maximum voltage or a minimum voltage of the second voltage domain and to apply the selected maximum voltage or minimum voltage of the second voltage domain to the output line, a difference between the maximum voltage and the minimum voltage of the second voltage domain being greater than a voltage rating of a plurality of transistors in the transistor network. In some embodiments, the logic circuit includes a first level shifter before the level shifter, the first level shifter to convert the plurality of signals from the reference voltage domain to the first voltage domain.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A level shifter, comprising:

a transistor network for receiving a signal at a first node in a first voltage domain and generating a corresponding signal at a second node in a second voltage domain for a transition period; and

a self-timing circuit to receive a start signal based on the signal at the first node and to generate a voltage transition accelerator signal, wherein the voltage transition accelerator signal is to pull up the second node before the transition period expires.

2. The level shifter of claim 1, wherein the self-timing circuit comprises a logic gate, wherein the logic gate determines when to generate the voltage translation accelerator signal.

3. The level shifter of claim 1,

wherein the transistor network is configured to receive a signal at a third node in the first voltage domain and to generate a corresponding signal at a fourth node in the second voltage domain;

wherein a second self-timing circuit receives a second start signal based on the signal at the third node and generates a second voltage conversion accelerator signal, wherein the second voltage conversion accelerator signal is used to pull up the fourth node.

4. The level shifter of claim 1, wherein the level shifter is an overdrive level shifter, wherein the transistor network is rated to a rated voltage, wherein a difference between a maximum voltage and a minimum voltage in the second voltage domain is greater than the rated voltage.

5. The level shifter of claim 1, wherein a first circuit path comprises a first transistor and a second transistor, wherein the second node is between the first transistor and the second transistor, wherein a size of the first transistor is relative to a size of the second transistor to prevent voltage overshoot of the first transistor by more than a threshold amount during a level shifting operation.

6. A method of converting a signal from a first voltage domain to a second voltage domain, comprising:

receiving a signal at a first node of a transistor network in the first voltage domain and generating a corresponding signal at a second node in the second voltage domain for a transition period;

providing a start signal to a self-timing circuit based on the signal at the first node; and

generating a voltage transition accelerator signal using the self-timing circuit, wherein the voltage transition accelerator signal is configured to pull up the second node before the transition time period expires.

7. The method of claim 6, further comprising:

receiving a signal at a third node in the first voltage domain and generating a corresponding signal at a fourth node in the second voltage domain; and

a second self-timing circuit is used to generate a second voltage conversion accelerator signal, wherein the second voltage conversion accelerator signal is used to pull up the fourth node.

8. The method of claim 7,

wherein the first node is in a first level shift path, wherein the first level shift path includes a series of transistors between the first node and a first output node, wherein the fourth node is also in the first level shift path;

wherein the third node is located in a second level shift path, wherein the second level shift path includes a second series of transistors between the second node and a second output node, wherein the second node is also located in the second level shift path.

9. The method of claim 8,

wherein when the first node is switched from high level to low level, the fourth node is pulled down through a transistor on the first level switching path;

wherein a control node is shifted to a low level based on the fourth node being pulled down, wherein the start signal is shifted to a low level based on the control node.

10. An integrated circuit, comprising:

a logic circuit for operating in a first voltage domain;

an input/output circuit for operating in a second voltage domain, wherein the second voltage domain has a higher maximum voltage than the first voltage domain; and

a level shifter comprising:

a transistor network for receiving a signal at a first node in the first voltage domain and generating a corresponding signal at a second node in the second voltage domain for a transition period; and