CN114362482B

CN114362482B - Pin input circuit and chip

Info

Publication number: CN114362482B
Application number: CN202210149402.2A
Authority: CN
Inventors: 马继荣
Original assignee: Beijing Unigroup Tsingteng Microsystems Co Ltd
Current assignee: Beijing Unigroup Tsingteng Microsystems Co Ltd
Priority date: 2022-02-18
Filing date: 2022-02-18
Publication date: 2023-07-18
Anticipated expiration: 2042-02-18
Also published as: CN114362482A

Abstract

The application relates to the technical field of integrated circuit design and discloses a pin input circuit. The clock signal is provided through the clock port connection clock signal, the buffered clock signal is provided for the clock port of the chip through the buffer, a circuit between the clock port and the power input end of the chip is conducted through the first capacitor connected with the clock port and the first switch module connected with the power input end of the chip, and a circuit between the clock port and the power output end of the chip is conducted through the second capacitor connected with the clock port and the second switch module connected with the power output end of the chip, so that voltage drop on an inductor equivalent to wire bonding of the power input end and the power output end can be reduced under the condition that the pin input circuit is applied to the chip, and power disturbance caused by the inductor equivalent to wire bonding of the power input end and the power output end is reduced. The application also discloses a chip.

Description

Pin input circuit and chip

Technical Field

The present disclosure relates to the field of integrated circuit design, and for example, to a pin input circuit and a chip.

Background

Currently, with the development of integrated circuit design technology, the application range of chips is becoming wider and wider. In the case of a chip running the program code of the electronic device system, the average current through the power pins of the chip will be larger and larger as the instantaneous power consumption of the electronic device system increases. The average current, in the case of a wire-bonding equivalent inductance through the power pins of the chip, can cause a large disturbance on the power pins of the chip.

In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art: the power supply disturbance of the power supply pins of the chip cannot be reduced in the prior art.

Disclosure of Invention

The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview, and is intended to neither identify key/critical elements nor delineate the scope of such embodiments, but is intended as a prelude to the more detailed description that follows.

The embodiment of the disclosure provides a pin input circuit and a chip, so as to reduce power supply disturbance of a power supply pin of the chip.

In some embodiments, the pin-in circuit comprises: a clock port for providing a clock signal to the first capacitor, the second capacitor and the buffer; the first input end of the first capacitor is connected with the clock port, the second output end of the second capacitor and the fifth input end of the buffer respectively, and the first output end of the first capacitor is connected with the third input end of the first switch module; the first capacitor is used for providing voltage for a third input end of the first switch module so as to trigger the first switch module to be conducted; the second output end of the second capacitor is connected with the clock port, the first input end of the first capacitor and the fifth input end of the buffer respectively, and the second input end of the second capacitor is connected with the fourth output end of the second switch module; the second capacitor is used for providing voltage for a fourth output end of the second switch module so as to trigger the second switch module to be conducted; the third input end of the first switch module is connected with the first output end of the first capacitor, and the third output end of the first switch module is connected with the power input end of the chip; the first switch module is used for conducting a circuit between the clock port and the power input end of the chip; the fourth input end of the second switch module is connected with the power supply output end of the chip; the second switch module is used for conducting a circuit between the clock port and the power output end of the chip; the fifth input end of the buffer is respectively connected with the clock port, the first input end of the first capacitor and the second output end of the second capacitor, and the fifth output end of the buffer is connected with the clock port of the chip; the buffer is used for buffering the clock signal and providing the buffered clock signal to the clock port of the chip.

In some embodiments, the chip includes a clock port, a power input, a power output, and the pin-in circuits described above.

The pin input circuit and the chip provided by the embodiment of the disclosure can realize the following technical effects: the clock signal is provided through the clock port connection clock signal, the buffered clock signal is provided for the clock port of the chip through the buffer, a circuit between the clock port and the power input end of the chip is conducted through the first capacitor connected with the clock port and the first switch module connected with the power input end of the chip, and a circuit between the clock port and the power output end of the chip is conducted through the second capacitor connected with the clock port and the second switch module connected with the power output end of the chip, so that voltage drop on an inductor equivalent to wire bonding of the power input end and the power output end can be reduced under the condition that the pin input circuit is applied to the chip, and power disturbance caused by the inductor equivalent to wire bonding of the power input end and the power output end is reduced.

The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which like reference numerals refer to similar elements, and in which:

FIG. 1 is a schematic diagram of a first pin-in circuit provided in an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a second pin-in circuit provided in an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a third pin-in circuit provided in an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of pins of a chip provided in an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of the current flow of a first chip pin routing using pin input circuitry provided by an embodiment of the present disclosure;

fig. 6 is a schematic diagram of a current flow of a second chip pin routing using pin input circuitry provided by an embodiment of the present disclosure.

Reference numerals:

1: a clock port; 2: a first capacitor; 3: a second capacitor; 4: a first switch module; 5 a second switch module; 6: a buffer; 7: a first diode; 8: a second diode; 9: a PMOS tube; 10: an NMOS tube; 11: a first inductance; 12: and a second inductor.

Detailed Description

So that the manner in which the features and techniques of the disclosed embodiments can be understood in more detail, a more particular description of the embodiments of the disclosure, briefly summarized below, may be had by reference to the appended drawings, which are not intended to be limiting of the embodiments of the disclosure. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawing.

The terms first, second and the like in the description and in the claims of the embodiments of the disclosure and in the above-described figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe embodiments of the present disclosure. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.

In the embodiments of the present disclosure, the terms "upper", "lower", "inner", "middle", "outer", "front", "rear", and the like indicate an azimuth or a positional relationship based on that shown in the drawings. These terms are used primarily to better describe embodiments of the present disclosure and embodiments thereof and are not intended to limit the indicated device, element, or component to a particular orientation or to be constructed and operated in a particular orientation. Also, some of the terms described above may be used to indicate other meanings in addition to orientation or positional relationships, for example, the term "upper" may also be used to indicate some sort of attachment or connection in some cases. The specific meaning of these terms in the embodiments of the present disclosure will be understood by those of ordinary skill in the art in view of the specific circumstances.

In addition, the terms "disposed," "connected," "secured" and "affixed" are to be construed broadly. For example, "connected" may be in a fixed connection, a removable connection, or a unitary construction; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, elements, or components. The specific meaning of the above terms in the embodiments of the present disclosure may be understood by those of ordinary skill in the art according to specific circumstances.

The term "plurality" means two or more, unless otherwise indicated.

In the embodiment of the present disclosure, the character "/" indicates that the front and rear objects are an or relationship. For example, A/B represents: a or B.

The term "and/or" is an associative relationship that describes an object, meaning that there may be three relationships. For example, a and/or B, represent: a or B, or, A and B.

It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other.

As shown in connection with fig. 1, an embodiment of the present disclosure provides a first pin-in circuit, comprising: a clock port 1, a first capacitor 2, a second capacitor 3, a first switch module 4, a second switch module 5 and a buffer 6. A clock port 1 for providing a clock signal to the first capacitor 2, the second capacitor 3 and the buffer 6; the first input end of the first capacitor 2 is respectively connected with the clock port 1, the second output end of the second capacitor 3 and the fifth input end of the buffer 6, and the first output end of the first capacitor 2 is connected with the third input end of the first switch module 4; the first capacitor 2 is configured to provide a voltage to a third input terminal of the first switch module 4 to trigger the first switch module 4 to be turned on; the second output end of the second capacitor 3 is respectively connected with the clock port 1, the first input end of the first capacitor 2 and the fifth input end of the buffer 6, and the second input end of the second capacitor 3 is connected with the fourth output end of the second switch module 5; the second capacitor 3 is configured to provide a voltage to a fourth output terminal of the second switch module 5 to trigger the second switch module 5 to be turned on; the third input end of the first switch module 4 is connected with the first output end of the first capacitor 2, and the third output end of the first switch module 4 is connected with the power input end of the chip; the first switch module 4 is used for conducting a circuit between the clock port 1 and a power input end of the chip; the fourth output end of the second switch module 5 is connected with the second input end of the second capacitor 3, and the fourth input end of the second switch module 5 is connected with the power output end of the chip; the second switch module 5 is used for conducting a circuit between the clock port 1 and the power output end of the chip; the fifth input end of the buffer 6 is respectively connected with the clock port 1, the first input end of the first capacitor 2 and the second output end of the second capacitor 3, and the fifth output end of the buffer 6 is connected with the clock port of the chip; the buffer 6 is used for buffering the clock signal and providing the buffered clock signal to the clock port of the chip.

By adopting the pin input circuit provided by the embodiment of the disclosure, the clock signal is provided through the clock port connection clock signal, the buffered clock signal is provided for the clock port of the chip through the buffer, the circuit between the clock port and the power input end of the chip is conducted through the first capacitor connected with the clock port and the first switch module connected with the power input end of the chip, and the circuit between the clock port and the power output end of the chip is conducted through the second capacitor connected with the clock port and the second switch module connected with the power output end of the chip, so that the voltage drop on the inductor equivalent to the wire bonding of the power input end and the power output end can be reduced under the condition that the pin input circuit is applied to the chip, and the power disturbance caused by the inductor equivalent to the wire bonding of the power input end and the power output end is reduced.

Optionally, the power input end of the chip is a power interface of the chip.

Optionally, the power output terminal of the chip is a ground terminal interface of the chip.

Optionally, the clock signal is a periodic alternating current signal.

In some embodiments, the clock signal is a square wave signal. Therefore, the periodic square wave signal can be provided for the pin input circuit, so that the voltage drop on the equivalent inductance of the wire bonding of the power input end and the power output end can be reduced under the condition that the pin input circuit is applied to a chip, and the power disturbance caused by the equivalent inductance of the wire bonding of the power input end and the power output end is reduced.

Optionally, in the event of a rising edge of the square wave signal, the voltage of the clock port jumps from 0 to a preset voltage value. Optionally, the preset voltage value is the maximum value of the square wave signal.

Optionally, in case of an incoming rising edge of the square wave signal, the first output of the first capacitor is coupled with a preset voltage increment. Optionally, the preset voltage increment is the maximum value of the square wave signal. Optionally, the voltage across the first output and the first input of the first capacitor cannot be abrupt.

Optionally, in the case that the falling edge of the square wave signal arrives, the voltage of the clock port jumps from a preset voltage value to 0.

Optionally, in the event of a falling edge of the square wave signal, the second input of the second capacitor is coupled with a preset voltage decrement. Alternatively, the preset voltage decrement is the opposite number of the maximum value of the square wave signal. Optionally, the voltage across the second output and the second input of the second capacitor cannot be abrupt.

Optionally, the first switch module is a diode or PMOS transistor (positive channel Metal Oxide Semiconductor). Therefore, the first switch module can be triggered to be conducted through the voltage of the two ends of the first switch module to conduct a circuit between the clock port and the power input end of the chip, so that voltage drop on the equivalent inductance of the power input end can be reduced under the condition that the pin input circuit is applied to the chip, and power disturbance caused by the equivalent inductance of the power input end can be reduced.

Optionally, in the case that the first switch module is a diode, the third input terminal of the first switch module is an anode of the diode, and the third output terminal of the first switch module is a cathode of the diode.

Optionally, in the case that the first switch module is a PMOS transistor, the third input end of the first switch module is a drain electrode of the PMOS transistor, and the third output end of the first switch module is a source electrode of the PMOS transistor.

In some embodiments, the first switch module is a diode, and the first output end of the first capacitor is coupled with a preset voltage increment when the rising edge of the square wave signal arrives, and the diode is forward conducted when the voltage value of the first output end of the first capacitor is greater than a preset first conducting voltage, so that a forward average current from the clock port to the power input end is formed; the first conducting voltage is the sum of the maximum value of the square wave signal and the conducting voltage of the diode.

In some embodiments, after the first switch module is turned on for the first time, in the case that the rising edge of the square wave signal arrives, the voltage value of the first output end of the first capacitor is necessarily greater than a preset first turn-on voltage, and the first switch module is turned on to form a forward average current from the clock port to the power input end, i.e. a current path is formed between the clock port and the power input end; when the falling edge of the square wave signal comes, the first switch module is turned off, i.e. no current path exists between the clock port and the power input terminal.

Optionally, in the case that the first switch module is a PMOS transistor, the first gate of the first switch module is connected to the power output terminal of the chip. Therefore, the grid electrode of the PMOS tube and the source electrode of the PMOS tube are in a conducting state, so that the first switch module is conveniently triggered to be conducted through the voltage of the third input end and the voltage of the third output end of the first switch module, a circuit between the clock port and the power input end of the chip is conducted, and therefore voltage drop on the equivalent inductance of the power input end in the case that the pin input circuit is applied to the chip can be reduced, and power disturbance caused by the equivalent inductance of the power input end in the case that the pin input circuit is applied to the chip is reduced.

Optionally, in the case that the first switch module is a PMOS transistor, an N-well of the PMOS transistor is connected to a power input terminal of the chip.

Optionally, in the case that the first switch module is a PMOS transistor, the average current passing through the PMOS transistor is a sum of the average current passing through the parasitic PN junction of the PMOS transistor and the average current passing through the channel of the PMOS transistor. Therefore, when the first switch module is a PMOS tube, the average current passing through the PMOS tube is the sum of the average current passing through the parasitic PN junction of the PMOS tube and the average current passing through the channel of the PMOS tube, and the voltage drop on the equivalent inductance of the wire bonding of the power input end can be reduced under the condition that the pin input circuit is applied to a chip, so that the power disturbance caused by the equivalent inductance of the wire bonding of the power input end is reduced.

Optionally, the average current through the circuit between the clock port and the power input of the chip is the average current through the PMOS transistor.

Optionally, the parasitic PN junction of the PMOS tube is a parasitic PN junction corresponding to the drain electrode and the N well of the PMOS tube.

In some embodiments, the first switch module is a PMOS transistor, the gate of the PMOS transistor is connected to the power output end of the chip, then a drain of the PMOS transistor is in a conductive state with a source of the PMOS transistor, an initial voltage of the first output end of the first capacitor is the same as a voltage of the power output end of the chip, and in case that a rising edge of the square wave signal arrives, the first output end of the first capacitor is coupled with a preset voltage increment, then a maximum voltage value of the first output end of the first capacitor is a sum of a voltage value of the power output end of the chip and a maximum value of the square wave signal. Under the condition that the voltage value of the first output end of the first capacitor is larger than a preset second conduction voltage, parasitic PN junctions corresponding to the drain electrode and the N well of the PMOS tube are conducted in the forward direction, so that forward average current from the clock port to the power input end is formed; the second conducting voltage is the sum of the maximum value of the square wave signal and the conducting voltage of the parasitic PN junction of the PMOS tube. Meanwhile, the PMOS tube is conducted to form average current from the drain electrode to the source electrode, namely average current from the clock port to the power input end. Then, the average current through the PMOS transistor is the sum of the average current through the parasitic PN junction of the PMOS transistor and the average current through the channel of the PMOS transistor.

Optionally, the second switch module is a diode or an NMOS (N-Metal-Oxide-Semiconductor) transistor. Therefore, the second switch module can be triggered to be conducted through the voltage of the two ends of the second switch module to conduct a circuit between the clock port and the power output end of the chip, so that voltage drop on the equivalent inductance of the power output end can be reduced under the condition that the pin input circuit is applied to the chip, and power disturbance caused by the equivalent inductance of the power output end can be reduced.

Optionally, in the case that the second switch module is a diode, the fourth input terminal of the second switch module is an anode of the diode, and the fourth output terminal of the second switch module is a cathode of the diode.

Optionally, in the case that the second switch module is an NMOS transistor, the fourth input end of the second switch module is a source electrode of the NMOS transistor, and the fourth output end of the fourth switch module is a drain electrode of the NMOS transistor.

In some embodiments, the second switch module is a diode, and the second input end of the second capacitor is coupled with a preset voltage decrement when the falling edge of the square wave signal arrives, and the diode is forward conducted when the voltage value of the second input end of the second capacitor is smaller than a preset third conducting voltage, so that a forward average current from the power supply output end to the clock port is formed; the third conducting voltage is a negative value of the conducting voltage of the diode.

In some embodiments, after the second switch module is turned on for the first time, in the case that the falling edge of the square wave signal arrives, the voltage value of the second input end of the second capacitor is smaller than a preset third turn-on voltage, and the second switch module is turned on to form a forward average current from the power output end to the clock port, i.e. a current path is formed between the clock port and the power output end; when the rising edge of the square wave signal comes, the second switch module is turned off, i.e. no current path exists between the clock port and the power supply output terminal.

Optionally, in the case that the second switch module is an NMOS transistor, the second gate of the second switch module is connected to the power input terminal of the chip. Therefore, the grid electrode of the NMOS tube and the source electrode of the NMOS tube are in a conducting state, so that the first switch module is conveniently triggered to be conducted through the voltage of the third input end and the voltage of the third output end of the first switch module, a circuit between the clock port and the power input end of the chip is conducted, and therefore voltage drop on the equivalent inductance of the power input end in the case that the pin input circuit is applied to the chip can be reduced, and power disturbance caused by the equivalent inductance of the power input end in the case that the pin input circuit is applied to the chip is reduced.

Optionally, in the case that the second switch module is an NMOS transistor, a P substrate of the NMOS transistor is connected to a power input terminal of the chip.

Optionally, in the case that the second switching module is an NMOS transistor, the average current through the NMOS transistor is a sum of the average current through the parasitic PN junction of the NMOS transistor and the average current through the channel of the NMOS transistor. Therefore, the grid electrode of the NMOS tube and the source electrode of the NMOS tube are in a conducting state, so that the second switch module is conveniently triggered to be conducted through the voltage of the fourth input end and the voltage of the fourth output end of the second switch module, a circuit between the clock port and the power output end of the chip is conducted, and therefore voltage drop on the equivalent inductance of the power output end in the case that the pin input circuit is applied to the chip can be reduced, and power disturbance caused by the equivalent inductance of the power output end in the case that the pin input circuit is applied to the chip is reduced.

Optionally, the average current through the circuit between the clock port and the power supply output of the chip is the average current through the NMOS transistor.

Optionally, the parasitic PN junction of the NMOS tube is the parasitic PN junction corresponding to the drain electrode of the NMOS tube and the P substrate.

In some embodiments, the second switch module is an NMOS transistor, the gate of the NMOS transistor is connected to the power input end, and then a drain of the NMOS transistor is in a conductive state with the source of the NMOS transistor, an initial voltage of the second input end of the second capacitor is a voltage of the power input end of the chip, and in case that a falling edge of the square wave signal arrives, the second input end of the second capacitor is coupled with a preset voltage decrement, and then a minimum voltage value of the second input end of the second capacitor is a difference value between a voltage of the power input end of the chip and a negative value of a maximum value of twice the clock signal. Under the condition that the voltage value of the second input end of the second capacitor is smaller than a preset fourth conduction voltage, the parasitic PN junction of the NMOS tube is conducted in the forward direction, so that the forward average current from the power supply output end to the clock port is formed; the fourth turn-on voltage is the turn-on voltage of the parasitic PN junction. Meanwhile, the NMOS tube conducts the channel to form average current from the source electrode to the drain electrode, namely average current from the power output end to the clock port. Then the average current through the NMOS transistor is the sum of the average current through the parasitic PN junction of the NMOS transistor and the average current through the channel of the NMOS transistor.

As shown in connection with fig. 2, embodiments of the present disclosure provide a second kind of pin-in circuit, comprising: a clock port 1, a first capacitor 2, a second capacitor 3, a first diode 7, a second diode 8 and a buffer 6. A clock port 1 for providing a clock signal to the first capacitor 2, the second capacitor 3 and the buffer 6; the first input end of the first capacitor 2 is respectively connected with the clock port 1, the second output end of the second capacitor 3 and the fifth input end of the buffer 6, and the first output end of the first capacitor 2 is connected with the third input end of the first diode 7; the first capacitor 2 is used for providing voltage to the third input end of the first diode 7 so as to trigger the first diode 7 to be conducted; the second output end of the second capacitor 3 is respectively connected with the clock port 1, the first input end of the first capacitor 2 and the fifth input end of the buffer 6, and the second input end of the second capacitor 3 is connected with the fourth output end of the second diode 8; the second capacitor 3 is used for providing voltage to the fourth output end of the second diode 8 to trigger the second diode 8 to be conducted; the third input end of the first diode 7 is connected with the first output end of the first capacitor 2, and the third output end of the first diode 7 is connected with the power input end of the chip; the first diode 7 is used for conducting a circuit between the clock port 1 and a power input end of the chip; the fourth output end of the second diode 8 is connected with the second input end of the second capacitor 3, and the fourth input end of the second diode 8 is connected with the power supply output end of the chip; the second diode 8 is used for conducting a circuit between the clock port 1 and the power supply output end of the chip; the fifth input end of the buffer 6 is respectively connected with the clock port 1, the first input end of the first capacitor 2 and the second output end of the second capacitor 3, and the fifth output end of the buffer 6 is connected with the clock port of the chip; the buffer 6 is used for buffering the clock signal and providing the buffered clock signal to the clock port of the chip.

By adopting the pin input circuit provided by the embodiment of the disclosure, the clock signal is provided through the clock port connection clock signal, the buffered clock signal is provided for the clock port of the chip through the buffer, the circuit between the clock port and the power input end of the chip is conducted through the first capacitor connected with the clock port and the first diode connected with the power input end of the chip, and the circuit between the clock port and the power output end of the chip is conducted through the second capacitor connected with the clock port and the second diode connected with the power output end of the chip, so that the voltage drop on the inductor equivalent to the wire bonding of the power input end and the power output end can be reduced under the condition that the pin input circuit is applied to the chip, and the power disturbance caused by the inductor equivalent to the wire bonding of the power input end and the power output end is reduced.

As shown in connection with fig. 3, an embodiment of the present disclosure provides a third pin-in circuit, comprising: the clock port 1, the first capacitor 2, the second capacitor 3, the PMOS tube 9, the NMOS tube 10 and the buffer 6. A clock port 1 for providing a clock signal to the first capacitor 2, the second capacitor 3 and the buffer 6; the first input end of the first capacitor 2 is respectively connected with the clock port 1, the second output end of the second capacitor 3 and the fifth input end of the buffer 6, and the first output end of the first capacitor 2 is connected with the third input end of the PMOS tube 9; the first capacitor 2 is used for providing voltage for the third input end of the PMOS tube 9 so as to trigger the PMOS tube 9 to be conducted; the second output end of the second capacitor 3 is respectively connected with the clock port 1, the first input end of the first capacitor 2 and the fifth input end of the buffer 6, and the second input end of the second capacitor 3 is connected with the fourth output end of the NMOS tube 10; the second capacitor 3 is used for providing voltage for the fourth output end of the NMOS 10 to trigger the NMOS 10 to be turned on; the third input end of the PMOS tube 9 is connected with the first output end of the first capacitor 2, and the third output end of the PMOS tube 9 is connected with the power input end of the chip; the PMOS tube 9 is used for conducting a circuit between the clock port 1 and the power input end of the chip; the fourth output end of the NMOS tube 10 is connected with the second input end of the second capacitor 3, and the fourth input end of the NMOS tube 10 is connected with the power output end of the chip; the NMOS tube 10 is used for conducting a circuit between the clock port 1 and the power output end of the chip; the fifth input end of the buffer 6 is respectively connected with the clock port 1, the first input end of the first capacitor 2 and the second output end of the second capacitor 3, and the fifth output end of the buffer 6 is connected with the clock port of the chip; the buffer 6 is used for buffering the clock signal and providing the buffered clock signal to the clock port of the chip.

By adopting the pin input circuit provided by the embodiment of the disclosure, the clock signal is provided through the clock port connection clock signal, the buffered clock signal is provided for the clock port of the chip through the buffer, the circuit between the clock port and the power input end of the chip is conducted through the first capacitor connected with the clock port and the PMOS tube connected with the power input end of the chip, and the circuit between the clock port and the power output end of the chip is conducted through the second capacitor connected with the clock port and the NMOS tube connected with the power output end of the chip, so that the voltage drop on the equivalent inductance of the wire bonding of the power input end and the power output end can be reduced under the condition that the pin input circuit is applied to the chip, and the power disturbance caused by the equivalent inductance of the wire bonding of the power input end and the power output end is reduced.

The embodiment of the disclosure provides a chip, which comprises a clock port, a power input end, a power output end and the pin input circuit.

In some embodiments, the chip is a serial interface nonvolatile memory chip.

By adopting the chip provided by the embodiment of the disclosure, the clock signal is provided through the clock port connection clock signal, the buffer is used for providing the buffered clock signal for the clock port of the chip, the circuit between the clock port and the power input end of the chip is conducted through the first capacitor connected with the clock port and the first switch module connected with the power input end of the chip, and the circuit between the clock port and the power output end of the chip is conducted through the second capacitor connected with the clock port and the second switch module connected with the power output end of the chip, so that the voltage drop on the equivalent inductance of the power input end and the power output end in the wire bonding process can be reduced, and the power disturbance caused by the equivalent inductance of the power input end and the power output end in the wire bonding process is reduced.

Referring to fig. 4, a schematic pin diagram of a chip is provided in the embodiment of fig. 4. The pins of the chip include a CS (chip select) pin, a SO (data output) pin, a WP (write protect) pin, a GND (ground) pin, a SI (data input) pin, an SCLK (clock) pin, a HOLD (HOLD) pin, and a VCC (power supply) pin. Wherein the CS pin is used for chip selection input; the SO pin is used for SO data output and the WP pin is used for WP data write protection input; the GND pin is a power output end of the chip and is used for being connected with a GND ground wire; the SI pin is used for SI data input; the SCLK pin is used for SCLK clock input; the HOLD pin is used for HOLD input; the VCC pin is a power supply input end of the chip and is used for being connected with a VCC power supply line.

Optionally, the GND pin of the chip is connected to the fourth input of the second switching module.

Optionally, the VCC pin of the chip is connected with the third output terminal of the first switching module.

Optionally, in the above chip, the pin input circuit includes: a clock port connected with SCLK pin of the chip; for providing a clock signal to the first capacitor, the second capacitor and the buffer; the first input end of the first capacitor is connected with the clock port, the second output end of the second capacitor and the fifth input end of the buffer respectively, and the first output end of the first capacitor is connected with the third input end of the first switch module; the first capacitor is used for providing voltage for a third input end of the first switch module so as to trigger the first switch module to be conducted; the second output end of the second capacitor is connected with the clock port, the first input end of the first capacitor and the fifth input end of the buffer respectively, and the second input end of the second capacitor is connected with the fourth output end of the second switch module; the second capacitor is used for providing voltage for a fourth output end of the second switch module so as to trigger the second switch module to be conducted; the third input end of the first switch module is connected with the first output end of the first capacitor, and the third output end of the first switch module is connected with the VCC pin of the chip; the first switch module is used for conducting a circuit between the clock port and the power input end of the chip; the fourth input end of the second switch module is connected with the GND pin of the chip; the second switch module is used for conducting a circuit between the clock port and the power output end of the chip; the fifth input end of the buffer is respectively connected with the clock port, the first input end of the first capacitor and the second output end of the second capacitor, and the fifth output end of the buffer is connected with the clock port of the chip; the buffer is used for buffering the clock signal and providing the buffered clock signal to the clock port of the chip.

In this way, clock signals are provided through the clock port connection clock signals, buffered clock signals are provided for the clock port of the chip through the buffer, a circuit between the clock port and the VCC pin of the chip is conducted through the first capacitor connected with the clock port and the first switch module connected with the power input end of the chip, and a circuit between the clock port and the power output end of the chip is conducted through the second capacitor connected with the clock port and the second switch module connected with the GND pin of the chip, so that voltage drop on an inductor equivalent to the wire bonding of the VCC pin and the GND pin can be reduced, and power disturbance caused by the inductor equivalent to the wire bonding of the VCC pin and the GND pin is reduced.

Referring to fig. 5, fig. 5 is a schematic diagram of a current flow of a first chip pin routing using a pin input circuit according to an embodiment of the present disclosure. Wherein, the pins of the chip comprise CS pin, SO pin, WP pin, GND pin, SI pin, SCLK pin, HOLD pin and VCC pin; the first inductor 11 is an inductor corresponding to the VCC pin routing. The inductance of the first inductor 11 is j×ω1×l1; wherein ω1 is the angular velocity of the alternating current signal through the first inductance; l1 is the inductance value of the first inductor. The external voltage of the VCC pin is VCC_IO; when the rising edge of the clock signal input by the SCLK pin arrives, a current path exists between the SCLK pin and the VCC pin of the chip, the average current of the current path between the SCLK pin and the VCC pin is the current i_ck1 flowing from the SCLK pin to the VCC pin, the average current flowing in the first inductor is i_ccio, and the average current in the VCC power pin 208 is i_cc, which is the sum of the average current i_ccio and the average current i_ck1. Voltage at VCC pin: u1=vcc_io-j×ω1×l1× (Icc-i_ck1). Therefore, due to the existence of the average current I_C1 of the current path between the SCLK pin and the VCC pin, the voltage drop on the wire bonding inductance of the power VCC pin is obviously reduced, so that the fluctuation caused by the power inductance is reduced, the influence of the disturbance of the power on the chip is avoided, and the clock port of the chip, especially the stability of the operation of the analog circuit inside the chip and the storage unit inside the chip is improved.

In some embodiments, the first switch module is an NMOS transistor, and the average current i_ck1 of the current path between the SCLK pin and the VCC pin is the sum of the average current i_ck1_pn through the parasitic PN junction of the NMOS transistor and the average current i_ck1_pm through the channel of the NMOS transistor.

Referring to fig. 6, fig. 6 is a schematic diagram of a current flow of a second chip pin bonding wire using a pin input circuit according to an embodiment of the present disclosure. Wherein, the pins of the chip comprise CS pin, SO pin, WP pin, GND pin, SI pin, SCLK pin, HOLD pin and VCC pin; the second inductor 12 is an inductor corresponding to the wire bonding of the GND pin. The inductance of the second inductor 12 is j×ω2×l2; wherein ω2 is the angular velocity of the alternating current signal through the second inductance; l2 is the inductance value of the second inductor. The external voltage of the GND pin is GND_IO; when the falling edge of the clock signal input by the SCLK pin arrives, a current path is arranged between the SCLK pin and the GND pin of the chip, the average current of the current path between the SCLK pin and the VCC pin is I_ck2, the average current I_ck2 flows from the GND pin to the SCLK pin, the average current flowing in the second inductor is I_gndio, and the average current in the GND pin is I_gnd which is the difference between the average current I_gndio and the average current I_ck2. The voltage at GND pin: u2=gnd_io+j×ω×l2× (i_gnd-i_ck2). Therefore, due to the existence of the average current I_ck2 of the current path between the SCLK pin and the GND pin, the voltage drop on the routing inductance of the power GND pin is obviously reduced, so that the fluctuation caused by the power inductance is reduced, the influence of the disturbance of the power on the chip is avoided, and the working stability of the analog circuit inside the chip and the storage unit inside the chip is improved.

In some embodiments, the second switch module is a PMOS transistor, and the average current i_ck2 of the current path between the SCLK pin and the GND pin is the sum of the average current i_ck2_pn through the parasitic PN junction of the PMOS transistor and the average current i_ck2_pm through the channel of the NMOS transistor.

In some embodiments, the SCLK pin wire-bonding equivalent inductance does not have a directly significant effect on the power supply perturbations of the VCC pin and the GND pin.

The above description and the drawings illustrate embodiments of the disclosure sufficiently to enable those skilled in the art to practice them. Other embodiments may include structural and other modifications. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for, those of others. The embodiments of the present disclosure are not limited to the structures that have been described above and shown in the drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A pin input circuit, comprising:

a clock port for providing a clock signal to the first capacitor, the second capacitor and the buffer;

the first input end of the first capacitor is connected with the clock port, the second output end of the second capacitor and the fifth input end of the buffer respectively, and the first output end of the first capacitor is connected with the third input end of the first switch module; the first capacitor is used for providing voltage for a third input end of the first switch module so as to trigger the first switch module to be conducted;

the second output end of the second capacitor is connected with the clock port, the first input end of the first capacitor and the fifth input end of the buffer respectively, and the second input end of the second capacitor is connected with the fourth output end of the second switch module; the second capacitor is used for providing voltage for a fourth output end of the second switch module so as to trigger the second switch module to be conducted;

the third input end of the first switch module is connected with the first output end of the first capacitor of the third input end, and the third output end of the first switch module is connected with the power input end of the chip; the first switch module is used for conducting a circuit between the clock port and the power input end of the chip;

the fourth input end of the second switch module is connected with the power supply output end of the chip; the second switch module is used for conducting a circuit between the clock port and the power output end of the chip;

the fifth input end of the buffer is respectively connected with the clock port, the first input end of the first capacitor and the second output end of the second capacitor, and the fifth output end of the buffer is connected with the clock port of the chip; the buffer is used for buffering the clock signal and providing the buffered clock signal for the clock port of the chip;

in the case that the first switch module is a PMOS tube, a first grid electrode of the first switch module is connected with a power output end of the chip; the average current passing through the PMOS tube is the sum of the average current passing through the parasitic PN junction of the PMOS tube and the average current passing through the channel of the PMOS tube;

in the case that the second switch module is an NMOS tube, a second grid electrode of the second switch module is connected with a power input end of the chip; the average current through the NMOS tube is the sum of the average current through the parasitic PN junction of the NMOS tube and the average current through the channel of the NMOS tube.

2. The pin-in circuit of claim 1, wherein the clock signal is a periodic square wave signal.

3. A chip comprising a clock port, a power input, a power output and a pin-in circuit as claimed in claim 1 or 2.

4. The chip of claim 3, wherein the pin-in circuit comprises:

a clock port connected with SCLK pin of the chip; for providing a clock signal to the first capacitor, the second capacitor and the buffer;

the third input end of the first switch module is connected with the first output end of the first capacitor, and the third output end of the first switch module is connected with the VCC pin of the chip; the first switch module is used for conducting a circuit between the clock port and the power input end of the chip;

the fourth input end of the second switch module is connected with the GND pin of the chip; the second switch module is used for conducting a circuit between the clock port and the power output end of the chip;

in the case that the first switch module is a PMOS tube, a first grid electrode of the first switch module is connected with a power output end of the chip; the first grid electrode of the first switch module is connected with the power supply output end of the chip; the average current passing through the PMOS tube is the sum of the average current passing through the parasitic PN junction of the PMOS tube and the average current passing through the channel of the PMOS tube;