CN114362482A

CN114362482A - Pin input circuit and chip

Info

Publication number: CN114362482A
Application number: CN202210149402.2A
Authority: CN
Inventors: 马继荣
Original assignee: Beijing Unigroup Tsingteng Microsystems Co Ltd
Current assignee: Beijing Unigroup Tsingteng Microsystems Co Ltd
Priority date: 2022-02-18
Filing date: 2022-02-18
Publication date: 2022-04-15
Anticipated expiration: 2042-02-18
Also published as: CN114362482B

Abstract

The application relates to the technical field of integrated circuit design and discloses a pin input circuit. The clock port is connected with a clock signal through the clock port to provide the clock signal, the buffer provides the buffered clock signal for the clock port of the chip, the first capacitor connected with the clock port and the first switch module connected with the power input end of the chip are used for switching on a circuit between the clock port and the power input end of the chip, the second capacitor connected with the clock port and the second switch module connected with the power output end of the chip are used for switching on a circuit between the clock port and the power output end of the chip, and therefore under the condition that the pin input circuit is applied to the chip, the voltage drop on the inductance equivalent to the routing of the power input end and the power output end can be reduced, and power disturbance caused by the inductance equivalent to the routing of the power input end and the power output end is reduced. The application also discloses a chip.

Description

Pin input circuit and chip

Technical Field

The present application relates to the field of integrated circuit design technologies, and for example, to a pin input circuit and a chip.

Background

At present, with the development of integrated circuit design technology, the application range of chips is more and more extensive. In the case of a chip running the program code of an electronic device system, the average current through the power pins of the chip will be larger and larger as the instantaneous power consumption of the electronic device system increases. The average current will cause a large disturbance on the power pin of the chip when passing through the wire bonding equivalent inductance of the power pin of the chip.

In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art: the power disturbance of the chip power supply pin cannot be reduced in the prior art.

Disclosure of Invention

The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview nor is intended to identify key/critical elements or to delineate the scope of such embodiments but rather as a prelude to the more detailed description that is presented later.

The embodiment of the disclosure provides a pin input circuit and a chip, so as to reduce power disturbance of a power pin of the chip.

In some embodiments, the pin input circuit comprises: the clock port is used for providing clock signals for the first capacitor, the second capacitor and the buffer; a first input end of the first capacitor is respectively connected with the clock port, a second output end of the second capacitor and a fifth input end of the buffer, and a first output end of the first capacitor is connected with a third input end of the first switch module; the first capacitor is used for providing voltage for a third input end of the first switch module so as to trigger the first switch module to be conducted; the second output end of the second capacitor is connected with a clock port, the first input end of the first capacitor and the fifth input end of the buffer respectively, and the second input end of the second capacitor is connected with the fourth output end of the second switch module; the second capacitor is used for providing voltage for a fourth output end of the second switch module so as to trigger the second switch module to be conducted; the third input end of the first switch module is connected with the first output end of the first capacitor, and the third output end of the first switch module is connected with the power supply input end of the chip; the first switch module is used for conducting a circuit between the clock port and the power supply input end of the chip; the fourth output end of the second switch module is connected with the second input end of the second capacitor, and the fourth input end of the second switch module is connected with the power supply output end of the chip; the second switch module is used for conducting a circuit between the clock port and the power supply output end of the chip; the fifth input end of the buffer is respectively connected with a clock port, the first input end of the first capacitor and the second output end of the second capacitor, and the fifth output end of the buffer is connected with the clock port of the chip; the buffer is used for buffering the clock signal and providing the buffered clock signal to a clock port of the chip.

In some embodiments, the chip includes a clock port, a power input, a power output, and the pin input circuit described above.

The pin input circuit and the chip provided by the embodiment of the disclosure can realize the following technical effects: the clock port is connected with a clock signal through the clock port to provide the clock signal, the buffer provides the buffered clock signal for the clock port of the chip, the first capacitor connected with the clock port and the first switch module connected with the power input end of the chip are used for switching on a circuit between the clock port and the power input end of the chip, the second capacitor connected with the clock port and the second switch module connected with the power output end of the chip are used for switching on a circuit between the clock port and the power output end of the chip, and therefore under the condition that the pin input circuit is applied to the chip, the voltage drop on the inductance equivalent to the routing of the power input end and the power output end can be reduced, and power disturbance caused by the inductance equivalent to the routing of the power input end and the power output end is reduced.

The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the accompanying drawings and not in limitation thereof, in which elements having the same reference numeral designations are shown as like elements and not in limitation thereof, and wherein:

fig. 1 is a schematic structural diagram of a first pin input circuit provided in an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a second pin input circuit provided in the embodiments of the present disclosure;

fig. 3 is a schematic structural diagram of a third pin input circuit provided in the embodiment of the present disclosure;

FIG. 4 is a pin diagram of a chip provided in accordance with an embodiment of the present disclosure;

fig. 5 is a schematic diagram illustrating a current flow direction of a first chip pin bonding using a pin input circuit according to an embodiment of the present disclosure;

fig. 6 is a schematic diagram illustrating a current flow direction of a second chip pin bonding using a pin input circuit according to an embodiment of the present disclosure.

Reference numerals:

1: a clock port; 2: a first capacitor; 3: a second capacitor; 4: a first switch module; 5 a second switch module; 6: a buffer; 7: a first diode; 8: a second diode; 9: a PMOS tube; 10: an NMOS tube; 11: a first inductor; 12: a second inductor.

Detailed Description

So that the manner in which the features and elements of the disclosed embodiments can be understood in detail, a more particular description of the disclosed embodiments, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other instances, well-known structures and devices may be shown in simplified form in order to simplify the drawing.

The terms "first," "second," and the like in the description and in the claims, and the above-described drawings of embodiments of the present disclosure, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the present disclosure described herein may be made. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions.

In the embodiments of the present disclosure, the terms "upper", "lower", "inner", "middle", "outer", "front", "rear", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings. These terms are used primarily to better describe the disclosed embodiments and their examples and are not intended to limit the indicated devices, elements or components to a particular orientation or to be constructed and operated in a particular orientation. Moreover, some of the above terms may be used to indicate other meanings besides the orientation or positional relationship, for example, the term "on" may also be used to indicate some kind of attachment or connection relationship in some cases. The specific meanings of these terms in the embodiments of the present disclosure can be understood by those of ordinary skill in the art as appropriate.

In addition, the terms "disposed," "connected," and "secured" are to be construed broadly. For example, "connected" may be a fixed connection, a detachable connection, or a unitary construction; can be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, elements or components. Specific meanings of the above terms in the embodiments of the present disclosure can be understood by those of ordinary skill in the art according to specific situations.

The term "plurality" means two or more unless otherwise specified.

In the embodiment of the present disclosure, the character "/" indicates that the preceding and following objects are in an or relationship. For example, A/B represents: a or B.

The term "and/or" is an associative relationship that describes objects, meaning that three relationships may exist. For example, a and/or B, represents: a or B, or A and B.

It should be noted that, in the case of no conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

With reference to fig. 1, an embodiment of the present disclosure provides a first pin input circuit, including: clock port 1, first capacitor 2, second capacitor 3, first switch module 4, second switch module 5 and buffer 6. A clock port 1 for providing a clock signal to the first capacitor 2, the second capacitor 3 and the buffer 6; a first input end of the first capacitor 2 is connected with the clock port 1, a second output end of the second capacitor 3 and a fifth input end of the buffer 6 respectively, and a first output end of the first capacitor 2 is connected with a third input end of the first switch module 4; the first capacitor 2 is used for providing voltage for a third input end of the first switch module 4 so as to trigger the first switch module 4 to be conducted; a second output end of the second capacitor 3 is connected with the clock port 1, the first input end of the first capacitor 2 and the fifth input end of the buffer 6 respectively, and a second input end of the second capacitor 3 is connected with a fourth output end of the second switch module 5; the second capacitor 3 is used for providing voltage for a fourth output end of the second switch module 5 so as to trigger the second switch module 5 to be conducted; a third input end of the first switch module 4 is connected with the first output end of the first capacitor 2, and a third output end of the first switch module 4 is connected with a power supply input end of the chip; the first switch module 4 is used for conducting a circuit between the clock port 1 and a power supply input end of the chip; a fourth output end of the second switch module 5 is connected with a second input end of the second capacitor 3, and a fourth input end of the second switch module 5 is connected with a power supply output end of the chip; the second switch module 5 is used for conducting a circuit between the clock port 1 and the power supply output end of the chip; a fifth input end of the buffer 6 is respectively connected with the clock port 1, the first input end of the first capacitor 2 and the second output end of the second capacitor 3, and a fifth output end of the buffer 6 is connected with the clock port of the chip; the buffer 6 is used for buffering the clock signal and providing the buffered clock signal to the clock port of the chip.

By adopting the pin input circuit provided by the embodiment of the disclosure, the clock signal is provided by connecting the clock port, the buffered clock signal is provided for the clock port of the chip by the buffer, the circuit between the clock port and the power input end of the chip is conducted by the first capacitor connected with the clock port and the first switch module connected with the power input end of the chip, and the circuit between the clock port and the power output end of the chip is conducted by the second capacitor connected with the clock port and the second switch module connected with the power output end of the chip, so that under the condition that the pin input circuit is applied to the chip, the voltage drop on the wire bonding equivalent inductance of the power input end and the power output end can be reduced, and the power disturbance caused by the wire bonding equivalent inductance of the power input end and the power output end is reduced.

Optionally, the power input terminal of the chip is a power interface of the chip.

Optionally, the power output terminal of the chip is a ground terminal interface of the chip.

Optionally, the clock signal is a periodic alternating current signal.

In some embodiments, the clock signal is a square wave signal. Therefore, periodic square wave signals can be provided for the pin input circuit, so that under the condition that the pin input circuit is applied to a chip, the voltage drop of the wire bonding equivalent inductance of the power input end and the power output end can be reduced, and the power disturbance caused by the wire bonding equivalent inductance of the power input end and the power output end is reduced.

Alternatively, in case of the rising edge of the square wave signal arriving, the voltage of the clock port jumps from 0 to a preset voltage value. Optionally, the preset voltage value is a maximum value of the square wave signal.

Optionally, the first output terminal of the first capacitor is coupled with a predetermined voltage increment upon arrival of a rising edge of the square wave signal. Optionally, the preset voltage increment is a maximum value of the square wave signal. Optionally, the voltage across the first output terminal and the first input terminal of the first capacitor cannot jump abruptly.

Alternatively, in case of the falling edge of the square wave signal arriving, the voltage of the clock port jumps from a preset voltage value to 0.

Optionally, the second input terminal of the second capacitor is coupled with a predetermined voltage decrement when the falling edge of the square wave signal arrives. Optionally, the preset voltage decrement is an inverse of a maximum value of the square wave signal. Optionally, the voltage across the second output terminal and the second input terminal of the second capacitor cannot jump abruptly.

Optionally, the first switch module is a diode or a PMOS (positive channel Metal Oxide Semiconductor). Therefore, the first switch module can be triggered to be switched on through the voltage at the two ends of the first switch module to switch on a circuit between the clock port and the power input end of the chip, so that the voltage drop of the routing equivalent inductance of the power input end can be reduced under the condition that the pin input circuit is applied to the chip, and the power disturbance caused by the routing equivalent inductance of the power input end is reduced.

Optionally, in a case that the first switch module is a diode, the third input end of the first switch module is an anode of the diode, and the third output end of the first switch module is a cathode of the diode.

Optionally, in a case that the first switch module is a PMOS transistor, the third input terminal of the first switch module is a drain of the PMOS transistor, and the third output terminal of the first switch module is a source of the PMOS transistor.

In some embodiments, the first switch module is a diode, the first output terminal of the first capacitor is coupled with a preset voltage increment when a rising edge of the square wave signal arrives, and the diode is turned on in the forward direction to form a forward average current from the clock port to the power supply input terminal when the voltage value of the first output terminal of the first capacitor is greater than a preset first on-state voltage; the first conduction voltage is the sum of the maximum value of the square wave signal and the conduction voltage of the diode.

In some embodiments, after the first switch module is turned on for the first time, when a rising edge of the square wave signal arrives, a voltage value of the first output end of the first capacitor is necessarily greater than a preset first turn-on voltage, the first switch module is turned on to form a positive average current from the clock port to the power input end, that is, a current path is formed between the clock port and the power input end; when the falling edge of the square wave signal arrives, the first switch module is turned off, namely, no current path exists between the clock port and the power supply input end.

Optionally, in a case that the first switch module is a PMOS transistor, the first gate of the first switch module is connected to the power output terminal of the chip. Therefore, the grid electrode of the PMOS tube and the source electrode of the PMOS tube can be in a conduction state, the first switch module is triggered to be conducted through the voltage of the third input end and the third output end of the first switch module, the circuit between the clock port and the power input end of the chip is conducted, the voltage drop of the routing equivalent inductance of the power input end can be reduced under the condition that the pin input circuit is applied to the chip, and the power disturbance caused by the routing equivalent inductance of the power input end is reduced.

Optionally, in the case that the first switch module is a PMOS transistor, an N-well of the PMOS transistor is connected to the power input terminal of the chip.

Optionally, in the case that the first switch module is a PMOS transistor, the average current through the PMOS transistor is the sum of the average current through the parasitic PN junction of the PMOS transistor and the average current through the channel of the PMOS transistor. Therefore, under the condition that the first switch module is a PMOS (P-channel metal oxide semiconductor) tube, the average current passing through the PMOS tube is the sum of the average current passing through a parasitic PN junction of the PMOS tube and the average current passing through a channel of the PMOS tube, so that under the condition that the pin input circuit is applied to a chip, the voltage drop on the wire bonding equivalent inductance of the power input end can be reduced, and the power disturbance caused by the wire bonding equivalent inductance of the power input end is reduced.

Optionally, the average current through the circuit between the clock port and the power input of the chip is the average current through the PMOS transistor.

Optionally, the parasitic PN junction of the PMOS transistor is a parasitic PN junction corresponding to the drain of the PMOS transistor and the N-well.

In some embodiments, the first switch module is a PMOS transistor, a gate of the PMOS transistor is connected to the power output terminal of the chip, a drain of the PMOS transistor and a source of the PMOS transistor are in a conducting state, an initial voltage of the first output terminal of the first capacitor is the same as a voltage of the power output terminal of the chip, when a rising edge of the square wave signal arrives, the first output terminal of the first capacitor is coupled by a preset voltage increment, and a maximum voltage value of the first output terminal of the first capacitor is a sum of the voltage value of the power output terminal of the chip and a maximum value of the square wave signal. Under the condition that the voltage value of the first output end of the first capacitor is larger than a preset second conduction voltage, the drain electrode of the PMOS tube is conducted in the forward direction with the parasitic PN junction corresponding to the N well, and a forward average current from the clock port to the power supply input end is formed; the second conduction voltage is the sum of the maximum value of the square wave signal and the conduction voltage of a parasitic PN junction of the PMOS tube. Meanwhile, the PMOS tube conduction channel forms the average current of the drain electrode towards the source electrode direction, namely the average current of the clock port towards the power supply input end. Then, the average current through the PMOS transistor is the sum of the average current through the parasitic PN junction of the PMOS transistor and the average current through the channel of the PMOS transistor.

Optionally, the second switch module is a diode or an NMOS transistor (N-Metal-Oxide-Semiconductor). Therefore, the second switch module can be triggered to be switched on through the voltage at the two ends of the second switch module to switch on a circuit between the clock port and the power output end of the chip, so that the voltage drop of the routing equivalent inductance of the power output end can be reduced under the condition that the pin input circuit is applied to the chip, and the power disturbance caused by the routing equivalent inductance of the power output end is reduced.

Optionally, in a case that the second switch module is a diode, the fourth input end of the second switch module is an anode of the diode, and the fourth output end of the second switch module is a cathode of the diode.

Optionally, in a case that the second switch module is an NMOS transistor, a fourth input end of the second switch module is a source of the NMOS transistor, and a fourth output end of the fourth switch module is a drain of the NMOS transistor.

In some embodiments, the second switch module is a diode, the second input terminal of the second capacitor is coupled with a preset voltage decrement when the falling edge of the square wave signal arrives, and the diode is turned on in the forward direction when the voltage value of the second input terminal of the second capacitor is smaller than a preset third on-state voltage, so as to form a forward average current from the power output terminal to the clock port; and the third conduction voltage is the negative value of the conduction voltage of the diode.

In some embodiments, after the first switching module is turned on, when a falling edge of the square wave signal arrives, a voltage value of the second input terminal of the second capacitor is smaller than a preset third on-state voltage, and the second switching module is turned on to form a forward average current from the power output terminal to the clock port, that is, a current path is formed between the clock port and the power output terminal; when the rising edge of the square wave signal arrives, the second switch module is turned off, namely, no current path exists between the clock port and the power output end.

Optionally, in a case that the second switch module is an NMOS transistor, a second gate of the second switch module is connected to the power input terminal of the chip. Therefore, the grid electrode of the NMOS tube and the source electrode of the NMOS tube can be in a conduction state, the first switch module is triggered to be conducted through the voltage of the third input end and the third output end of the first switch module, a circuit between the clock port and the power input end of the chip is conducted, the voltage drop of the routing equivalent inductance of the power input end can be reduced under the condition that the pin input circuit is applied to the chip, and power disturbance caused by the routing equivalent inductance of the power input end is reduced.

Optionally, in the case that the second switch module is an NMOS transistor, the P substrate of the NMOS transistor is connected to the power input terminal of the chip.

Optionally, in the case that the second switch module is an NMOS transistor, the average current through the NMOS transistor is the sum of the average current through the parasitic PN junction of the NMOS transistor and the average current through the channel of the NMOS transistor. Therefore, the grid electrode of the NMOS tube and the source electrode of the NMOS tube can be in a conduction state, the second switch module is triggered to be conducted through the voltage of the fourth input end and the fourth output end of the second switch module, a circuit between the clock port and the power output end of the chip is conducted, the voltage drop of the wire bonding equivalent inductance of the power output end can be reduced under the condition that the pin input circuit is applied to the chip, and the power disturbance caused by the wire bonding equivalent inductance of the power output end is reduced.

Optionally, the average current through the circuit between the clock port and the power supply output of the chip is the average current through the NMOS transistor.

Optionally, the parasitic PN junction of the NMOS transistor is a parasitic PN junction corresponding to the drain of the NMOS transistor and the P substrate.

In some embodiments, the second switch module is an NMOS transistor, a gate of the NMOS transistor is connected to the power input terminal, a drain of the NMOS transistor and a source of the NMOS transistor are in a conducting state, an initial voltage of the second input terminal of the second capacitor is a voltage of the power input terminal of the chip, when a falling edge of the square wave signal arrives, the second input terminal of the second capacitor is coupled to a preset voltage decrement, and a minimum voltage value of the second input terminal of the second capacitor is a difference between the voltage of the power input terminal of the chip and a negative value of a maximum value of twice the clock signal. Under the condition that the voltage value of the second input end of the second capacitor is smaller than a preset fourth breakover voltage, a parasitic PN junction of the NMOS tube is conducted in the forward direction, and a forward average current from the power supply output end to the clock port is formed; the fourth turn-on voltage is the turn-on voltage of the parasitic PN junction. Meanwhile, the NMOS tube conduction channel forms the average current from the source electrode to the drain electrode, namely the average current from the power supply output end to the clock port. Then, the average current through the NMOS transistor is the sum of the average current through the parasitic PN junction of the NMOS transistor and the average current through the channel of the NMOS transistor.

With reference to fig. 2, an embodiment of the present disclosure provides a second pin input circuit, including: clock port 1, first capacitor 2, second capacitor 3, first diode 7, second diode 8 and buffer 6. A clock port 1 for providing a clock signal to the first capacitor 2, the second capacitor 3 and the buffer 6; a first input end of the first capacitor 2 is connected with the clock port 1, a second output end of the second capacitor 3 and a fifth input end of the buffer 6 respectively, and a first output end of the first capacitor 2 is connected with a third input end of the first diode 7; the first capacitor 2 is used for providing voltage for a third input end of the first diode 7 so as to trigger the first diode 7 to be conducted; a second output end of the second capacitor 3 is connected with the clock port 1, the first input end of the first capacitor 2 and the fifth input end of the buffer 6 respectively, and a second input end of the second capacitor 3 is connected with a fourth output end of the second diode 8; the second capacitor 3 is used for providing voltage for a fourth output end of the second diode 8 so as to trigger the second diode 8 to be conducted; a third input end of the first diode 7 is connected with the first output end of the first capacitor 2, and a third output end of the first diode 7 is connected with a power supply input end of the chip; the first diode 7 is used for conducting a circuit between the clock port 1 and the power supply input end of the chip; a fourth output end of the second diode 8 is connected with the second input end of the second capacitor 3, and a fourth input end of the second diode 8 is connected with the power supply output end of the chip; the second diode 8 is used for conducting a circuit between the clock port 1 and the power supply output end of the chip; a fifth input end of the buffer 6 is respectively connected with the clock port 1, the first input end of the first capacitor 2 and the second output end of the second capacitor 3, and a fifth output end of the buffer 6 is connected with the clock port of the chip; the buffer 6 is used for buffering the clock signal and providing the buffered clock signal to the clock port of the chip.

By adopting the pin input circuit provided by the embodiment of the disclosure, the clock signal is provided by connecting the clock port, the buffered clock signal is provided for the clock port of the chip by the buffer, the circuit between the clock port and the power input end of the chip is conducted by the first capacitor connected with the clock port and the first diode connected with the power input end of the chip, and the circuit between the clock port and the power output end of the chip is conducted by the second capacitor connected with the clock port and the second diode connected with the power output end of the chip, so that under the condition that the pin input circuit is applied to the chip, the voltage drop on the wire bonding equivalent inductance of the power input end and the power output end can be reduced, and the power disturbance caused by the wire bonding equivalent inductance of the power input end and the power output end is reduced.

As shown in fig. 3, an embodiment of the present disclosure provides a third pin input circuit, including: clock port 1, first electric capacity 2, second electric capacity 3, PMOS pipe 9, NMOS pipe 10 and buffer 6. A clock port 1 for providing a clock signal to the first capacitor 2, the second capacitor 3 and the buffer 6; a first input end of the first capacitor 2 is connected with the clock port 1, a second output end of the second capacitor 3 and a fifth input end of the buffer 6 respectively, and a first output end of the first capacitor 2 is connected with a third input end of the PMOS tube 9; the first capacitor 2 is used for providing voltage for a third input end of the PMOS tube 9 so as to trigger the conduction of the PMOS tube 9; a second output end of the second capacitor 3 is connected with the clock port 1, the first input end of the first capacitor 2 and the fifth input end of the buffer 6 respectively, and a second input end of the second capacitor 3 is connected with a fourth output end of the NMOS tube 10; the second capacitor 3 is used for providing voltage for the fourth output end of the NMOS transistor 10 to trigger the NMOS transistor 10 to be turned on; a third input end of the PMOS tube 9 is connected with the first output end of the first capacitor 2, and a third output end of the PMOS tube 9 is connected with a power supply input end of the chip; the PMOS tube 9 is used for conducting a circuit between the clock port 1 and the power supply input end of the chip; a fourth output end of the NMOS tube 10 is connected with a second input end of the second capacitor 3, and a fourth input end of the NMOS tube 10 is connected with a power supply output end of the chip; the NMOS tube 10 is used for conducting a circuit between the clock port 1 and the power supply output end of the chip; a fifth input end of the buffer 6 is respectively connected with the clock port 1, the first input end of the first capacitor 2 and the second output end of the second capacitor 3, and a fifth output end of the buffer 6 is connected with the clock port of the chip; the buffer 6 is used for buffering the clock signal and providing the buffered clock signal to the clock port of the chip.

By adopting the pin input circuit provided by the embodiment of the disclosure, the clock signal is provided by connecting the clock port, the buffered clock signal is provided for the clock port of the chip by the buffer, the circuit between the clock port and the power input end of the chip is conducted by the first capacitor connected with the clock port and the PMOS tube connected with the power input end of the chip, and the circuit between the clock port and the power output end of the chip is conducted by the second capacitor connected with the clock port and the NMOS tube connected with the power output end of the chip, so that under the condition that the pin input circuit is applied to the chip, the voltage drop on the wire bonding equivalent inductance of the power input end and the power output end can be reduced, and the power disturbance caused by the wire bonding equivalent inductance of the power input end and the power output end is reduced.

The embodiment of the disclosure provides a chip, which comprises a clock port, a power input end, a power output end and the pin input circuit.

In some embodiments, the chip is a serial interface non-volatile memory chip.

By adopting the chip provided by the embodiment of the disclosure, the clock signal is provided by connecting the clock port through the clock port, the buffered clock signal is provided for the clock port of the chip through the buffer, the circuit between the clock port and the power input end of the chip is conducted through the first capacitor connected with the clock port and the first switch module connected with the power input end of the chip, and the circuit between the clock port and the power output end of the chip is conducted through the second capacitor connected with the clock port and the second switch module connected with the power output end of the chip, so that the voltage drop on the wire bonding equivalent inductance of the power input end and the power output end can be reduced, and the power disturbance caused by the wire bonding equivalent inductance of the power input end and the power output end is reduced.

Referring to fig. 4, a pin diagram of a chip provided in this embodiment of fig. 4 is shown. The pins of the chip include a CS (chip select) pin, an SO (data output) pin, a WP (write protect) pin, a GND (ground) pin, an SI (data input) pin, an SCLK (clock) pin, a HOLD pin, and a VCC (power supply) pin. The CS pin is used for chip selection input; the SO pin is used for SO data output, and the WP pin is used for WP data write protection input; the GND pin is a power output end of the chip and is used for being connected with a GND ground wire; the SI pin is used for SI data input; the SCLK pin is used for SCLK clock input; the HOLD pin is used for HOLD holding input; the VCC pin is a power input end of the chip and is used for connecting a VCC power line.

Optionally, the GND pin of the chip is connected to the fourth input terminal of the second switch module.

Optionally, the VCC pin of the chip is connected to the third output terminal of the first switch module.

Optionally, in the above chip, the pin input circuit includes: the clock port is connected with an SCLK pin of the chip; the first capacitor, the second capacitor and the buffer are provided with clock signals; the first input end of the first capacitor is connected with the clock port, the second output end of the second capacitor and the fifth input end of the buffer respectively, and the first output end of the first capacitor is connected with the third input end of the first switch module; the first capacitor is used for providing voltage for the third input end of the first switch module so as to trigger the first switch module to be conducted; a second output end of the second capacitor is respectively connected with the clock port, the first input end of the first capacitor and the fifth input end of the buffer, and a second input end of the second capacitor is connected with a fourth output end of the second switch module; the second capacitor is used for providing voltage for a fourth output end of the second switch module so as to trigger the second switch module to be conducted; a third input end of the first switch module is connected with a first output end of the first capacitor, and a third output end of the first switch module is connected with a VCC pin of the chip; the first switch module is used for conducting a circuit between the clock port and the power supply input end of the chip; a fourth output end of the second switch module is connected with a second input end of the second capacitor, and a fourth input end of the second switch module is connected with a GND pin of the chip; the second switch module is used for conducting a circuit between the clock port and the power supply output end of the chip; a fifth input end of the buffer is respectively connected with the clock port, the first input end of the first capacitor and the second output end of the second capacitor, and a fifth output end of the buffer is connected with the clock port of the chip; the buffer is used for buffering the clock signal and providing the buffered clock signal to a clock port of the chip.

Like this, connect clock signal through the clock port and provide clock signal, clock signal after providing the buffering through the buffer for the clock port of chip, and switch on the circuit between the VCC pin of clock port and chip through the first electric capacity of being connected with the clock port and the first switch module of being connected with the power input end of chip, switch on the circuit between the power output end of clock port and chip through the second electric capacity of being connected with the clock port and the second switch module of being connected with the GND pin of chip, thereby can reduce the pressure drop on the routing equivalent inductance of VCC pin and GND pin, thereby the power disturbance that the routing equivalent inductance of VCC pin and GND pin caused has been reduced.

Referring to fig. 5, fig. 5 is a schematic diagram illustrating a current flow direction of a chip pin bonding of a first application pin input circuit according to an embodiment of the present disclosure. The pins of the chip comprise a CS pin, a SO pin, a WP pin, a GND pin, an SI pin, an SCLK pin, a HOLD pin and a VCC pin; the first inductor 11 is an inductor corresponding to the VCC pin routing. The inductance of the first inductor 11 is j × ω 1 × L1; where ω 1 is the angular velocity of the ac signal through the first inductor; l1 is the inductance of the first inductor. The external voltage of the VCC pin is VCC _ IO; when the rising edge of the clock signal input by the SCLK pin arrives, a current path exists between the SCLK pin and the VCC pin of the chip, the average current of the current path between the SCLK pin and the VCC pin is the current I _ ck1 flowing from the SCLK pin to the VCC pin, the average current flowing in the first inductor is I _ ccio, and the average current in the VCC power supply pin 208 is I _ cc which is the sum of the average current I _ ccio and the average current I _ ck 1. The voltage at the VCC pin is: u1 ═ VCC _ IO-j × ω 1 × L1 × (Icc-I _ ck 1). It can be seen that due to the existence of the average current I _ ck1 of the current path between the SCLK pin and the VCC pin, the voltage drop on the routing inductor of the VCC pin of the power supply is significantly reduced, thereby reducing the fluctuation caused by the power supply inductor, avoiding the influence of the disturbance of the power supply on the chip, and improving the working stability of the chip clock port, especially the analog circuit inside the chip and the memory cell inside the chip.

In some embodiments, the first switch module is an NMOS transistor, and the average current I _ ck1 of the current path between the SCLK pin and the VCC pin is the sum of the average current I _ ck1_ PN passing through the parasitic PN junction of the NMOS transistor and the average current I _ ck1_ pm passing through the channel of the NMOS transistor.

Referring to fig. 6, fig. 6 is a schematic diagram illustrating a current flow direction of a chip pin bonding of a second application pin input circuit according to an embodiment of the present disclosure. The pins of the chip comprise a CS pin, a SO pin, a WP pin, a GND pin, an SI pin, an SCLK pin, a HOLD pin and a VCC pin; the second inductor 12 is an inductor corresponding to the routing of the GND pin. The inductive reactance of the second inductor 12 is j × ω 2 × L2; where ω 2 is the angular velocity of the ac signal through the second inductor; l2 is the inductance of the second inductor. The external voltage of the GND pin is GND _ IO; when the falling edge of the clock signal input by the SCLK pin arrives, a current path exists between the SCLK pin and the GND pin of the chip, the average current of the current path between the SCLK pin and the VCC pin is I _ ck2, the average current I _ ck2 flows from the GND pin to the SCLK pin, the average current flowing in the second inductor is I _ gndio, and the average current I _ GND in the GND pin is the difference between the average current I _ gndio and the average current I _ ck 2. The voltage at the GND pin is: u2 ═ GND _ IO + j × ω × L2 × (I _ GND-I _ ck 2). Therefore, due to the existence of the average current I _ ck2 of the current path between the SCLK pin and the GND pin, the voltage drop on the routing inductor of the power GND pin is obviously reduced, so that the fluctuation caused by the power inductor is reduced, the influence of the disturbance of the power supply on the chip is avoided, and the working stability of the analog circuit inside the chip and the storage unit inside the chip is improved.

In some embodiments, the second switch module is a PMOS transistor, and the average current I _ ck2 of the current path between the SCLK pin and the GND pin is the sum of the average current I _ ck2_ PN passing through the parasitic PN junction of the PMOS transistor and the average current I _ ck2_ pm passing through the channel of the NMOS transistor.

In some embodiments, the SCLK pin wire bonding equivalent inductance does not have a direct significant impact on the power supply disturbance of the VCC pin and the GND pin.

The above description and drawings sufficiently illustrate embodiments of the disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others. The embodiments of the present disclosure are not limited to the structures that have been described above and shown in the drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A pin input circuit, comprising:

the clock port is used for providing clock signals for the first capacitor, the second capacitor and the buffer;

a first input end of the first capacitor is respectively connected with the clock port, a second output end of the second capacitor and a fifth input end of the buffer, and a first output end of the first capacitor is connected with a third input end of the first switch module; the first capacitor is used for providing voltage for a third input end of the first switch module so as to trigger the first switch module to be conducted;

the second output end of the second capacitor is connected with a clock port, the first input end of the first capacitor and the fifth input end of the buffer respectively, and the second input end of the second capacitor is connected with the fourth output end of the second switch module; the second capacitor is used for providing voltage for a fourth output end of the second switch module so as to trigger the second switch module to be conducted;

the third input end of the first switch module is connected with the third input end of the first capacitor, and the third output end of the first switch module is connected with the power input end of the chip; the first switch module is used for conducting a circuit between the clock port and the power supply input end of the chip;

the fourth output end of the second switch module is connected with the second input end of the second capacitor, and the fourth input end of the second switch module is connected with the power supply output end of the chip; the second switch module is used for conducting a circuit between the clock port and the power supply output end of the chip;

the fifth input end of the buffer is respectively connected with a clock port, the first input end of the first capacitor and the second output end of the second capacitor, and the fifth output end of the buffer is connected with the clock port of the chip; the buffer is used for buffering the clock signal and providing the buffered clock signal to a clock port of the chip.

2. The pin input circuit according to claim 1, wherein the clock signal is a periodic square wave signal.

3. The pin input circuit according to claim 1, wherein the first switch module is a diode or a PMOS transistor.

4. The pin input circuit according to claim 3, wherein in the case that the first switch module is a PMOS transistor, the first gate of the first switch module is connected to a power output terminal of a chip.

5. The pin input circuit according to claim 4, wherein in the case that the first switch module is a PMOS transistor, the average current through the PMOS transistor is the sum of the average current through the parasitic PN junction of the PMOS transistor and the average current through the channel of the PMOS transistor.

6. The pin input circuit according to claim 1, wherein the second switch module is a diode or an NMOS transistor.

7. The pin input circuit according to claim 6, wherein in the case that the second switch module is an NMOS transistor, the second gate of the second switch module is connected to a power input terminal of a chip.

8. The pin input circuit according to claim 7, wherein in the case that the first switch module is an NMOS transistor, the average current through the NMOS transistor is the sum of the average current through the parasitic PN junction of the NMOS transistor and the average current through the channel of the NMOS transistor.

9. A chip comprising a clock port, a power input, a power output and a pin input circuit as claimed in any one of claims 1 to 8.

10. The chip of claim 9, wherein the pin input circuit comprises:

the clock port is connected with an SCLK pin of the chip; the first capacitor, the second capacitor and the buffer are provided with clock signals;

the third input end of the first switch module is connected with the first output end of the first capacitor, and the third output end of the first switch module is connected with a VCC (voltage to current converter) pin of the chip; the first switch module is used for conducting a circuit between the clock port and the power supply input end of the chip;

the fourth output end of the second switch module is connected with the second input end of the second capacitor, and the fourth input end of the second switch module is connected with the GND pin of the chip; the second switch module is used for conducting a circuit between the clock port and the power supply output end of the chip;