CN114361057A

CN114361057A - Defect detection method for semiconductor device and electronic equipment

Info

Publication number: CN114361057A
Application number: CN202111619470.2A
Authority: CN
Inventors: 李鸿智; 陈昌言
Original assignee: Guangzhou Yuexin Semiconductor Technology Co Ltd
Current assignee: Guangzhou Yuexin Semiconductor Technology Co Ltd
Priority date: 2021-12-27
Filing date: 2021-12-27
Publication date: 2022-04-15

Abstract

The invention provides a defect detection method for rapidly detecting whether defects exist in a metal silicide layer of a semiconductor device at multiple points, which is applied to the field of semiconductors. The existing TEM detection for detecting the defect problem of the metal silicide layer is replaced by YE online detection, so that the problem that one point or a plurality of points of one chip in a wafer can be detected at one time by the TEM detection method and a plurality of points on a plurality of chips on the same wafer cannot be detected simultaneously is solved. Since the YE online inspection is an inspection method using chip-to-chip, then, the inspection images of a plurality of chips are compared, and a place where there is a difference is determined as an abnormal position. Therefore, the detection method provided by the invention avoids the problems that the wafer needs to be sliced to be made into a wafer sample wafer for TEM detection, and the sample wafer can not be continuously subjected to subsequent experiments, so that the method is not economical and practical, and the single variable of the test cannot be maintained.

Description

Defect detection method for semiconductor device and electronic equipment

Technical Field

The present invention relates to the field of semiconductor manufacturing, and in particular, to a method for detecting defects of a semiconductor device and an electronic device.

Background

As semiconductor process sizes become smaller and smaller, failure analysis becomes more difficult, and a small defect may cause device failure, thereby affecting the operation of the whole chip. For example, when a semiconductor is in contact with a metal, a barrier layer is often formed to be a non-rectifying contact, i.e., an ohmic contact. The contact resistance of an ideal ohmic contact should be small compared to a semiconductor sample or device so that when current flows through the sample or device, the voltage drop across the ohmic contact should be much less than the voltage drop across the sample or device itself, and such contact does not affect the current-voltage characteristics of the device. Currently, a good ohmic contact is formed by doping a semiconductor with a high concentration of impurities. The refractory metal cobalt (Co) reacts with silicon to generate a metal-silicide with thermal stability, and the interface of the silicon/refractory metal has low resistivity, so that the contact resistance of a connecting point of a source (Source), a Drain (Drain) and a grid (Gate) is greatly reduced.

Currently, a conventional method for detecting whether Co silicide metallization is abnormal is to perform TEM (Transmission Electron Microscope) inspection on a wafer on which a metal normalization is formed, and obtain a slice image of a detection point in a vertical direction through the TEM to determine whether the metallization is abnormal. The working principle of TEM detection is that a sample wafer to be detected is thinned in the modes of cutting, grinding, ion thinning and the like, then the sample wafer is placed into a TEM observation chamber, one point or a plurality of points of one chip in a sample wafer are irradiated by high-pressure accelerated electron beams, the appearance of the sample wafer is amplified, projected onto a screen, photographed and analyzed.

Based on the principle of TEM examination, there are several disadvantages in TEM examination:

1. TEM inspection can only detect one or a few points on one chip on one wafer at a time, which cannot simultaneously obtain the metallization of a large number of locations of one chip in the same wafer;

2. the metallization condition can not be detected aiming at multiple positions of graphs with various complexity in the same chip;

3. the TEM has long feedback time, and the detection result can be obtained only in 1 to 2 days at least;

4. the TEM inspection requires slicing of the wafer or chip, so that the experimental wafer or chip cannot be used for subsequent experiments, which is not economical and practical, and the single variable of the experiment cannot be maintained.

Disclosure of Invention

The invention aims to provide a defect detection method of a semiconductor device, which is used for realizing the rapid and multi-point detection of whether a metal silicide layer formed on a plurality of chips in a wafer has defects.

In a first aspect, to solve the above technical problem, the present invention provides a method for detecting defects of a semiconductor device, including the steps of: providing a wafer, wherein the wafer comprises a plurality of chips, and each chip is provided with a metal silicide layer stacked on the corresponding position of an active region.

And sampling the wafer by using the YE sampling rate set in the YE online detection machine to obtain a defect detection sample.

And carrying out YE online defect detection on the defect detection sample by utilizing the YE online detection machine, and respectively generating an SEM image and an EDX elemental analysis chart of the defect detection sample.

And determining whether the metal silicide layer of each chip in the defect detection sample has defects according to the comparison relationship between the SEM image and the reference SEM image and/or the comparison relationship between the EDX elemental analysis chart and the reference EDX elemental analysis chart.

Further, the material of the metal silicide layer may include one or more of titanium silicide, cobalt silicide, nickel silicide, or molybdenum silicide.

Further, the step of sampling the wafer by using the YE sampling rate set in the YE online detection machine to obtain the defect detection sample may include: and selecting a preset number of chips from the wafer as a to-be-detected chip set, and using a selected area of at least one chip selected from the to-be-detected chip set as a target detection area of the chip.

And determining the position information of the target detection area of each chip in the to-be-detected chip set according to the position information of the target detection area of the chip and the preset position relationship between the chips in the to-be-detected chip set.

And taking each chip in the to-be-detected chip set and the target detection area of each chip as the defect detection sample.

Further, the step of performing YE online defect detection on the defect detection sample by using the YE online detection machine may include: and sequentially carrying out electronic scanning on the target detection area of each chip in the defect detection sample by using the YE online detection machine table so as to obtain the SEM image of the target detection area of each chip.

And sequentially carrying out electronic scanning on the target detection area of each chip in the defect detection sample by using an EDX chart spectrometer in the YE online detection machine so as to obtain an EDX elemental analysis chart of the target detection area of each chip.

Further, the step of determining whether the metal silicide layer of each chip in the defect detection sample has defects according to the comparison relationship between the SEM image and the reference SEM image and/or the comparison relationship between the EDX elemental analysis chart and the reference EDX elemental analysis chart may include: and comparing the SEM image of the target detection area of each chip with the reference SEM image, and selecting the chips with the SEM images of the target detection areas of all the chips inconsistent with the reference SEM image.

And aiming at each selected chip, comparing the EDX elemental analysis chart of the selected chip with the reference EDX elemental analysis chart, and determining the chip with the metal content lower than a preset threshold value in the EDX elemental analysis chart of the selected chip as the chip with the defect metal silicide layer.

Further, the reference SEM image may be an SEM image of a predetermined metal silicide layer not including a defective chip, or may be an SEM image of a chip in the defect inspection sample.

Further, the reference EDX elemental analysis map may be an EDX elemental analysis map of a chip in which the predetermined metal silicide layer does not include a defect, or may be an EDX elemental analysis map of a chip in the defect detection sample.

Further, the step of forming a metal silicide layer stacked on the corresponding position of the active region on the chip may include: the chip comprises a substrate, and a grid structure is formed on the surface of the substrate.

And respectively forming a source region and a drain region in the substrate at two sides of the gate structure.

And forming a metal layer on the surface of the substrate, and carrying out a silicification reaction on the substrate so as to form metal silicide layers on the source region, the drain region and the top surface of the gate structure respectively.

Further, the substrate may be a silicon substrate.

In a second aspect, the present invention further provides an electronic device, which includes a processor, a communication interface, a memory, and a communication bus, where the processor, the communication interface, and the memory complete communication with each other through the communication bus.

A memory for storing a computer program.

And a processor for implementing the steps of the method for detecting defects of a semiconductor device as described above when executing the program stored in the memory.

In a third aspect, the embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored, and the computer program, when executed by a processor, implements the steps of the defect detection method for any one of the semiconductor devices.

Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:

the invention provides a defect detection method for rapidly detecting whether defects exist in a metal silicide layer of a semiconductor device at multiple points. Specifically, in the defect detection method of the semiconductor device provided by the invention, the existing TEM detection for detecting the defect problem of the metal silicide layer is replaced by YE online detection, so that the problem that the TEM detection method can only detect one point or multiple points of one chip in a wafer at one time and cannot simultaneously detect multiple points on multiple chips on the same wafer is solved. Moreover, the YE online detection method introduced by the invention is a chip-to-chip detection method, and then the detection images of a plurality of chips are compared, and the position with difference is determined as an abnormal position. Therefore, the detection method provided by the invention avoids the problems that the wafer needs to be sliced to be made into a wafer sample wafer for TEM detection, and the sample wafer can not be continuously subjected to subsequent experiments, so that the method is not economical and practical, and the single variable of the test cannot be maintained.

Furthermore, in the defect detection method of the semiconductor device, YE online detection and EDX element content comparative analysis are combined, so that quantitative analysis is performed on an SEM image obtained by YE online detection through EDX element content analysis, and the problem of metal silicide abnormality of multiple points of multiple chips in a wafer can be accurately and quickly determined.

Drawings

Fig. 1a to 1d are two SEM images comparing the same pattern area of different wafers under different test conditions provided in an embodiment of the present invention, fig. 1a and 1b, and EDX elemental analysis diagrams corresponding to the same pattern area of different wafers, fig. 1c and 1d, respectively.

Fig. 2 is a flowchart illustrating a method for detecting defects of a semiconductor device according to an embodiment of the present invention.

Detailed Description

As described in the background art, in the conventional method for detecting whether or not metallization of Co silicide is abnormal, TEM (Transmission Electron Microscope) inspection is performed on a wafer on which a metal-normalized material is formed, and a slice image in a vertical direction of a detection point is obtained by TEM to determine whether or not the metallization is abnormal. The working principle of TEM detection is that a sample wafer to be detected is thinned in the modes of cutting, grinding, ion thinning and the like, then the sample wafer is placed into a TEM observation chamber, one point or a plurality of points of one chip in a sample wafer are irradiated by high-pressure accelerated electron beams, the appearance of the sample wafer is amplified, projected onto a screen, photographed and analyzed.

In response to this problem, the present inventors found that: when the high-energy electron beam continuously irradiates the surface of the wafer, the high-energy incident electrons bombard out nuclear electrons of atoms to generate secondary electrons. The number of extra-nuclear electrons is different for different materials, the number and density of the generated secondary extra-nuclear electrons are greatly different, and the signals are received by corresponding receptors to generate corresponding characteristic images, such as SEM images, through amplification, modulation and the like. Therefore, the generated images and the results of the element analysis are different for different materials and contents.

Exemplary SEM image contrast maps of the same pattern area of different wafers under different test conditions as shown in fig. 1a and 1b, and EDX elemental analysis of the pattern position corresponding to fig. 1a fig. 1c and EDX elemental analysis of the pattern position corresponding to fig. 1b fig. 1 d. As can be seen from fig. 1a and 1b, the metal silicide layer in fig. 1b has more different white spots than in fig. 1a, and thus the metallization degree of the pattern structure corresponding to fig. 1a is better than that in fig. 1 b. As can be seen from fig. 1c and 1d, the metal silicide formed on the pattern structure corresponding to fig. 1c has a metal content (620) higher than the metal silicide formed on the pattern structure corresponding to fig. 1d (310), and thus the metallization degree of the pattern structure corresponding to fig. 1c is better than that of fig. 1 d.

Meanwhile, the scanning principle adopted by the YE online detection method is a chip-to-chip scanning principle, namely, the YE online high-energy electron beam can continuously irradiate one point, a plurality of points or the surface of the whole chip, so that an SEM image obtained by utilizing the YE online detection machine can contain the multi-position morphology state of various complex graphs on one chip.

Therefore, the researchers of the invention provide a scheme for combining YE online detection and EDX element content comparative analysis, so that quantitative analysis is carried out on an SEM image obtained by YE online detection through EDX element content analysis, and the problem of metal silicide abnormality of a plurality of points of a plurality of chips in a wafer can be accurately and rapidly determined.

In summary, the present invention provides a method for detecting defects of a semiconductor device, so as to achieve a fast and multi-point detection of defects in metal silicide layers formed on a plurality of chips in a wafer.

The method for detecting defects of a semiconductor device according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.

As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements. In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

Referring to fig. 2 in particular, fig. 2 is a schematic flowchart of a method for detecting defects of a semiconductor device according to an embodiment of the present invention. Specifically, the defect detection method of the semiconductor device at least comprises the following steps:

step S100, providing a wafer, where the wafer includes a plurality of chips, and each of the chips has a metal silicide layer stacked on a corresponding position of an active region of the chip.

In this embodiment, a wafer (chip) may be provided, wherein the wafer may include a plurality of chips, for example, 20 chips, and all the chips on the wafer have the same pattern formed thereon. Illustratively, each of the chips in the embodiments of the present invention may have a metal silicide layer stacked on a corresponding position of the active region thereof. Specifically, the manner of forming the metal silicide layer on each chip may be: the chip comprises a substrate, wherein a grid structure is formed on the surface of the substrate; forming a source region and a drain region in the substrate on two sides of the grid structure respectively; and forming a metal layer on the surface of the substrate, and carrying out a silicification reaction on the substrate so as to form metal silicide layers on the source region, the drain region and the top surface of the gate structure respectively.

Wherein, the material of the metal silicide layer can comprise one or more of titanium silicide, cobalt silicide, nickel silicide or molybdenum silicide. Illustratively, the material of the metal silicide layer formed on all the chips in the embodiment of the present invention is cobalt silicide.

And S200, sampling the wafer by using the YE sampling rate set in the YE online detection machine to obtain a defect detection sample.

In this embodiment, one, a plurality of or all of the chips in the wafer provided in step S100 may be selected as the defect detection sample according to actual conditions.

As an embodiment, the invention provides a specific method for sampling the wafer to obtain the defect detection sample, which is as follows: selecting a preset number of chips from the wafer as a to-be-detected chip set, and using a selected area of at least one chip selected from the to-be-detected chip set as a target detection area of the chip; determining the position information of the target detection area of each chip in the chip set to be detected according to the position information of the target detection area of the chip and the preset position relationship between the chips in the chip set to be detected; and taking each chip in the to-be-detected chip set and the target detection area of each chip as the defect detection sample.

Specifically, since the relative positions of the chips on the wafer including the chips are fixed, and any position on each chip corresponds to a coordinate position, the position of a point on one chip (the first chip) can be selected to calculate the coordinate information of other chips on the same wafer and the same position (point) on the first chip. Therefore, after determining the wafer to be subjected to defect detection in the embodiment of the present invention, a plurality of chips may be selected from the wafer, for example, 17 (other number) chips may be selected from the middle, the edge, and other positions of the wafer as a to-be-detected chip set, then one chip is selected from the to-be-detected chip set, that is, 17 chips, and then a selected area (an area where a detection defect may exist) on one chip is used as a target detection area of the chip. Then, the YE online detection machine is used to determine the coordinate information (position information) of the target detection area of the chip, and then, the coordinate information of the same position (target detection area) of the rest 16 chips as the chip for which the coordinate information was just determined is calculated by using the coordinate information of the target detection area of the chip and the position relationship between the chips in the set of chips to be detected, that is, the coordinate information of the target detection area to be YE online detected of each of the 17 chips in the set of chips to be detected can be obtained by the above formula.

And step S300, carrying out YE online defect detection on the defect detection sample by using the YE online detection machine, and respectively generating an SEM image and an EDX elemental analysis chart of the defect detection sample.

In this embodiment, after the coordinate information of the target detection area of each chip in the defect detection sample is determined in step S200, the YE online detection machine may be used to sequentially perform electronic scanning on the target detection area of each chip in the defect detection sample to obtain an SEM image of the target detection area of each chip; and then, sequentially carrying out electronic scanning on the target detection area of each chip in the defect detection sample by using an EDX chart spectrometer in the YE online detection machine table to obtain an EDX elemental analysis chart of the target detection area of each chip.

It is understood that the SEM image and the EDX elemental analysis chart formed for each of the chips in the defect detection sample in the defect detection method of a semiconductor device provided by the present invention are images obtained for the same position (target detection region) of the chip, respectively. Obviously, the defect detection method provided by the invention introduces YE online detection, so that the problem that only one point or a plurality of points of one chip in a wafer can be detected at one time by using a TEM detection method, but a plurality of points on a plurality of chips on the same wafer cannot be detected simultaneously by using the TEM detection method can be solved.

And step S400, determining whether the metal silicide layer of each chip in the defect detection sample has defects according to the comparison relationship between the SEM image and the reference SEM image and/or the comparison relationship between the EDX elemental analysis diagram and the reference EDX elemental analysis diagram.

The reference SEM image may be an SEM image of a predetermined metal silicide layer not including a defective chip, or the reference SEM image may be an SEM image of a chip in the defect inspection sample. And the reference EDX elemental analysis map may be an EDX elemental analysis map of a chip in which the predetermined metal silicide layer does not include a defect, or the reference EDX elemental analysis map may be an EDX elemental analysis map of a chip in the defect detection sample.

In this embodiment, for each chip in the defect detection sample, only the SEM image of the chip may be compared with the reference SEM image, and if there is a place where the SEM image of the chip is inconsistent with the reference SEM image, it indicates that there is a defect problem in the target detection area of the chip, and if there is a place where the SEM image of the chip is consistent with the reference SEM image, it indicates that there is no defect problem in the target detection area of the chip. Similarly, the EDX elemental analysis chart of the chip may be compared with the reference EDX elemental analysis chart alone, if the content of the metal element in the EDX elemental analysis chart of the chip is different from the content of the metal element in the reference EDX elemental analysis chart, it is indicated that the target detection area of the chip has the defect problem, and if the content of the metal element in the EDX elemental analysis chart of the chip is the same as the content of the metal element in the reference EDX elemental analysis chart, it is indicated that the target detection area of the chip does not have the defect problem. And the defects of each chip can be judged by simultaneously utilizing the reference SEM image and the reference EDX elemental analysis chart.

As an embodiment, the present invention provides a specific way to determine whether there is a defect in the metal silicide layer of each chip in the defect detection sample according to the comparison relationship between the SEM image and the reference SEM image and the comparison relationship between the EDX elemental analysis chart and the reference EDX elemental analysis chart, including the following steps:

and comparing the SEM image of the target detection area of each chip with the reference SEM image, and selecting the chips with the SEM images of the target detection areas of all the chips inconsistent with the reference SEM image.

In this embodiment, the SEM image of the target detection area of each chip may be compared with the reference SEM image, and if there is a place where the SEM image of the target detection area of the chip is inconsistent with the reference SEM image, it indicates that there is a defect problem in the target detection area of the chip, and if there is a match between the SEM image of the target detection area of the chip and the reference SEM image, it indicates that there is no defect problem in the target detection area of the chip. And then, performing EDX elemental analysis (EDX) image comparison on the chips with the SEM images inconsistent with the reference SEM images, so as to determine which chips in the defect detection sample have defects in the metal silicide layers formed on the chips in a secondary image comparison mode.

It should be noted that the SEM image and the reference EDX elemental analysis chart may be one SEM image or one EDX elemental analysis chart, or may be a plurality of SEM images or EDX elemental analysis charts, and the present invention is not limited in particular.

In summary, the present invention provides a method for rapidly detecting defects in a metal silicide layer of a semiconductor device at multiple points. Specifically, in the defect detection method of the semiconductor device provided by the invention, the existing TEM detection for detecting the defect problem of the metal silicide layer is replaced by YE online detection, so that the problem that the TEM detection method can only detect one point or multiple points of one chip in a wafer at one time and cannot simultaneously detect multiple points on multiple chips on the same wafer is solved. Moreover, the YE online detection method introduced by the invention is a chip-to-chip detection method, and then the detection images of a plurality of chips are compared, and the position with difference is determined as an abnormal position. Therefore, the detection method provided by the invention avoids the problems that the wafer needs to be sliced to be made into a wafer sample wafer for TEM detection, and the sample wafer can not be continuously subjected to subsequent experiments, so that the method is not economical and practical, and the single variable of the test cannot be maintained.

In addition, the embodiment of the invention also provides an electronic device, which comprises a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete mutual communication through the communication bus,

a memory for storing a computer program;

the processor is used for realizing the defect detection method of the semiconductor device provided by the embodiment of the invention when executing the program stored in the memory.

Specifically, the method for detecting defects of a semiconductor device includes: providing a wafer, wherein the wafer comprises a plurality of chips, and each chip is provided with a metal silicide layer stacked on the corresponding position of an active region.

For specific implementation and related explanation of each step of the method, reference may be made to the method embodiment shown in fig. 1, which is not described herein again.

In addition, other implementation manners of the defect detection method of the semiconductor device, which are realized by the processor executing the program stored in the memory, are the same as the implementation manners mentioned in the foregoing method embodiment section, and are not described again here.

The communication bus mentioned in the electronic device may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown, but this does not mean that there is only one bus or one type of bus.

The communication interface is used for communication between the electronic equipment and other equipment.

The Memory may include a Random Access Memory (RAM) or a Non-Volatile Memory (NVM), such as at least one disk Memory. Optionally, the memory 303 may also be at least one storage device located remotely from the aforementioned processor.

The Processor 701 may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

In still another embodiment of the present invention, there is further provided a computer-readable storage medium having stored therein instructions, which when run on a computer, cause the computer to execute the defect detection method of the semiconductor device described in any one of the above embodiments.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the invention to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the apparatus, the electronic device, and the computer-readable storage medium embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and in relation to the description, reference may be made to some portions of the description of the method embodiments.

The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.

Claims

1. A defect detection method of a semiconductor device is characterized by comprising the following steps:

providing a wafer, wherein the wafer comprises a plurality of chips, and a metal silicide layer stacked on the corresponding position of an active region of each chip is formed on each chip;

sampling the wafer by using a YE sampling rate set in a YE online detection machine to obtain a defect detection sample;

carrying out YE online defect detection on the defect detection sample by using the YE online detection machine, and respectively generating an SEM image and an EDX elemental analysis chart of the defect detection sample;

2. The method of detecting defects in a semiconductor device according to claim 1, wherein the material of the metal silicide layer comprises one or more of titanium silicide, cobalt silicide, nickel silicide, or molybdenum silicide.

3. The method of claim 1, wherein the step of obtaining the defect inspection samples by sampling the wafer at a YE sampling rate set in a YE online inspection machine comprises:

selecting a preset number of chips from the wafer as a to-be-detected chip set, and using a selected area of at least one chip selected from the to-be-detected chip set as a target detection area of the chip;

determining the position information of the target detection area of each chip in the chip set to be detected according to the position information of the target detection area of the chip and the preset position relationship between the chips in the chip set to be detected;

4. The method of claim 3, wherein the step of using the YE online inspection machine to perform YE online defect inspection on the defect inspection sample comprises:

sequentially carrying out electronic scanning on the target detection area of each chip in the defect detection sample by using the YE online detection machine to obtain an SEM image of the target detection area of each chip;

5. The method of detecting defects in a semiconductor device according to claim 4, wherein the step of determining whether the metal silicide layer of each chip in the defect detection sample has defects based on the comparison of the SEM image with the reference SEM image and/or the comparison of the EDX elemental analysis chart with the reference EDX elemental analysis chart comprises:

comparing the SEM image of the target detection area of each chip with the reference SEM image, and selecting the chips with the SEM images of the target detection areas of all the chips inconsistent with the reference SEM image;

6. The method of claim 3, wherein the reference SEM image is an SEM image of a chip with a predetermined metal silicide layer not including defects, or an SEM image of a chip in the defect inspection sample.

7. The method of detecting defects in a semiconductor device according to claim 3, wherein the reference EDX elemental analysis map is an EDX elemental analysis map of a chip in which the predetermined metal silicide layer does not include a defect, or an EDX elemental analysis map of a chip in the defect detection sample.

8. The method of detecting defects in a semiconductor device according to claim 1, wherein the step of forming a metal silicide layer stacked on the chip at a corresponding position of the active region thereof comprises:

the chip comprises a substrate, wherein a grid structure is formed on the surface of the substrate;

forming a source region and a drain region in the substrate on two sides of the grid structure respectively;

9. The defect detection method of a semiconductor device according to claim 8, wherein the substrate is a silicon substrate.

10. An electronic device is characterized by comprising a processor, a communication interface, a memory and a communication bus, wherein the processor and the communication interface are used for realizing mutual communication by the memory through the communication bus;

a memory for storing a computer program;

a processor for implementing the method steps of any of claims 1-9 when executing a program stored in the memory.