CN114361034A

CN114361034A - Low-voltage high-efficiency gallium nitride power device and manufacturing method thereof

Info

Publication number: CN114361034A
Application number: CN202111407815.8A
Authority: CN
Inventors: 马晓华; 祝杰杰; 刘思雨; 郭静姝; 宓珉瀚
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2021-11-24
Filing date: 2021-11-24
Publication date: 2022-04-15

Abstract

The invention discloses a low-voltage high-efficiency gallium nitride power device and a manufacturing method thereof, wherein the method comprises the following steps: obtaining an epitaxial substrate; electrically isolating the epitaxial substrate; etching source and drain electrode regions on the cap layer, and growing ohmic metal in the source and drain electrode regions by using a secondary epitaxial technology and a patterned etching technology to form a source electrode and a drain electrode; growing a passivation layer on the source electrode, the drain electrode and the cap layer; etching a groove area on the passivation layer, and etching the passivation layer in the groove area until a preset position forms a groove; growing a gate dielectric layer in the groove; photoetching a gate electrode region on the passivation layer and above the groove, and growing gate metal on the passivation layer in the gate electrode region and on the gate dielectric layer in the groove to form a T-shaped gate electrode; and etching the passivation layers on the source electrode and the drain electrode until reaching the source electrode and the drain electrode, and respectively growing interconnection electrodes on the source electrode, the drain electrode and the T-shaped gate electrode. The invention reduces the power consumption of the device and improves the power characteristic of the device.

Description

Low-voltage high-efficiency gallium nitride power device and manufacturing method thereof

Technical Field

The invention belongs to the technical field of microelectronics, and particularly relates to a low-voltage high-efficiency gallium nitride power device and a manufacturing method thereof.

Background

With the improvement of the development level of science and technology and society, the first and second generation semiconductor materials can not meet the requirements of electronic devices with higher frequency and higher power, and because the GaN material has wide forbidden bandwidth, high electronic saturation velocity, high breakdown field strength, high thermal conductivity and high electron mobility, the device manufactured on the basis of the GaN material has wide application in the aspects of high-temperature high-frequency and microwave power devices. Such devices have become the focus of research.

GaN-based High Electron Mobility Transistor (HEMT) devices can be classified into two types according to their threshold voltages: one type is a traditional depletion type GaN-based HEMT device, the device is in an on state even when no grid bias is applied, and the device can be turned off only by applying negative grid voltage (Vth < 0), so that the conventional GaN-based HEMT device is in a depletion type and is also called a normally-on type; the other type is an enhanced GaN-based HEMT device, which is just opposite to a depletion device, the device has positive starting voltage (Vth is more than 0), so that a radio frequency/microwave circuit can be simplified, the failure operation of a power electronic device can be avoided, more importantly, the device can be combined with the depletion device to form a Direct Coupled Field Effect Transistor logic (DCFL) digital circuit, and the application range of the GaN-based HEMT device is greatly expanded. Low voltage high efficiency gallium nitride power devices are now being used in large numbers in the radio frequency field and as low voltage high efficiency power switching devices. At present, the most common low-voltage high-efficiency gallium nitride radio-frequency power device is a radio-frequency power device based on a groove gate structure, the radio-frequency power device has low leakage current and large saturation current, and the gate length can be controlled through an etching process so as to ensure the stability of the power device. Among them, an ohmic annealing technique is often used for the ohmic contact formation of the source and drain electrodes.

However, for the rf power device with the recessed gate structure, the contact resistance is a very important criterion. At present, the conventional ohmic annealing technology needs to continuously adjust the annealing temperature and time aiming at different barrier materials and cap layer thicknesses, so that the contact resistance is not easy to control, and the power device has poor working stability and short service life.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a low-voltage high-efficiency gallium nitride power device and a manufacturing method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:

in a first aspect, an embodiment of the present invention provides a method for manufacturing a low-voltage high-efficiency gallium nitride power device, including:

obtaining an epitaxial substrate; the epitaxial substrate sequentially comprises a substrate layer, a nucleating layer, a buffer layer, an insertion layer, a barrier layer and a cap layer from bottom to top;

forming an electrical isolation of an active region on the epitaxial substrate;

etching a source electrode area and a drain electrode area on the cap layer, and growing ohmic metal on the source electrode area and the drain electrode area respectively by utilizing a secondary epitaxial technology and a graphical etching technology to form a source electrode and a drain electrode;

growing a passivation layer on the source electrode, the drain electrode and the cap layer;

etching a groove area on the passivation layer, and etching the passivation layer in the groove area until a preset position forms a groove;

growing a gate dielectric layer in the groove;

photoetching a gate electrode region on the passivation layer and above the groove, and growing gate metal on the passivation layer in the gate electrode region and on the gate dielectric layer in the groove to form a T-shaped gate electrode;

and etching the passivation layers on the source electrode and the drain electrode until reaching the source electrode and the drain electrode, and respectively growing interconnection electrodes on the source electrode, the drain electrode and the T-shaped gate electrode.

In one embodiment of the present invention, the forming of the electrical isolation of the active region on the epitaxial substrate comprises:

photoetching an electric isolation area on the cap layer;

etching the cap layer, the barrier layer and the insertion layer of the electric isolation area to part of the buffer layer in sequence by utilizing an ICP (inductively coupled plasma) etching process to form electric isolation of an active area; wherein the etching depth is 140 nm-150 nm.

photoetching an electric isolation area on the cap layer;

sequentially injecting N ions into the cap layer, the barrier layer and the insertion layer of the electric isolation region to part of the buffer layer by utilizing an ion injection process to form electric isolation of an active region; wherein the depth of implantation is 110 nm-120 nm.

In an embodiment of the present invention, the growing ohmic metal on the source electrode area and the drain electrode area respectively to form a source electrode and a drain electrode by using a double epitaxy technique and a patterned etching technique includes:

growing a mask layer on the cap layer;

photoetching a source electrode area and a drain electrode area on the mask layer;

etching the mask layer in the source electrode area and the drain electrode area until part of the buffer layer;

growing an N + GaN epitaxial layer on the buffer layer and the mask layer;

removing the mask layer and the N + GaN epitaxial layer on the cap layer by wet etching;

photoetching an ohmic patterned region on the N + GaN epitaxial layer;

etching part of the N + GaN epitaxial layer in the ohm patterning region to form an ohm contact groove array;

and depositing ohmic metal on the N + GaN epitaxial layer and in each ohmic contact groove in the ohmic contact groove array to form the source electrode and the drain electrode.

In an embodiment of the present invention, the etching the passivation layer in the groove region until a predetermined position forms a groove includes:

etching the passivation layer in the groove region to the upper surface of the barrier layer by adopting a first etching process condition;

continuously etching part of the barrier layer in the groove region by adopting a second etching process condition; wherein the etching depth in the barrier layer is a first etching depth, and the first etching depth is 1/2 which is at most the thickness of the barrier layer;

continuously etching part of the barrier layer in the groove region to form the groove by adopting a third etching process condition; wherein the etching depth in the barrier layer is a second etching depth which is 1/4 times the first etching depth.

etching the passivation layer in the groove region to the upper surface of the barrier layer by adopting a fourth etching process condition;

and continuously etching the barrier layer in the groove region until the groove is formed on the upper surface of the buffer layer by adopting a fifth etching process condition.

In an embodiment of the present invention, the growing a gate dielectric layer in the groove includes:

and forming a gate dielectric layer with the thickness of 2 nm-7 nm in the groove by in-situ oxidation at the temperature of 250-300 ℃ by using plasma enhanced atomic layer deposition equipment and a thermal oxidation process.

and growing a gate dielectric layer with the thickness of 1 nm-10 nm in the groove at the temperature of 250-300 ℃ by utilizing atomic layer deposition equipment.

In a second aspect, an embodiment of the present invention provides a low-voltage high-efficiency gallium nitride power device, including:

an epitaxial substrate; the epitaxial substrate sequentially comprises a substrate layer, a nucleating layer, a buffer layer, an insertion layer, a barrier layer and a cap layer from bottom to top;

a source electrode and a drain electrode at both ends of the buffer layer penetrating the cap layer, the barrier layer, and the insertion layer; an N + GaN epitaxial layer is respectively arranged between the source electrode and the buffer layer and between the drain electrode and the buffer layer, an ohmic contact groove array is arranged on the N + GaN epitaxial layer, and each ohmic contact groove in the ohmic contact groove array is filled with ohmic metal;

a passivation layer on the source electrode, the drain electrode and the cap layer;

a T-shaped gate electrode comprising a first portion and a second portion flush with the first portion; the first portion is located within the barrier layer at an intermediate position through the passivation layer and the cap layer; the second part is positioned at two sides of the first part and embedded into the passivation layer; a gate dielectric layer is further arranged between the first part and the barrier layer;

and the interconnection electrodes are positioned on the source electrode and the drain electrode which penetrate through the passivation layer and the T-shaped gate electrode.

In a third aspect, an embodiment of the present invention provides a low-voltage high-efficiency gallium nitride power device, including:

a T-shaped gate electrode including a first portion on the buffer layer penetrating the passivation layer, the cap layer, the barrier layer, and the insertion layer, and a second portion flush with the first portion, the second portion being located at both sides of the first portion and embedded in the passivation layer; a gate dielectric layer is further arranged between the first part and the buffer layer;

The invention has the beneficial effects that:

according to the manufacturing method of the low-voltage high-efficiency gallium nitride power device, when ohmic contact is manufactured, the secondary epitaxial technology is adopted to generate the epitaxial layer, the epitaxial layer and ohmic metal form ohmic contact, and meanwhile ohmic graphical etching is combined, so that the ohmic metal contact area is increased, ohmic contact resistance is further reduced, parasitic capacitance is reduced, power consumption of the device is reduced, and the frequency characteristic of the device is improved.

Aiming at various reliability problems of the existing gallium nitride power device, the method for manufacturing the gallium nitride power device can improve the reliability of the device, has very important significance for manufacturing various low-voltage high-efficiency gallium nitride power devices, and has wide prospect in low-voltage and high-efficiency application of the device.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

Fig. 1 is a schematic flow chart of a method for manufacturing a low-voltage high-efficiency gallium nitride power device according to an embodiment of the present invention;

fig. 2(a) -2 (o) are schematic structural diagrams corresponding to the manufacturing process of the low-voltage high-efficiency gallium nitride power device according to the embodiment of the invention;

fig. 3 is a schematic structural diagram of an embodiment of the present invention illustrating a corresponding electrical isolation process implemented by an ion implantation process;

FIG. 4 is a schematic diagram of another structure corresponding to a groove etch provided in an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a low-voltage high-efficiency gan power device according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of another low-voltage high-efficiency gallium nitride power device according to an embodiment of the present invention.

Description of reference numerals:

1-a substrate layer; 2-a nucleation layer; 3-a buffer layer; 4-an intervening layer; 5-a barrier layer; 6-a cap layer; 7-a source electrode; 8-a drain electrode; a 9-N + GaN epitaxial layer; 10-a passivation layer; 11-a gate dielectric layer; a 12-T shaped gate electrode; 13-an interconnected electrode; mask layer 14.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.

Example one

In order to reduce the power consumption of the device and improve the power characteristics of the device, the embodiment of the invention provides a low-voltage high-efficiency gallium nitride power device and a manufacturing method thereof.

In a first aspect, referring to fig. 1, an embodiment of the present invention provides a method for manufacturing a low-voltage high-efficiency gallium nitride power device, including the following steps:

s10, obtaining an epitaxial substrate; the epitaxial substrate comprises a substrate layer 1, a nucleation layer 2, a buffer layer 3, an insertion layer 4, a barrier layer 5 and a cap layer 6 from bottom to top in sequence.

Specifically, referring to fig. 2(a), the epitaxial substrate selected in the embodiment of the present invention sequentially includes, from bottom to top, a substrate layer 1, a nucleation layer 2, a buffer layer 3, an insertion layer 4, a barrier layer 5, and a cap layer 6. The epitaxial substrate may be an existing integrated epitaxial substrate, or may be manufactured by sequentially growing a nucleation layer 2, a buffer layer 3, an insertion layer 4, a barrier layer 5, and a cap layer 6 on a substrate layer 1 by using a Metal-organic Chemical Vapor DePosition (MOCVD) process.

Preferably, the substrate layer 1 comprises sapphire or SiC or Si with a thickness of 400 to 500 μm; the nucleating layer 2 comprises AlN with the thickness of 160 nm-180 nm; the buffer layer 3 comprises GaN with the thickness of 1.3-2 mu m; the insertion layer 4 comprises AlN with the thickness of 0-1 nm; the barrier layer 5 comprises AlGaN or AlN or InAlN or ScAlN or InAlGaN with the thickness of 3 nm-20 nm; the cap layer 6 includes GaN having a thickness of 2nm to 6 nm.

And S20, forming electric isolation of the active region on the epitaxial substrate.

Referring specifically to fig. 2(b), an alternative embodiment of the present invention provides an alternative method for forming electrical isolation of active regions on an epitaxial substrate, comprising:

and S201, photoetching an electric isolation region on the cap layer 6.

Specifically, first, the sample was baked on a hot plate at 200 ℃ for 5 min; then, coating and spin coating the photoresist at a spin coating speed of 3500 rpm/mim, and baking the sample on a hot plate at 90 deg.C for 1 min; then, putting the sample into a photoetching machine to expose the photoresist in the electric isolation area; and finally, putting the exposed sample into a developing solution to remove the photoresist in the electric isolation area, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist.

S202, sequentially etching the cap layer 6, the barrier layer 5 and the insertion layer 4 of the electric isolation region to part of the buffer layer 3 by utilizing an ICP (inductively coupled plasma) etching process to form electric isolation of the active region; wherein the etching depth is 140 nm-150 nm.

Specifically, firstly, a cap layer 6, a barrier layer 5, an insertion layer 4 and a part of a buffer layer 3 in an electrical isolation region are etched in sequence by utilizing an Inductively Coupled Plasma (ICP) process to realize mesa isolation of an active region, wherein the total etching depth is 140 nm-150 nm; then, sequentially putting the sample into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the electrical isolation region; finally, the sample was rinsed with ultra pure water and blown dry with nitrogen.

Referring to fig. 3, an alternative embodiment of the present invention provides an alternative method for forming an electrical isolation of an active region on an epitaxial substrate, comprising:

s20-1, an electrically isolated region is photo-etched on the cap layer 6.

Specifically, the sample is first baked on a hot plate at 200 ℃ for 5 min; then, coating and spin coating the photoresist, wherein the spin coating thickness is 2 microns, and placing the sample on a hot plate at 90 ℃ for baking for 1 min; and finally, putting the exposed sample into a developing solution to remove the photoresist in the electric isolation region, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist.

S20-2, implanting N ions into the cap layer 6, the barrier layer 5 and the insertion layer 4 of the electric isolation region to part of the buffer layer 3 in sequence by using an ion implantation process to form electric isolation of the active region; wherein the depth of implantation is 110 nm-120 nm.

Specifically, firstly, N ions are implanted into the cap layer 6, the barrier layer 5, the insertion layer 4 and part of the buffer layer 3 of the electric isolation region in sequence by utilizing an ion implantation process so as to realize the electric isolation of the source region, wherein the total implantation depth is 110 nm-120 nm; and then sequentially putting the sample into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the electric isolation area, and finally rinsing the sample with ultrapure water and drying the sample with nitrogen.

And S30, etching a source electrode area and a drain electrode area on the cap layer 6, and growing ohmic metal on the source electrode area and the drain electrode area respectively by utilizing a secondary epitaxial technology and a patterned etching technology to form a source electrode 7 and a drain electrode 8.

Specifically, an alternative scheme is provided in an embodiment of the present invention, including:

s301, growing a mask layer 14 on the cap layer 6.

Specifically, referring to fig. 2(c), the sample is placed in a Plasma Enhanced Chemical Vapor Deposition (PECVD) apparatus to grow the mask layer 14, wherein the process conditions for the growth are as follows: by the use of O₂And SiH₄As the reaction gas, the substrate temperature was 250 ℃, the reaction chamber pressure was 600mTorr, and the RF power was 44W.

Preferably, mask layer 14 comprises SiO with a thickness of 150nm to 200nm₂。

S302, a source electrode region and a drain electrode region are etched on the mask layer 14.

Specifically, first, the sample was baked on a hot plate at 200 ℃ for 5 min; then, glue coating and spin coating of the stripping glue are carried out on the mask layer 14, the thickness of the spin coating is 0.35 mu m, and the sample is placed on a hot plate at 200 ℃ to be baked for 5 min; then, gluing and spinning photoresist on the stripper with the thickness of 0.77 μm, and baking the sample on a hot plate at 90 deg.C for 1 min; then, putting the sample which is subjected to gluing and whirl coating into a photoetching machine to expose the photoresist in the source electrode area and the drain electrode area; and finally, putting the exposed sample into a developing solution to remove the photoresist and the stripping glue in the source electrode area and the drain electrode area, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist and the stripping glue.

And S303, etching the mask layer 14 in the source electrode region and the drain electrode region until part of the buffer layer 3.

Specifically, referring to fig. 2(d), first, a sample of the photolithographic patterns of the active electrode 7 and the drain electrode 8 is etched in an ICP etcher using an etching condition: the reaction gas being CF₄And O₂The pressure of the reaction chamber is 10mTorr, the radio frequency power of the upper electrode and the lower electrode is 100W and 10W respectively, and the mask layer 14 and the cap layer 6 are etched until the upper surface of the barrier layer 5; and then another etching condition is utilized: the reaction gas is Cl₂And BCl₃The pressure of the reaction chamber is 5mTorr, the radio frequency power of the upper electrode and the radio frequency power of the lower electrode are 150W and 50W respectively, the etching is carried out until part of the buffer layer 3 is etched, and the etching depth in the buffer layer 3 is 10 nm-20 nm; and cleaning the photoresist on the surface of the etched sample.

And S304, growing the N + GaN epitaxial layer 9 on the buffer layer 3 and the mask layer 14.

Specifically, referring to fig. 2(e), the sample is placed in an MOCVD apparatus, and the N + GaN epitaxial layer 9 is grown, i.e., secondary epitaxy, on the buffer layer 3 and the mask layer 14 by using an MOCVD process, and specifically, the N + GaN epitaxial layer 9 with a thickness of 100nm to 200nm is grown on the buffer layer 3 and the mask layer 14.

And S305, removing the mask layer 14 and the N + GaN epitaxial layer 9 on the cap layer 6 by adopting wet etching.

Specifically, referring to fig. 2(f), the sample is placed in a Buffered Oxide Etch (BOE) solution for wet etching, the mask layer 14 on the cap layer 6 is etched away, and the N + GaN epitaxial layer 9 covering the mask layer 14 falls off along with the mask layer 14. The etching process conditions are as follows: BOE solution was prepared from 49% aqueous HF: 40% NH₄F aqueous solution 1: 6 (volume ratio) and the corrosion time is 3 min.

And S306, photoetching an ohmic patterned region on the N + GaN epitaxial layer 9.

Specifically, an ohmic patterned region was etched on the N + GaN epitaxial layer 9 by a method of photolithography of a source electrode region and a drain electrode region in S302.

And S307, etching part of the N + GaN epitaxial layer 9 in the ohmic patterning region to form an ohmic contact groove array.

Specifically, referring to fig. 2(g), an ICP etching process is used to remove a portion of the N + GaN epitaxial layer 9 in the ohmic patterned region, wherein the etching conditions are as follows: the reaction gas being CF₄And O₂The pressure of the reaction chamber is 10mTorr, the radio frequency power of the upper electrode and the radio frequency power of the lower electrode are 100W and 10W respectively, an ohmic contact groove array is formed in the N + GaN epitaxial layer 9 through the etching part, and the etching depth in the N + GaN epitaxial layer 9 ranges from 50nm to 80 nm. The ohmic contact groove array comprises a plurality of ohmic contact grooves, the surface shape of each ohmic contact groove can be circular, rectangular and the like, and the specific shape is not limited.

And S308, depositing ohmic metal in each ohmic contact groove in the N + GaN epitaxial layer 9 and the ohmic contact groove array to form a source electrode 7 and a drain electrode 8.

Specifically, referring to fig. 2(h), firstly, a sample with a photo-etching pattern of the active electrode 7 and the drain electrode 8 is placed in a plasma resist remover for base film treatment, wherein the treatment time is 5 min; then, the sample is put into an electron beam evaporation table until the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10^-6After Torr, ohmic metal is evaporated on the N + GaN epitaxial layer 9 in the source electrode region and the drain electrode region and on the photoresist outside the source electrode region and the drain electrode region in each ohmic contact groove in the ohmic contact groove arrayThe M metal is a metal stack structure which is sequentially composed of four layers of metals of Ti, Al, Ni and Au from bottom to top; then, stripping the sample after the ohmic metal evaporation is completed so as to remove the ohmic metal, the photoresist and the stripping glue outside the source electrode area and the drain electrode area; finally, the sample was rinsed with ultra pure water and blown dry with nitrogen.

In the embodiment S30 of the present invention, when the secondary epitaxy method is adopted, the requirements on the selection of the mask layer 14, the growth process of the N + GaN epitaxial layer 9, and the selection of the ohmic metal evaporated on the N + GaN epitaxial layer 9 are very strict. In the process of manufacturing the process, because of the need of selective area growth, the mask layer 14 needs to be added, and the mask layer 14 needs to be made of a mask material which is not denatured at high temperature and is easy to peel off, so that the growth quality of the N + GaN epitaxial layer 9 can be ensured; the quality of the source electrode 7 and the drain electrode 8 can be seriously influenced by over-thickness or over-thinness of the N + GaN epitaxial layer 9, the growth thickness of the N + GaN epitaxial layer 9 is preferably 100 nm-200 nm, and meanwhile, BOE solution with proper proportion is adopted to etch the surface of the N + GaN epitaxial layer 9 after growth, so that the growth quality of the N + GaN epitaxial layer 9 is improved; when ohmic metal is grown on the N + GaN epitaxial layer 9, there is also a requirement on metal selection, and the ohmic metal must include Ni metal with good adhesion and Au, which is more conductive in the upper layer.

And S40, growing a passivation layer 10 on the source electrode 7, the drain electrode 8 and the cap layer 6.

In particular, embodiments of the present invention provide an alternative to growing a passivation layer 10 on the source electrode 7, the drain electrode 8 and the cap layer 6, including:

s401, cleaning the surface of the sample after the growth of the active electrode 7 and the drain electrode 8 is completed.

Specifically, firstly, a sample after the growth of the active electrode 7 and the drain electrode 8 is completed is placed in an acetone solution for ultrasonic cleaning for 3mim, and the ultrasonic intensity is 3.0; then, putting the sample into stripping liquid with the temperature of 60 ℃ for water bath heating for 5 min; then, the sample is sequentially placed into an acetone solution and an ethanol solution for ultrasonic cleaning for 3min, and the ultrasonic intensity is 3.0; finally, the sample was rinsed with ultra pure water and blown dry with nitrogen.

S402, growing a passivation layer 10 on the source electrode 7, the drain electrode 8 and the cap layer 6.

Specifically, referring to fig. 2(i), the sample is placed in a PECVD apparatus, and a passivation layer 10 is grown on the source electrode 7, the drain electrode 8 and the cap layer 6 of the active region by using a PECVD process, wherein the growth process conditions are as follows: by NH₃And SiH₄As the reaction gas, the substrate temperature was 250 ℃, the reaction chamber pressure was 600mTorr, and the RF power was 22W.

Preferably, the passivation layer 10 comprises SiN with a thickness of 100nm to 120 nm.

And S50, etching a groove area on the passivation layer 10, and etching the passivation layer 10 in the groove area until a groove is formed at a preset position.

Specifically, an alternative scheme is provided, in which a groove region is etched on the passivation layer 10, and the passivation layer 10 in the groove region is etched until a groove is formed at a predetermined position, where the alternative scheme includes:

and S501, etching a groove region on the passivation layer 10.

Specifically, first, the sample was baked on a hot plate at 200 ℃ for 5 min; then, coating and spin coating the photoresist at a spin coating speed of 3500 rpm/mim, and baking the sample on a hot plate at 90 deg.C for 1 min; then, putting the sample into a photoetching machine to expose the photoresist in the groove area; finally, the exposed sample is put into a developing solution to remove the photoresist in the groove area, and the photoresist is washed by ultrapure water and dried by nitrogen.

And S502, etching the passivation layer 10 in the groove area to the upper surface of the barrier layer 5 by adopting the first etching process condition.

Specifically, referring to fig. 2(j), placing the sample into an ICP etching machine, removing the passivation layer 10 and the cap layer 6 in the groove region by using an ICP etching process, and etching by using a first etching process, wherein the etching conditions are as follows: the reaction gas being CF₄And O₂The pressure of the reaction chamber is 10mTorr, the radio frequency power of the upper electrode and the lower electrode is 100W and 10W respectively, and the etching is carried out until the upper surface of the barrier layer 5.

S503, continuing to etch part of the barrier layer 5 in the groove area by adopting a second etching process condition; wherein the etching depth in the barrier layer 5 is the first etching.

Specifically, referring to fig. 2(k), the etching conditions are changed, the ICP etching machine uses the second etching process conditions to achieve the fast etching, and the barrier layer 5 in the groove region is continuously etched, and the specific fast etching conditions are as follows: the reaction gas is Cl₂And BCl₃The pressure of the reaction chamber is 5mTorr, the radio frequency powers of the upper electrode and the lower electrode are 300W and 75W respectively, the etching depth is a first etching depth, specifically the first etching depth is at most 1/2 of the thickness of the barrier layer 5, for example, when the thickness of the barrier layer 5 is 20nm, the first etching depth can be 8nm, and the residual thickness of the barrier layer 5 in the corresponding groove region is 12 nm.

S504, continuing to etch part of the barrier layer 5 in the groove area to form a groove by adopting a third etching process condition; wherein the etching depth in the barrier layer 5 is a second etching depth which is 1/4 times the first etching depth.

Specifically, referring to fig. 2(l), the etching condition is changed again, the ICP etching machine uses the third etching process condition to realize the low loss recovery, and the barrier layer 5 in the groove region is continuously etched to form the groove, and the specific low damage repair condition is as follows: the reaction gas is O₂And BCl₃The pressure of the reaction chamber is 20mTorr, the rf powers of the upper electrode and the lower electrode are 50W and 15W, respectively, the etching depth is the second etching depth, and according to the fact that the second etching depth is 1/4 of the first etching depth, for example, when the second etching depth is 8nm, the second etching depth may be 2nm, and the remaining thickness of the barrier layer 5 in the corresponding groove region is 10 nm.

The embodiment of the present invention provides another alternative, where the step of S50 etching the passivation layer in the groove region until a groove is formed at a predetermined position includes:

and S50-1, etching the passivation layer in the groove area to the upper surface of the barrier layer 5 by adopting a fourth etching process condition.

Specifically, the embodiment of the present invention selects the first etching process condition which is the same as S502 as the fourth etching process condition, and etches the passivation layer 10 in the groove region in the ICP etcher until the upper surface of the barrier layer 5 forms the structure as shown in fig. 2 (j).

S50-2, adopting the fifth etching process condition, continuously etching the barrier layer 5 in the groove area until the groove is formed on the upper surface of the buffer layer 3.

Specifically, referring to fig. 3, by changing the etching process conditions, the embodiment of the present invention uses the third etching process condition, which is the same as S504, as the fifth etching process condition, and continues to etch the barrier layer 5 in the groove region until the groove is formed on the upper surface of the buffer layer 3 in the ICP etching machine.

Fig. 2(m) -2 (o) are schematic diagrams of the structure manufactured based on the process of fig. 2(l), which only show that the corresponding structure is manufactured based on the process of fig. 2(l), and the subsequent manufacturing processes corresponding to the grooves formed by etching through S50-1 and S50-2 are similar. Next, the following process flow of fig. 2(m) to fig. 2(o) based on fig. 2(l) will be described with emphasis.

And S60, growing a gate dielectric layer 11 in the groove.

Specifically, referring to fig. 2(i), an alternative solution is provided in the embodiments of the present invention, in which a gate dielectric layer with a thickness of 1nm to 10nm is formed in a recess by using a thermal oxidation process at a temperature of 250 ℃ to 300 ℃ and using a plasma enhanced atomic layer deposition apparatus, and the method specifically includes:

s601, cleaning the surface of the sample subjected to groove etching.

Specifically, firstly, putting a sample subjected to groove etching into an acetone solution, and ultrasonically cleaning the sample for 3mim with the ultrasonic intensity of 3.0; then, putting the sample into stripping liquid with the temperature of 60 ℃ for water bath heating for 5 min; then, the sample is sequentially placed into an acetone solution and an ethanol solution for ultrasonic cleaning for 3min, and the ultrasonic intensity is 3.0; finally, the sample was rinsed with ultra pure water and blown dry with nitrogen.

And S602, carrying out in-situ pretreatment on the barrier layer 5 of the groove region and the surface of the passivation layer 10 outside the groove region.

Specifically, the sample after surface cleaning is placed into a Plasma Enhanced Atomic Layer Deposition (PEALD) device, and the barrier Layer 5 in the groove region and the surface of the passivation Layer 10 outside the groove region are subjected to in-situ pretreatmentThe processing conditions are as follows: the reaction gas being NH₃And N₂The gas mixture, substrate temperature 300 ℃, RF power set at 200W, process time 5 min.

S603, growing an AlN medium inserting layer on the surface of the barrier layer 5 in the groove area.

Specifically, an AlN dielectric insertion layer with the thickness of 1nm to 2nm is grown on the surface of the barrier layer 5 in the groove region by using a PEALD process, and the growth process conditions are as follows: by NH₃And TMA as a reactive precursor source, the substrate temperature was 250 ℃ to 300 ℃, the RF power was set at 50W, and the reaction chamber pressure was 0.3 Torr.

And S604, oxidizing the AlN dielectric insertion layer of the groove region and the surface of the passivation layer 10 outside the groove region.

Specifically, in the PEALD process, the AlN medium insertion layer in the recess region and the surface of the passivation layer 10 outside the recess region are oxidized under the following process conditions: the reaction gas is O₂The substrate temperature was 250-300 deg.C, the RF power was set at 200W, and the processing time was 20 min.

And S605, carrying out in-situ oxidation on the AlN dielectric insertion layer of the groove region and the passivation layer 10 outside the groove region by utilizing a thermal oxidation process to form a gate dielectric layer 11.

Specifically, on the AlN dielectric insertion layer of the groove region and the passivation layer 10 outside the groove region, by using PEALD equipment, Al with the thickness of 2 nm-5 nm is formed on the AlN dielectric insertion layer by in-situ oxidation through a thermal oxidation process₂O₃A high-k dielectric layer consisting of an AlN dielectric insertion layer and Al₂O₃The high-k dielectric layers jointly form a gate dielectric layer 11, and are oxidized in situ on the passivation layer 10 to form SiO₂The passivation layer 10 is grown under the following process conditions: by the use of O₂And TMA as a reactive precursor source, the substrate temperature was 250 ℃ to 300 ℃, the RF power was set at 100W, and the reaction chamber pressure was 0.3 Torr.

In another alternative provided by the embodiment of the present invention, S60 is to grow a gate dielectric layer 11 in the groove, including: growing a gate dielectric layer with the thickness of 2 nm-7 nm in the groove at the temperature of 250-300 ℃ by utilizing Atomic Layer Deposition (ALD) equipment, and specifically:

and S60-1, cleaning the surface of the sample after groove etching.

S60-2, carrying out in-situ pretreatment on the barrier layer 5 of the groove area and the surface of the passivation layer 10 outside the groove area.

S60-3, growing an AlN medium inserting layer on the surface of the barrier layer 5 in the groove area.

S60-4, growing HfO on AlN medium insertion layer₂A high-k dielectric layer.

S60-1-S60-3 is the same as S601-S603, and is not described herein again, except that S60-4 is used for growing HfO with a thickness of 1 nm-5 nm on the AlN dielectric insertion layer by ALD process₂The growth process conditions of the high-k dielectric layer are as follows: the source of the reactive precursor is O₃And TEMAH, the substrate temperature was 300 ℃, the reaction chamber pressure was 0.3 Torr.

And S70, photoetching a gate electrode region on the passivation layer 10 and above the groove, and growing gate metal on the gate dielectric layer 11 in the gate electrode region and on the gate dielectric layer 11 in the groove to form a T-shaped gate electrode 12.

Specifically, referring to fig. 2(n), a gate electrode region is patterned on the passivation layer 10 and above the groove, and a gate metal is grown on the passivation layer 10 in the gate electrode region and on the gate dielectric layer 11 in the groove to form a T-shaped gate electrode 12, including:

and S701, photoetching a gate electrode region on the passivation layer 10 and above the groove.

Specifically, firstly, a sample on which the growth of the gate dielectric layer 11 is completed is placed on a hot plate at 200 ℃ and baked for 5 min; then, glue spreading and spin coating of the stripping glue are carried out on the passivation layer 10 and above the groove, the spin coating thickness is 0.35 mu m, and the sample is placed on a hot plate at 200 ℃ to be baked for 5 min; then, gluing and spinning photoresist on the stripper with the thickness of 0.77 μm, and baking the sample on a hot plate at 90 deg.C for 1 min; then, putting the sample subjected to gluing and whirl coating into a photoetching machine to expose the photoresist in the gate electrode area; and finally, putting the exposed sample into a developing solution to remove the photoresist and the stripping glue in the gate electrode area, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist and the stripping glue.

And S702, growing gate metal on the passivation layer 10 in the gate electrode area and on the gate dielectric layer 11 in the groove to form a T-shaped gate electrode 12.

Specifically, firstly, a sample with a photoetching pattern of a T-shaped gate electrode 12 is placed in a plasma photoresist remover to be subjected to bottom film treatment, wherein the treatment time is 5 min; then, the sample is put into an electron beam evaporation table until the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10^-6After Torr, evaporating gate metal on the passivation layer 10 and the groove in the gate electrode region and the photoresist outside the gate electrode region, wherein the gate metal is a metal stack structure sequentially consisting of two layers of Ni and Au from bottom to top; then, stripping the sample after the gate metal evaporation is finished so as to remove the gate metal, the photoresist and the stripping glue outside the gate electrode area; finally, the sample was rinsed with ultra pure water and blown dry with nitrogen.

And S80, etching the passivation layer 10 on the source electrode 7 and the drain electrode 8 until reaching the source electrode 7 and the drain electrode 8, and growing an interconnection electrode 13 on the source electrode 7, the drain electrode 8 and the T-shaped gate electrode 12 respectively.

Specifically, referring to fig. 2(o), the passivation layer 10 on the source electrode 7 and the drain electrode 8 is etched until the source electrode 7 and the drain electrode 8, and an interconnection electrode 13 is grown on the source electrode 7, the drain electrode 8 and the T-shaped gate electrode 12, respectively, including:

and S801, photoetching a metal interconnection area on the passivation layer 10.

Specifically, the sample on which the growth of the T-shaped gate electrode 12 is completed is placed on a hot plate at 200 ℃ and baked for 5 min; coating stripping glue and throwing glue on the passivation layer 10 on the source electrode 7 and the drain electrode 8 and the T-shaped gate electrode 12, wherein the thickness of the throwing glue is 0.35 mu m, and baking the sample on a hot plate at 200 ℃ for 5 min; coating photoresist on the stripping glue and throwing the photoresist to a thickness of 0.77 mu m, and baking the sample on a hot plate at 90 ℃ for 1 min; and putting the sample subjected to gluing and whirl coating into a photoetching machine to expose the photoresist in the metal interconnection area, putting the exposed sample into a developing solution to remove the photoresist and the stripping glue in the metal interconnection area, and washing the photoresist and the stripping glue with ultrapure water and drying the photoresist with nitrogen.

And S802, etching the passivation layer 10 in the metal interconnection area to the source electrode 7 and the drain electrode 8.

Specifically, the passivation layer 10 in the metal interconnection region is removed by using an ICP etching process, and the etching conditions are as follows: the reaction gas being CF₄And O₂The pressure of the reaction chamber is 10mTorr, the radio frequency power of the upper electrode and the lower electrode is 100W and 10W respectively, the etching depth is 100 nm-120 nm, and the etching is carried out immediately until the upper surfaces of the source electrode 7 and the drain electrode 8.

And S803, evaporating interconnection metal on the source electrode 7, the drain electrode 8 and the T-shaped gate electrode 12 in the metal interconnection area to form an interconnection electrode 13.

Specifically, a sample with a metal interconnection area is placed in a plasma degumming machine for base film treatment, wherein the treatment time is 5 min; putting the sample into an electron beam evaporation table until the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10^-6After the Torr, evaporating interconnection metal on the source electrode 7, the drain electrode 8 and the T-shaped gate electrode 12 in the metal interconnection area and the photoresist outside the metal interconnection area to form an interconnection electrode 13, wherein the interconnection electrode 13 is a metal stack structure consisting of two layers of Ti and Au from bottom to top in sequence; and stripping the sample after the evaporation of the interconnection metal is completed to remove the interconnection metal, the photoresist and the stripping glue outside the metal interconnection area, washing the sample with ultrapure water and drying the sample with nitrogen to complete the manufacture of the device.

In summary, according to the method for manufacturing a low-voltage high-efficiency gallium nitride power device provided by the embodiment of the invention, when ohmic contact is manufactured, the epitaxial layer is generated by adopting the secondary epitaxial technology, the epitaxial layer and ohmic metal form ohmic contact, and simultaneously ohmic patterned etching is combined, so that the ohmic metal contact area is increased, the ohmic contact resistance is further reduced, the parasitic capacitance is reduced, the power consumption of the device is reduced, and the frequency characteristic of the device is improved.

In the groove etching process, the groove is processed by utilizing low-damage repair after rapid etching, so that fixed charges and etching damage are reduced, the scattering influence of interface charges and impurities in the groove on channel electrons is improved, and the reliability of the device is improved.

The gate dielectric layer 11 of the embodiment of the invention adopts a laminated structure consisting of an AlN dielectric insertion layer and a high-k dielectric layer, the AlN dielectric insertion layer improves the interface quality between the gate dielectric layer 11 and the cap layer 6, and the high-k dielectric layer improves the off-state leakage current and the gate control capability of the insulated gate high electron mobility transistor. Wherein the high-k dielectric layer comprises Al₂O₃High-k dielectric layer or HfO₂A high-k dielectric layer.

In the growth process of the gate dielectric layer 11, the gate dielectric layer 11 is oxidized in situ by using a thermal oxidation treatment process, and under the condition of ensuring that the height of the strong polarization nitride barrier is not reduced, part of the barrier layer 5 is oxidized into the gate dielectric layer 11, so that the problem that the interface is damaged due to etching when the gate dielectric layer 11 is grown by adopting an ALD (atomic layer deposition) process in the prior art is solved, the sheet resistance of the device is reduced, the off-state leakage current of the device can be improved through the gate dielectric layer 11, and the power characteristic of the device is improved. In the thermal oxidation treatment process, remote plasma oxidation treatment is realized by adopting Plasma Enhanced Atomic Layer Deposition (PEALD) equipment, so that the damage of the plasma to the surface of the barrier layer 5 is reduced while the oxidation speed is increased; the temperature required in the oxidation treatment process is low, namely about 250-300 ℃, so that the damage to the material caused by high-temperature conditions can be effectively avoided, the off-state leakage of the grid electrode is improved, the breakdown voltage of the device is improved, the threshold voltage of the device is improved, and the purpose of manufacturing an enhancement device is achieved.

Finally, aiming at various reliability problems of the existing gallium nitride power device, the method for manufacturing the gallium nitride power device can improve the reliability of the device, has very important significance for manufacturing various low-voltage high-efficiency gallium nitride power devices, and has wide prospect in low-voltage and high-efficiency application of the device.

In a second aspect, referring to fig. 5, an embodiment of the invention provides a low-voltage high-efficiency gan power device, including:

an epitaxial substrate; the epitaxial substrate comprises a substrate layer 1, a nucleating layer 2, a buffer layer 3, an insertion layer 4, a barrier layer 5 and a cap layer 6 from bottom to top in sequence;

a source electrode 7 and a drain electrode 8 positioned at both ends of the buffer layer 3 penetrating the cap layer 6, the barrier layer 5, and the insertion layer; an N + GaN epitaxial layer 9 is arranged between the source electrode 7 and the buffer layer 3, an N + GaN epitaxial layer 9 is arranged between the drain electrode 8 and the buffer layer, an ohmic contact groove array is arranged on the N + GaN epitaxial layer 9, and each ohmic contact groove in the ohmic contact groove array is filled with ohmic metal;

a passivation layer 10 on the source electrode 7, the drain electrode 8 and the cap layer 6;

a T-shaped gate electrode 12 including a first portion and a second portion flush with the first portion; the first part is located in the barrier layer 5 in an intermediate position through the passivation layer 10 and the cap layer 6; the second portion is located on both sides of the first portion and embedded in the passivation layer 10; a gate dielectric layer 11 is arranged between the first part and the barrier layer 5;

and an interconnection electrode 13 on the source and

drain electrodes

7 and 8 and the T-shaped gate electrode 12 penetrating the passivation layer.

The low-voltage high-efficiency gallium nitride power device is manufactured by the manufacturing method of the low-voltage high-efficiency gallium nitride power device.

In a third aspect, referring to fig. 6, an embodiment of the present invention provides a low-voltage high-efficiency gallium nitride power device, including:

a source electrode 7 and a drain electrode 8 positioned at both ends of the buffer layer 3 penetrating the cap layer 6, the barrier layer 5, and the insertion layer 4; an N + GaN epitaxial layer 9 is arranged between the source electrode 7 and the buffer layer 3, an N + GaN epitaxial layer 9 is arranged between the drain electrode 8 and the buffer layer, an ohmic contact groove array is arranged on the N + GaN epitaxial layer 9, and each ohmic contact groove in the ohmic contact groove array is filled with ohmic metal;

a T-shaped gate electrode 12 including a first portion on the buffer layer 3 penetrating the passivation layer 10, the cap layer 6, the barrier layer 5 and the insertion layer 4, and a second portion flush with the first portion, on both sides of the first portion and embedded in the passivation layer 10; a gate dielectric layer 11 is also arranged between the first part and the buffer layer 3;

and an interconnection electrode 13 on the source and

drain electrodes

7 and 8 and the T-shaped gate electrode 12 penetrating the passivation layer 10.

The low-voltage high-efficiency gallium nitride power device is manufactured by the manufacturing method of the low-voltage high-efficiency gallium nitride power device. The difference from the low-voltage high-efficiency gallium nitride power device provided by the second aspect is that the low-voltage high-efficiency gallium nitride power device provided by the second aspect is arranged in the barrier layer 5 at the preset position for manufacturing the groove etching, and the low-voltage high-efficiency gallium nitride power device provided by the third aspect is arranged on the upper surface of the buffer layer 3 at the preset position for manufacturing the groove etching.

In the low-voltage high-efficiency gallium nitride power device provided by the first aspect and the second aspect of the embodiment of the invention, the ohmic contact region adopts an ohmic contact mode formed by the N + GaN epitaxial layer 9 and ohmic metal, and simultaneously, an ohmic contact groove array is formed by combining ohmic graphical etching, so that the ohmic metal contact area is increased, the ohmic contact resistance is further reduced, the parasitic capacitance is reduced, the power consumption of the device is reduced, and the frequency characteristic of the device is improved.

In the description of the present invention, it is to be understood that the terms "first", "second" and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.

While the present application has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims

1. A method for manufacturing a low-voltage high-efficiency gallium nitride power device is characterized by comprising the following steps:

forming an electrical isolation of an active region on the epitaxial substrate;

growing a gate dielectric layer in the groove;

2. The method of claim 1, wherein said forming an electrical isolation of active regions on said epitaxial substrate comprises:

photoetching an electric isolation area on the cap layer;

3. The method of claim 1, wherein said forming an electrical isolation of active regions on said epitaxial substrate comprises:

photoetching an electric isolation area on the cap layer;

4. The method of claim 1, wherein the growing ohmic metal on the source electrode region and the drain electrode region to form a source electrode and a drain electrode respectively by using a double epitaxy technique and a patterned etching technique comprises:

growing a mask layer on the cap layer;

growing an N + GaN epitaxial layer on the buffer layer and the mask layer;

photoetching an ohmic patterned region on the N + GaN epitaxial layer;

5. The method of claim 1, wherein etching the passivation layer in the trench region to a predetermined location to form a trench comprises:

6. The method of claim 1, wherein etching the passivation layer in the trench region to a predetermined location to form a trench comprises:

7. The method of claim 1, wherein the growing a gate dielectric layer in the recess comprises:

8. The method of claim 1, wherein the growing a gate dielectric layer in the recess comprises:

and growing a gate dielectric layer with the thickness of 2nm to 7nm in the groove at the temperature of 250 ℃ to 300 ℃ by utilizing atomic layer deposition equipment.

9. A low voltage high efficiency gallium nitride power device, comprising:

10. A low voltage high efficiency gallium nitride power device, comprising: