CN114360629A - Chip testing method and device - Google Patents

Abstract

The application provides a test method of a memory chip, wherein the tested memory chip is provided with a data input/output port and a chip enabling port corresponding to a data channel, and the test method comprises the following steps: receiving a mode encoding signal from the tester from the data input/output port, the mode encoding signal including first encoding information for controlling the chip enable port; and controlling the chip enable port based on the first encoding information in the testing process. According to the testing method, the testing efficiency of the tester is improved by reducing the number of the probes occupied by a single memory chip, the capability of the tester for testing the chips in parallel is improved to a certain extent, the chip testing time is reduced, the testing efficiency is improved, and the production cost is reduced. Meanwhile, the signal crosstalk among the probes can be reduced to a certain extent by using fewer probes for chip testing, and the testing quality is improved.

Description

Chip testing method and device

Technical Field

The present disclosure relates to the field of semiconductor design and manufacturing, and more particularly, to a method and apparatus for testing chips with reduced probe usage.

Background

NAND memories are widely used in various electronic devices, such as digital cameras, usb disks, and mobile phones, due to their large capacity and high speed. As devices using NAND memories as storage media tend to be more intelligent and miniaturized, the size of the memories is continuously reduced and the integration level is continuously increased, so that the time and cost for testing the memories are increased.

In the testing process, an interface between a Device Under Test (DUT) and a tester is mainly composed of three parts, namely a data channel, a power channel and a Power Management Unit (PMU) channel, where each channel needs to be allocated with a certain number of probes for testing. The current common test is a parallel test, and a test machine can test a plurality of chips simultaneously to reduce the test time and the test cost. Common parallel tests include full probe port (full) test and ultra low probe port (ULPC) test, where in a full port test scheme, three channels (i.e., the data channel, the power channel, and the PMU channel) require, for example, 14 probe tests, and in an ULPC test scheme, the three channels require 7 probe tests, which results in long test time and high cost. On the other hand, the integration level of the memory chips is high, and the distance between every two chips is small, so that crosstalk easily exists between probes in a test process. Therefore, the memory test is performed by using fewer probes, and the problem of improving the test accuracy is to be solved quickly.

Disclosure of Invention

The present application provides a chip testing apparatus and a testing method thereof that can at least partially solve the above-mentioned problems in the prior art.

According to an aspect of the present application, there is provided a test method of a memory chip, wherein the memory chip under test has a data input/output port and a chip enable port of a corresponding data channel, the test method may include: receiving a mode encoding signal from a tester from the data input/output port, wherein the mode encoding signal comprises first encoding information for controlling the chip enable port; and controlling the chip enable port based on the first coding information in the testing process.

In one embodiment of the present application, the first encoded information of the mode encoding signal may be a four-bit binary code, and the level of the chip enable port is controlled by different four-bit binary codes.

According to an aspect of the present application, there is provided a test method of a memory chip to be tested having a data input/output port and a chip enable port of a corresponding data channel, the test method may include: generating a mode encoding signal, wherein the mode encoding signal comprises first encoding information used for controlling the chip enabling port; and sending the mode coding signal to the memory chip through a probe corresponding to the data input/output port.

In one embodiment of the present application, the first encoded information of the mode encoding signal may be a four-bit binary code, and the level of the chip enable port is controlled by different four-bit binary codes.

According to an aspect of the present application, there is provided a test method of a memory chip to be tested having a data input/output port and a chip enable port of a corresponding data channel, the test method may include: receiving a specific clock signal from a tester from the write enable port, the specific clock signal including first signal information for controlling the chip enable port; and controlling the chip enable port based on the specific clock signal in the test process.

In one embodiment of the present application, the first signal information may include: the time interval between adjacent rising and falling edges of the particular clock signal is greater than or equal to a respective threshold time.

In one embodiment of the present application, the controlling the chip enable port based on the specific clock signal during the test may include: and controlling the level of the chip enable port to change in response to the time interval between adjacent rising edges and falling edges of the specific clock signal being greater than or equal to the corresponding threshold time.

In one embodiment of the present application, a time interval between a first falling edge of the specific clock signal and a rising edge consecutive to the first falling edge is greater than or equal to a first threshold time, which indicates that the data stream starts to correspond to a new data stream after the rising edge, and a time interval between a second falling edge of the specific clock signal and a rising edge consecutive to the second falling edge is greater than or equal to a second threshold time, which indicates that the second falling edge corresponds to an end of the new data stream.

In one embodiment of the present application, the threshold time may be greater than 1/2 clock cycles of the particular clock signal.

According to an aspect of the present application, there is provided a test method of a memory chip to be tested having a data input/output port and a chip enable port of a corresponding data channel, the test method may include: generating a specific clock signal, wherein the specific clock signal comprises first signal information for controlling the chip enable port; and sending the specific clock signal to the memory chip through a probe corresponding to the write enable port.

In one embodiment of the present application, the first signal information may include: the time interval between adjacent rising and falling edges of the particular clock signal is greater than or equal to a respective threshold time.

In one embodiment of the present application, the controlling the chip enable port based on the specific clock signal during the test may include: and controlling the level of the chip enable port to change in response to the time interval between adjacent rising edges and falling edges of the specific clock signal being greater than or equal to the corresponding threshold time.

In one embodiment of the present application, a time interval between a first falling edge of the specific clock signal and a rising edge consecutive to the first falling edge is greater than or equal to a first threshold time, which indicates that the data stream starts to correspond to a new data stream after the rising edge, and a time interval between a second falling edge of the specific clock signal and a rising edge consecutive to the second falling edge is greater than or equal to a second threshold time, which indicates that the second falling edge corresponds to an end of the new data stream.

In one embodiment of the present application, the threshold time may be greater than 1/2 clock cycles of the particular clock signal.

According to an aspect of the present application, there is provided a memory chip having a data input/output port corresponding to a data channel and a chip enable port, the data input/output port being configured to receive a mode encoding signal from a tester, the mode encoding signal including first encoding information for controlling the chip enable port; the memory chip may further include: a memory array, and peripheral circuitry coupled to the chip enable port and configured to control the chip enable port during testing based on the first encoded information.

In one embodiment of the present application, the first encoding information of the mode encoding signal may be a four-bit binary encoding, and the level of the chip enable port is controlled by different four-bit binary encodings.

According to an aspect of the present application, there is provided a memory chip having a data input/output port corresponding to a data channel and a chip enable port, the data input/output port being configured to receive a specific clock signal from a tester, the specific clock signal including first signal information for controlling the chip enable port; the memory chip may further include: a memory array, and peripheral circuitry coupled to the chip enable port, configured to control the chip enable port based on the particular clock signal during testing.

In one embodiment of the present application, the first signal information may include: the time interval between adjacent rising and falling edges of the particular clock signal is greater than or equal to a respective threshold time.

In one embodiment of the present application, the threshold time may be greater than 1/2 clock cycles of the particular clock signal.

According to an aspect of the present application, there is provided a memory chip testing apparatus, which may include: a probe for a first probe to a data input/output port of the memory chip under test; and a tester, comprising: an encoding generator configured to generate a mode encoding signal, wherein the mode encoding signal contains first encoding information for controlling a chip enable port of the memory chip; and a signal output interface configured to transmit the mode encoding signal to the memory chip through the probe.

In one embodiment of the present application, the first encoded information of the mode encoding signal is a four-bit binary code, and the level of the chip enable port is controlled by different four-bit binary codes.

According to an aspect of the present application, there is provided a memory chip testing apparatus, which may include: a probe for delivering a specific clock signal to a data input/output port of the memory chip under test; and a tester, comprising: a clock signal generator configured to generate the specific clock signal containing first signal information for controlling the chip enable port; and a signal output interface configured to transmit the specific clock signal to the memory chip through the probe.

In one embodiment of the present application, the first signal information may include: the time interval between adjacent rising and falling edges of the particular clock signal is greater than or equal to a respective threshold time.

In one embodiment of the present application, the threshold time may be greater than 1/2 clock cycles of the particular clock signal.

In one embodiment of the present application, the memory chip includes a three-dimensional NAND flash memory chip.

According to the testing device and the testing method of the memory chip, the chip enabling port is further controlled through the mode coding signal or the specific clock signal, and the number of the probes used by the chip enabling port during the testing of the memory chip is reduced. Meanwhile, the signal crosstalk among the probes can be reduced to a certain extent by using fewer probes for chip testing, and the testing quality is improved.

Drawings

Other features, objects, and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings. Wherein:

FIGS. 1A-1C are schematic diagrams of a prior art ULPC test protocol;

FIG. 2 is a schematic flow chart illustrating a chip testing method according to an embodiment of the present disclosure;

FIG. 3A is a diagram of a mode encoded signal in a prior art chip test scheme;

FIG. 3B is a schematic diagram of a mode encoded signal in a chip test scheme according to an embodiment of the present application;

FIG. 4 is a schematic flow chart illustrating a chip testing method according to another embodiment of the present application;

FIG. 5 is a diagram illustrating certain clock signals according to another embodiment of the present application; and

FIG. 6 is a diagram illustrating a memory chip testing apparatus according to an embodiment of the present application.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.

In the drawings, the size, dimension, and shape of elements have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. As used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art. In addition, in the present application, the order in which the processes of the respective steps are described does not necessarily indicate an order in which the processes occur in actual operation, unless explicitly defined otherwise or can be inferred from the context.

It will be further understood that terms such as "comprising," "including," "having," "including," and/or "containing," when used in this specification, are open-ended and not closed-ended, and specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of" appears after a list of listed features, it modifies that entire list of features rather than just individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.

Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In addition, the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

FIGS. 1A-1C are schematic diagrams of a prior art ULPC test protocol. Fig. 1A is a plan view of a wafer 100, the wafer 100 having a plurality of memory test chips 110 (e.g., three-dimensional NAND flash memory), wherein each memory chip 110 may include one or more arrayed dies (die). Fig. 1B is an enlarged schematic view of the memory test chip 110, the memory chip 110 may include a plurality of pads (Pad)111, and the tester 130 in fig. 1C may contact the pads 111 through the probes 120 to supply power to the memory test chip 110 and perform data transmission. FIG. 1 illustrates the ULPC test protocol. The interface between memory test chip 110 and tester 130 is made up of three parts, a data channel, a power channel, and a PMU channel. Wherein the data lanes include a chip enable port (CE), a write enable port (WE), a data input/output port (DQ); the power channel comprises a power port (VCC), a ground port (VSS) and a chip selection port (MDS); the PMU channel contains a voltage measurement port (VMON). In the process of testing chips by the ULPC test scheme, each memory test chip 110 needs 7 probes 120, for example, to complete the chip test. As will be appreciated by those skilled in the art, the number of memory test chips per wafer, the number of pads used for testing the memory test chips, and the number of probes included in the tester are illustrated in FIGS. 1A-1C.

Fig. 2 is a schematic flow chart illustrating a method for testing a memory chip according to an embodiment of the present disclosure. As shown in fig. 2, the present application provides a chip testing method 1000, which may include:

step S210: receiving a mode encoding signal from the tester from the data input/output port, the mode encoding signal including first encoding information for controlling the chip enable port; and

step S220: and controlling the chip enable port based on the first coding information in the test process.

According to the testing method of the memory chip, the chip enabling port of the memory testing chip is controlled through the first coded information, so that the chip enabling port is located at a high level or a low level, and the use of probes of a tester is reduced.

How the memory chip is tested using the exemplary first encoding information in the above chip testing method will be described in detail below with reference to fig. 3.

FIG. 3A is a diagram of a pattern encoded signal in a known memory chip test scheme. As shown in fig. 3A, the instruction definition in the prior art is performed using 3-bit encoding. For example, 010 is a command, 011 is an address command, 100 is an external data input command, 101 is an external data output command, 110 is an internal data input command, and 111 is an internal data output command. Each instruction has an independent code, and when the memory chip receives the code corresponding to the instruction, the corresponding operation is executed.

FIG. 3B is a diagram illustrating a mode encoding signal of a memory chip test scheme according to an embodiment of the present disclosure. Unlike the prior art shown in fig. 3A, in the embodiment shown in fig. 3B, the mode encoding signal includes first encoding information for controlling the chip enable port CE, wherein the first encoding information is defined by a four-bit binary encoding, i.e. a 4-bit encoding. In step S210, the data input/output port receives a mode encoding signal, which may be a four-bit binary encoding, from the tester. Different codes may represent different instructions, for example, 0010 is a command instruction, 0011 is an address instruction, 0100 is an external data input instruction, 0101 is an external data output instruction, 0110 is an internal data input instruction, 0111 is an internal data output instruction, 1111 is set to a high level for the chip enable port CE, and 0000 is set to a low level for the chip enable port CE. The level of the chip enable port CE is controlled by a different four bit binary encoding.

During the memory chip test, the tester may generate a pattern code signal containing first code information (such as the code information illustrated in fig. 3B) for controlling the chip enable port CE, and then may transmit the pattern code signal to the memory chip through a probe corresponding to the data input/output port (e.g., a probe corresponding to the DQ port). The first encoding information of the mode encoding signal is four-bit binary encoding. The memory receives the coding information of the mode coding signal, and the coding information can be decoded by the decoder to execute corresponding operation. In one embodiment of the present application, for example, when the first encoded information of the mode encoded signal generated by the tester is 1111, the memory may set the chip enable port CE to high level corresponding to 1111 through the translation of the encoded information by receiving the first encoded information of 1111. When the chip enable port CE is set to a high level, the chip stops the read-write operation. When the first encoding information of the mode encoding signal generated by the tester is 0000, the memory can be set to a low level corresponding to the chip enable port CE by translating the encoding information, for example, 0000, by receiving the first encoding information of 0000. When the chip enable port CE is set to a low level, the chip starts a read/write operation. Specifically, the first encoded information may be compiled with encoded information representing the actual transferred data and transferred to the memory chip through the DQ port. However, it can be understood by those skilled in the art that the operation instruction corresponding to the encoded information is an exemplary illustration, and the application is not limited thereto.

In the process of reading and writing the memory chip, the chip enable port CE always keeps a low level state, and at the moment, the chip can perform read-write operation, so that the level applied to the chip enable port CE can be controlled through the mode encoding signal. The tester transmits an instruction to a tested memory chip through a data input/output port, when the transmission instruction is 0000, a chip enable port CE is set to be at a low level, and at the moment, the memory chip can carry out reading and writing and other operations; when the transfer command is 1111, the chip enable port CE is set to a high level, and the memory chip terminates the read/write operations. However, those skilled in the art can understand that 4-bit encoding is taken as an example in the embodiment of the present application for illustration, and the instructions represented by different encodings can be predefined according to the requirement, and the form of encoding is not limited thereto.

According to an embodiment of the present application, the level of the chip enable port CE is not changed during operations such as reading and writing, so that the level of the chip enable port CE can be controlled by the mode encoding signal, the control of the tester on the test chip enable port CE by a probe is reduced, and the use of the probe of the chip enable port CE can be reduced. By reducing the number of probes occupied by a single test chip, the parallel test capability of the chip is improved to a certain extent, the test efficiency is improved, and the production cost is reduced. Meanwhile, the signal crosstalk among the probes can be reduced to a certain extent by using fewer probes for chip testing, and the testing quality is improved.

FIG. 4 is a flow chart illustrating a method for testing a memory chip according to another embodiment of the present disclosure. As shown in fig. 4, the present application provides a method 2000 for testing a chip, which may include:

step S230: receiving a specific clock signal from the tester from the data input/output port, the specific clock signal including first signal information for controlling the chip enable port; and

step S240: the chip enable port is controlled during testing based on a particular clock signal.

According to the testing method of the memory chip, the chip enabling port of the memory testing chip is controlled through the first signal information, so that the chip enabling port is located at a high level or a low level, and the use of probes of a tester is reduced.

How the memory chip is tested using the first signal information in the above chip test method will be described in detail with reference to fig. 5.

Fig. 5 is a schematic diagram of a specific clock signal according to another embodiment of the present application, where as shown in fig. 5, a low level is provided between a first falling edge of the specific clock signal and a first rising edge of the specific clock signal for a certain time period, and if a duration of the low level of the specific clock signal is greater than or equal to a corresponding threshold time, the chip enable port CE is converted from a high level to a low level, and a data read/write operation is started. After the data read-write operation is finished, a low level with a certain time length is arranged between the last falling edge of the specific clock signal and the last rising edge of the specific clock signal, if the duration time of the low level of the specific clock signal is larger than or equal to the corresponding threshold time, the chip enable port CE is converted from the low level to the high level, and the data read-write operation is finished.

It should be noted that the two threshold times in fig. 5 may not be the same, and the threshold time of the specific clock signal is greater than 1/2 clock cycles of the specific clock signal, where the clock cycle is the inverse of the clock frequency. However, it will be understood by those skilled in the art that the control of the chip enable port CE by a specific clock signal is exemplified in the embodiments of the present application, but the form of the specific clock signal is not limited thereto.

During the testing of the memory chip, the tester may generate a specific clock signal containing first signal information for controlling the chip enable port CE (such as the specific clock signal illustrated in fig. 5), and then may transmit the specific clock signal to the memory chip through the probe corresponding to the write enable port. The memory receives the specific clock signal and judges whether the specific clock signal contains the instruction information. In one embodiment of the present application, for example, the first signal information of the specific clock signal is that a time interval between adjacent rising edges and falling edges of the specific clock signal is greater than or equal to a threshold time, and a level applied to the chip enable port is changed. Where the threshold time is greater than 1/2 the period of the particular clock signal. As shown in fig. 5, the time interval between a first falling edge of a specific clock signal and a rising edge consecutive to the first falling edge is greater than or equal to the first threshold time, which indicates that a new data stream starts after the rising edge, and the memory can perform corresponding operations such as reading and writing. And until the time interval between the second falling edge of the specific clock signal and the rising edge successive to the second falling edge is greater than or equal to a second threshold time, which indicates that the second falling edge corresponds to the end of the new data stream, the memory can execute corresponding operations of reading and writing cancellation, and the like. The time interval between the first threshold time and the second threshold time may be the same or different.

According to another embodiment of the present application, the level state of the chip enable port CE is not changed during the read/write operation, so that the level of the chip enable port CE can be controlled by a specific clock signal, the control of the tester on the test chip enable port CE by a probe is reduced, and the use of the probe of the chip enable port CE can be reduced. By reducing the number of probes occupied by a single test chip, the parallel test capability of the chip is improved to a certain extent, the test efficiency is improved, and the production cost is reduced. Meanwhile, the signal crosstalk among the probes can be reduced to a certain extent by using fewer probes for chip testing, and the testing quality is improved.

Another aspect of the present application also provides a chip testing apparatus 3000. FIG. 6 is a diagram illustrating a memory chip testing apparatus according to an embodiment of the present application. As shown in fig. 6, the test apparatus 3000 may include a tester 130 and a plurality of probes 120 for testing the memory chip 110. The tester 130 may include an encoding generator, a clock signal generator, and a signal transmission interface. The memory chip 110 may include a plurality of memory chip interfaces 111, peripheral circuitry 112, and a memory array 113, wherein the peripheral circuitry 112 may include decoders and arbiters (not shown). A plurality of probes 120 including probes corresponding to data input/output ports of the memory chip under test. The tester 130 is configured to generate a pattern code signal containing first code information for controlling the chip enable port CE of the memory chip 110, and transmit the pattern code signal to the memory chip 110 through the probe. In the exemplary embodiment of the present application, the tester 130 may generate a mode encoding signal through an internal encoding generator, transmit the mode encoding signal to the peripheral circuit 112 through the data input/output port DQ, and the peripheral circuit 112 may decode the mode encoding signal by using an internal decoder to obtain information corresponding to the mode encoding signal, so as to control the chip enable port CE.

In the exemplary embodiment of the present application, the first encoding information of the mode encoding signal is a four-bit binary encoding, and the level of the chip enable port CE is controlled by different four-bit binary encodings, i.e. the encoding of 4 bits is defined by an instruction. The data input/output port DQ receives the pattern-encoded signal from the tester 130, and the transmission-specific signal to the memory chip 110 may be, for example, a four-bit binary code. Optionally, a specific signal sent by the tester may be decoded by the decoder to generate an operation instruction, where different codes may represent different instructions, for example, 0010 is a command instruction, 0011 is an address instruction, 0100 is an external data input instruction, 0101 is an external data output instruction, 0110 is an internal data input instruction, 0111 is an internal data output instruction, 1111 is set to a high level for the chip enable port CE, and 0000 is set to a low level for the chip enable port CE.

In the process of reading and writing the memory chip, the chip enable port CE always keeps a low level state, and at the moment, the chip can perform read-write operation, so that the level applied to the chip enable port CE can be controlled through the mode encoding signal. The tester may generate a pattern-coded signal containing first encoded information (e.g., encoded information illustrated in fig. 3B) for controlling the chip enable port CE, and then may transmit the pattern-coded signal to the memory chip through a probe corresponding to the data input/output port (e.g., a probe corresponding to the DQ port). The tester transmits an instruction to a tested memory chip through a data input/output port, when the transmission instruction is 0000, a chip enable port CE is set to be at a low level, and at the moment, the tested memory chip can carry out reading and writing operations and the like; when the transfer command is 1111, the chip enable port CE is set to a high level, and the memory chip terminates the read/write operations. However, it can be understood by those skilled in the art that the 4-bit encoding is used as an example in the embodiments of the present application, and the instructions represented by different encodings can be defined as required, and the form of encoding is not limited thereto.

In another embodiment of the present application, the test apparatus 3000 may include a tester 130 and a plurality of probes 120 for testing the memory chip 110. The tester 130 may include an encoding generator, a clock signal generator, and a signal transmission interface. The memory chip 110 may include a plurality of memory chip interfaces 111, peripheral circuitry 112, and a memory array 113, wherein the peripheral circuitry 112 may include decoders and arbiters (not shown). A plurality of probes 120 including probes corresponding to data input/output ports of the memory chip under test. The tester 130 is configured to generate a specific clock signal containing first signal information for controlling the chip enable port CE of the memory chip 110, and transmit the specific clock signal to the memory chip 110 through the probe. In the exemplary embodiment of the present application, the tester 130 may generate a specific clock signal through its internal clock signal generator, transmit the specific clock signal to the peripheral circuit 112 through the data input/output port DQ, and the peripheral circuit 112 may use its internal discriminator to discriminate the specific clock signal, so as to obtain information corresponding to the specific clock signal, so as to control the chip enable port CE.

The first signal information includes that a time interval between adjacent rising and falling edges of the specific clock signal is greater than or equal to a corresponding threshold time, the level applied to the chip enable port CE is changed, and the threshold time may be greater than 1/2 a period of the specific clock signal. Optionally, the specific clock signal sent by the tester may be determined by the determiner to determine whether the condition of the control chip enable port CE is satisfied, and if so, an operation instruction is generated. And if the duration time of the low level of the specific clock signal is longer than the threshold time, the chip enable port CE is converted from the high level to the low level, and the read-write operation of the data is started. After the data read-write operation is finished, a low level with a certain time length is arranged between the last falling edge of the specific clock signal and the last rising edge of the specific clock signal, if the duration time of the low level of the specific clock signal is longer than the threshold time, the chip enable port CE is converted from the low level to the high level, and the data read-write operation is finished. Wherein the threshold time of the particular clock signal is greater than 1/2 a particular clock signal period, wherein the particular clock signal period is the inverse of the clock frequency. As shown in fig. 5, the time interval between a first falling edge of a specific clock signal and a rising edge consecutive to the first falling edge is greater than or equal to the first threshold time, which indicates that a new data stream starts after the rising edge, and the memory can perform corresponding operations such as reading and writing. And until the time interval between the second falling edge of the specific clock signal and the rising edge successive to the second falling edge is greater than or equal to a second threshold time, which indicates that the second falling edge corresponds to the end of the new data stream, the memory can execute corresponding operations of reading and writing cancellation, and the like. The time interval between the first threshold time and the second threshold time may be the same or different. However, it will be understood by those skilled in the art that the control of the chip enable port CE by a specific clock signal is exemplified in the embodiments of the present application, but the form of the specific clock signal is not limited thereto.

According to another embodiment of the present application, the level state of the chip enable port CE is not changed during the read/write operation, so that the level of the chip enable port CE can be controlled by a specific clock signal, the control of the tester on the test chip enable port CE by a probe is reduced, and the use of the probe of the chip enable port CE can be reduced. By reducing the number of probes occupied by a single test chip, the parallel test capability of the chip is improved to a certain extent, the test efficiency is improved, and the production cost is reduced. Meanwhile, the signal crosstalk among the probes can be reduced to a certain extent by using fewer probes for chip testing, and the testing quality is improved.

Although the test chip 110 of the above example is illustrated with a three-dimensional NAND flash memory chip as an example, it will be understood that the test method and test apparatus of the above example can be equally applied when other memory chips have the same or similar test conditions.

The objects, technical solutions and advantageous effects of the present invention are further described in detail with reference to the above-described embodiments. It should be understood that the above description is only a specific embodiment of the present invention, and is not intended to limit the present invention. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims (25)

1. A method of testing a memory chip, wherein the memory chip under test has a data input/output port and a chip enable port corresponding to a data channel, the method comprising:

receiving a mode encoding signal from a tester from the data input/output port, wherein the mode encoding signal comprises first encoding information for controlling the chip enable port; and

and controlling the chip enabling port based on the first coding information in the testing process.

2. The method of claim 1, wherein the first encoded information of the mode encoded signal is a four-bit binary encoding, and wherein the level of the chip enable port is controlled by a different four-bit binary encoding.

3. A method of testing a memory chip having a data input/output port and a chip enable port corresponding to a data channel, the method comprising:

generating a mode encoding signal, wherein the mode encoding signal comprises first encoding information used for controlling the chip enabling port; and

and sending the mode coding signal to the memory chip through a probe corresponding to the data input/output port.

4. The method of claim 3, wherein the first encoded information of the mode encoded signal is a four-bit binary encoding, and wherein the level of the chip enable port is controlled by a different four-bit binary encoding.

5. A method of testing a memory chip having a data input/output port and a chip enable port corresponding to a data channel, the method comprising:

receiving a specific clock signal from a tester from the data input/output port, wherein the specific clock signal contains first signal information for controlling the chip enable port; and

and controlling the chip enabling port based on the specific clock signal in the testing process.

6. The method of claim 5, wherein the first signal information comprises:

the time interval between adjacent rising and falling edges of the particular clock signal is greater than or equal to a respective threshold time.

7. The method of claim 6, wherein controlling the chip enable port based on the specific clock signal during testing comprises:

and controlling the level of the chip enable port to change in response to the time interval between adjacent rising edges and falling edges of the specific clock signal being greater than or equal to the corresponding threshold time.

8. The method of claim 6, wherein a time interval between a first falling edge of the specific clock signal and a rising edge consecutive to the first falling edge is greater than or equal to a first threshold time, indicating that the rising edge is followed by a beginning of the corresponding new data stream, until a time interval between a second falling edge of the specific clock signal and a rising edge consecutive to the second falling edge is greater than or equal to a second threshold time, indicating that the second falling edge corresponds to an end of the corresponding new data stream.

9. The method of claim 6, wherein the threshold time is greater than 1/2 clock cycles of the particular clock signal.

10. A method of testing a memory chip having a data input/output port and a chip enable port corresponding to a data channel, the method comprising:

generating a specific clock signal, wherein the specific clock signal comprises first signal information for controlling the chip enable port; and

and sending the specific clock signal to the memory chip through a probe corresponding to the data input/output port.

11. The method of claim 10, wherein the first signal information comprises:

the time interval between adjacent rising and falling edges of the particular clock signal is greater than or equal to a respective threshold time.

12. The method of claim 11, wherein controlling the chip enable port based on the particular clock signal during testing comprises:

and controlling the level of the chip enable port to change in response to the time interval between adjacent rising edges and falling edges of the specific clock signal being greater than or equal to the corresponding threshold time.

13. The method of claim 11, wherein a time interval between a first falling edge of the specific clock signal and a rising edge consecutive to the first falling edge is greater than or equal to a first threshold time indicating that the rising edge is followed by a beginning of the corresponding new data stream, until a time interval between a second falling edge of the specific clock signal and a rising edge consecutive to the second falling edge is greater than or equal to a second threshold time indicating that the second falling edge corresponds to an end of the corresponding new data stream.

14. The method of claim 11, wherein the threshold time is greater than 1/2 clock cycles of the particular clock signal.

15. A memory chip having a data input/output port and a chip enable port corresponding to a data channel,

the data input/output port is configured to receive a mode encoding signal from a tester, the mode encoding signal including first encoding information for controlling the chip enable port;

the memory chip further includes:

a memory array, and

peripheral circuitry coupled to the chip enable port and configured to control the chip enable port during testing based on the first encoded information.

16. The memory chip of claim 15, wherein the mode encoded signal first encoded information is a four bit binary encoding, and wherein the level of the chip enable port is controlled by a different four bit binary encoding.

17. A memory chip having a data input/output port and a chip enable port corresponding to a data channel,

the data input/output port is configured to receive a specific clock signal from a tester, the specific clock signal containing first signal information for controlling the chip enable port;

the memory chip further includes:

a memory array, and

peripheral circuitry coupled to the chip enable port and configured to

And controlling the chip enabling port based on the specific clock signal in the testing process.

18. The memory chip of claim 17, wherein the first signal information comprises:

the time interval between adjacent rising and falling edges of the particular clock signal is greater than or equal to a corresponding threshold time, and the level applied to the chip enable port changes.

19. The memory chip of claim 18, in which the threshold time is greater than 1/2 clock cycles of the particular clock signal.

20. A memory chip test apparatus, comprising:

a probe for delivering a mode encoded signal to a data input/output port of the memory chip under test; and

a tester, comprising:

an encoding generator configured to generate the mode encoding signal, wherein the mode encoding signal contains first encoding information for controlling a chip enable port of the memory chip; and

a signal output interface configured to transmit the pattern encoded signal to the memory chip through the probe.

21. The memory chip test device of claim 20, wherein the mode-encoded signal first encoded information is a four-bit binary encoding, and the level of the chip enable port is controlled by a different four-bit binary encoding.

22. A memory chip test apparatus, comprising:

a probe for delivering a specific clock signal to a data input/output port of the memory chip under test; and

a tester, comprising:

a clock signal generator configured to generate the specific clock signal containing first signal information for controlling the chip enable port; and

a signal output interface configured to transmit the specific clock signal to the memory chip through the probe.

23. The memory chip test apparatus of claim 22, wherein the first signal information comprises:

the time interval between adjacent rising and falling edges of the particular clock signal is greater than or equal to a respective threshold time.

24. The memory chip test apparatus of claim 23, wherein the threshold time is greater than 1/2 clock cycles of the particular clock signal.

25. The memory chip of any one of claims 15 to 19, wherein the memory chip comprises a three-dimensional NAND flash memory chip.

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