CN114360622B - Reset circuit testing system and method for logic built-in self-test - Google Patents
Reset circuit testing system and method for logic built-in self-test Download PDFInfo
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- CN114360622B CN114360622B CN202210254392.9A CN202210254392A CN114360622B CN 114360622 B CN114360622 B CN 114360622B CN 202210254392 A CN202210254392 A CN 202210254392A CN 114360622 B CN114360622 B CN 114360622B
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Abstract
The reset circuit test system comprises a test vector generator, a logic built-in self-test controller and a test response analyzer, wherein the test vector generator generates a reset test vector and a pseudo-random test vector, receives an instruction of the logic built-in self-test controller and outputs a reset signal, a clock signal, a scan enable signal and a scan vector output signal to a circuit to be tested; the logic built-in self-test controller is used for respectively controlling the output of the signals of the test vector generator and controlling the test response analyzer to test the circuit to be tested; and the test response analyzer receives the instruction of the logic built-in self-test controller and tests the circuit to be tested. The invention also provides a reset circuit testing method for the logic built-in self-test, which solves the problem that reset signals cannot be covered highly in the traditional logic built-in self-test by using less logic, and improves fault coverage rate.
Description
Technical Field
The present invention relates to the field of integrated circuit board level testing technology, and in particular, to a system and method for testing a reset circuit of a logic built-in self-test.
Background
With the ever shrinking process size and increasing chip scale of integrated circuits, higher requirements are placed on chip testing difficulty, testing cost and testing method. Achieving higher test coverage with less test cost and less test time is a major issue in chip testing.
Conventional chip testing performs built-in self-test (MBIST) on memory cells of an Automatic Test Equipment (ATE) for on-chip memory, boundary SCAN test (BSD) for a system pin handling module (IO PAD), SCAN chain test (SCAN) for digital logic, quiescent current based test (IDDQ), low voltage test at reduced power supply voltage, test for analog circuits, and so forth. These are used as the test before the chip leaves the factory, in order to find the defect in the chip manufacturing process, improve the reliability of the test, thus ensure that the chip will realize the correct operation according to the design after putting into the system.
Since transistors in a chip are slowly aged and damaged during use, logic built-in self test (LBIST) is becoming a trend for applications in scenes where reliability requirements are high (e.g., automotive electronics, medical electronics, etc.). The self-test is carried out before the chip is started or during on-line operation, so that problems are found in advance, and faults in the operation of the system are avoided.
Conventional logic built-in self test (LBIST) generates pseudo-random test vectors by a built-in linear shift register (LFSR) to scan chain test a circuit under test (Circuit Under Test, CUT) of a completed scan design. And testing the reset signals of the registers in the circuit to be tested, and detecting whether the reset tree and the reset signals of the registers have faults or not. The test is also performed by a pseudo-random test vector, but because of the uncertainty of the test vector, there is a loss of this kind of coverage of registers, reducing the fault coverage.
Disclosure of Invention
In order to solve the defects existing in the prior art, the invention aims to provide a system and a method for testing a reset circuit of a logic built-in self test, which are used for testing a reset signal of a register in a circuit to be tested before a linear shift register (LFSR) is used as a test vector to test a scan chain of the circuit to be tested (Circuit under test, CUT) of a finished scan design, and detecting whether the reset signal of the reset tree and the register has faults or not.
In order to achieve the above object, the present invention provides a reset circuit test system for logic built-in self-test, comprising a test vector generator, a logic built-in self-test controller, and a test response analyzer, wherein,
the test vector generator generates a reset test vector and a pseudo-random test vector, receives an instruction of the logic built-in self-test controller, and outputs a reset signal, a clock signal, a scan enable signal and a scan vector output signal to a circuit to be tested;
the logic built-in self-test controller is used for respectively controlling the output of the signals of the test vector generator and controlling the test response analyzer to test the circuit to be tested;
and the test response analyzer receives the instruction of the logic built-in self-test controller and tests the circuit to be tested.
Still further, the test vector generator further comprises a reset test vector generator, a pseudo-random test vector generator, and a selector, wherein,
the reset test vector generator is used for generating a reset test vector;
the pseudo-random test vector generator is used for generating a pseudo-random test vector;
the selector receives the control from the logic built-in self-test controller, selects the input reset test vector and pseudo-random test vector, and outputs a reset signal, a clock signal, a scanning enabling signal and a scanning vector output signal to the circuit to be tested.
In order to achieve the above object, the present invention further provides a method for testing a reset circuit of a logic built-in self-test, comprising the steps of:
setting all reset test vectors to 1, setting all scan vector outputs to 1, and carrying out reset test vector test;
setting all reset test vectors to 0, setting all scan vector outputs to 0, and carrying out reset test vector test;
and setting the reset test enabling to 0, selecting a pseudo-random test vector to output, and performing pseudo-random test vector test.
Further, the step of setting all reset test vectors to 1, setting all scan vector outputs to 1, performing reset test vector test, further comprises,
at scan shift: and setting the scanning input as 1, setting the scanning enable output as 1, setting the reset signal in an invalid state, and beating the clock signal as the number of beats of the scanning chain length response to enable all 1 signals to be completely shifted into all scanning chain registers of the circuit to be tested.
Further, the step of setting all reset test vectors to 1, setting all scan vector outputs to 1, performing reset test vector test,
in the scanning capturing stage, the scanning enabling is pulled down to be in an invalid state, and a reset signal is reset or set; changing the value latched in the register reset to 0; if the register is defective, its value cannot be flipped.
Further, the step of setting all reset test vectors to 0, setting all scan vector outputs to 0, performing reset test vector test, further comprises,
in the scan shift phase: and setting the scanning input to 0, setting the scanning enabling to 1, enabling the reset signal to be in an invalid state, and beating the clock signal to be the number of beats of the scanning chain length response so as to enable the 0 signal to be completely shifted into all scanning chain registers of the circuit to be tested.
Further, the step of setting all reset test vectors to 0, setting all scan vector outputs to 0, performing reset test vector test, further comprises,
in the scan capturing stage, scan enabling is pulled down and is in an invalid state, a reset signal is reset or is set, and a value latched in a register set to 1 is changed to 1; if the register is defective, its value cannot be flipped.
Further, the step of setting the reset test enable to 0, selecting the pseudo-random test vector to output, and performing the pseudo-random test vector test, further comprises,
the reset signals are all in an invalid state, and the clock signals generate a clock period in the scanning capturing stage, so that the combinational logic in the circuit to be tested is tested.
In order to achieve the above object, the present invention further provides a chip, which includes the reset circuit testing system for logic built-in self-test described above.
To achieve the above object, the present invention further provides an electronic device, including a memory and a processor, where the memory stores a computer program running on the processor, and the processor executes the steps of the reset circuit testing method for logic built-in self-test as described above when running the computer program.
Compared with the prior art, the reset circuit testing system and method for the logic built-in self test have the following beneficial effects:
compared with the traditional logic built-in self test (LBIST) reset test, the test vector is more, and the test time is saved; under the condition that the original logic built-in self test is not affected, the problem that reset signals cannot be covered in the traditional logic built-in self test is solved by using less logic, and the fault coverage rate is improved;
resources on Automatic Test Equipment (ATE) can be saved to a great extent, and the high-speed test has higher quality than the traditional ATE test, and the on-line testing device has the advantage of being easier to integrate, and meanwhile, the on-line testing device can guarantee the reliability of the chip after being started.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, and do not limit the invention. In the drawings:
FIG. 1 is a schematic diagram of a system for testing a reset circuit of a logic built-in self-test according to the present invention.
FIG. 2 is a schematic diagram of a test vector generator according to the present invention;
FIG. 3 is a schematic diagram of a reset circuit test logic for a logic built-in self-test according to the present invention;
FIG. 4 is a flow chart of a method for testing a reset circuit of a logic built-in self-test according to the present invention.
Detailed Description
The preferred embodiments of the present invention will be described below with reference to the accompanying drawings, it being understood that the preferred embodiments described herein are for illustration and explanation of the present invention only, and are not intended to limit the present invention.
In the embodiment of the invention, a complex position 0 register, a complex position 1 register and a non-reset register exist in a circuit to be tested.
Example 1
Fig. 1 is a schematic diagram of a reset circuit test system of a logic built-in self-test according to the present invention, as shown in fig. 1, the reset circuit test system of the logic built-in self-test of the present invention includes a test vector generator 10, a logic built-in self-test controller 20, and a test response analyzer 30, wherein,
the test vector generator 10 generates a reset test vector and a pseudo-random test vector, receives an instruction from the logic built-in self-test controller 20, and outputs a reset signal, a clock signal, a scan enable signal, and a scan vector output signal to the circuit under test.
And the logic built-in self-test controller 20 is respectively connected with the test vector generator 10 and the test response analyzer 30, and controls the test vector generator 10 to generate a reset test vector and a pseudo-random test vector, and outputs signals and controls the test response analyzer 30 to test the circuit to be tested.
The test response analyzer 30 receives the instruction of the logic built-in self-test controller 20 and tests the circuit to be tested.
Example 2
Fig. 2 is a schematic diagram of a test vector generator according to the present invention, as shown in fig. 2, including a reset test vector generator 11, a pseudo-random test vector generator 12, and a selector 13, wherein,
a reset test vector generator 11 which sends the generated reset test vector to one input of the selector 13.
A pseudo-random test vector generator 12 which sends the generated pseudo-random test vector to the other input of the selector 13.
And a selector 13 for selecting the inputted reset test vector and pseudo-random test vector and outputting the reset signal, clock signal, scan enable signal and scan vector output signal to the circuit to be tested under the control of the reset test enable signal from the logic built-in self-test controller 20.
Example 3
Fig. 4 is a flowchart of a method for testing a reset circuit of a logic built-in self-test according to the present invention, and the method for testing a reset circuit of a logic built-in self-test according to the present invention will be described in detail with reference to fig. 4.
First, in step 401, a reset test enable is set to 1, and a reset test vector generator is selected.
In the embodiment of the present invention, the logic built-in self-test controller 20 sets the reset test enable of the selector 13 in the test vector generator 10 to 1, selects the output of the reset test vector generator, and performs the reset test vector test.
In step 402, the reset test vectors are all set to 1, the scan vector outputs are all set to 1, and the reset test vector test is performed.
In the embodiment of the present invention, as shown in fig. 3, in the scan shift (scan shift) stage: the scan input (SI, scan vector output signal generated by the reset vector generator) of the circuit to be tested is set to 1, the Scan Enable (SE) output is set to 1, the reset signal (RST_N) is in an invalid state, the clock signal is beaten to be the beat number of the scan chain length response, and all 1 signals (the values on all the scan registers of the circuit to be tested are 1) are shifted to all the scan chain registers of the circuit to be tested.
In the embodiment of the present invention, as shown in fig. 3, in the scan capture (scan capture) stage, the Scan Enable (SE) is pulled down, in an inactive state, and the reset signal (rst_n) is reset/set. When a register reset to 0 goes through the operation, the value latched in the register changes to 0, and if the register has a defect, the value cannot be flipped.
In step 403, the reset test vectors are all set to 0, and the scan vector outputs are all set to 0, so as to perform the reset test vector test.
In the embodiment of the present invention, as shown in fig. 3, in the scan shift (scan shift) stage: the Scan Input (SI) is 0, the shift signal is 0, the Scan Enable (SE) is 1, the reset signal (RST_N) is in an invalid state, the clock signal is the number of beats of the scan chain length response, and the 0 signal is shifted to all scan chain registers of the circuit to be tested.
In an embodiment of the present invention, as shown in fig. 3, during a scan capture (scan capture) phase, scan Enable (SE) is pulled low and in an inactive state. The reset signal (rst_n) is reset/set. When a register set to 1 goes through this operation, the value latched in the register changes to 1, and if the register has a defect, its value cannot be flipped.
In step 404, reset test enable is set to 0, a pseudo-random test vector is selected, and a pseudo-random test is performed.
In the embodiment of the invention, the stage continues to test other pins and combinational logic of sequential logic in the circuit to be tested through more test vectors. In the pseudo-random test vector test stage, the reset signal (RST_N) is in an inactive state, and in the scan capture (scan capture) stage, a clock signal is generated for one clock cycle to test the combinational logic in the circuit under test.
Example 4
In one embodiment of the present invention, there is further provided a chip including the reset circuit test system for logic built-in self-test as described above, wherein before a linear shift register (LFSR) is used as a test vector to perform scan chain test on a circuit under test (Circuit under test, CUT) of a completed scan design, a test is performed on a reset signal of a register in the circuit under test, and whether a fault exists in the reset tree and the reset signal of the register is detected.
Example 5
In one embodiment of the present invention, there is also provided an electronic device including a memory and a processor, the memory having stored thereon a computer program running on the processor, the processor executing the steps of the reset circuit test method of logic built-in self-test as described above when the computer program is run.
Those of ordinary skill in the art will appreciate that: the foregoing description is only a preferred embodiment of the present invention, and the present invention is not limited thereto, but it is to be understood that modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art, although the present invention has been described in detail with reference to the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (5)
1. A reset circuit test system for logic built-in self test is characterized by comprising a circuit to be tested, a test vector generator, a logic built-in self test controller and a test response analyzer, wherein,
the circuit to be tested is provided with a complex position 1 register and a complex position 0 register;
the test vector generator comprises a reset test vector generator for generating a reset test vector and a pseudo-random test vector generator for generating a pseudo-random test vector, and receives an instruction of the logic built-in self-test controller and outputs a reset signal, a clock signal, a scanning enabling signal and a scanning vector output signal to the circuit to be tested;
the logic built-in self-test controller is used for respectively controlling the output of the signals of the test vector generator and controlling the test response analyzer to test the circuit to be tested;
the test response analyzer receives the instruction of the logic built-in self-test controller and tests the circuit to be tested;
the scan input of the circuit to be tested is connected with the scan vector output signal of the reset test vector generator;
the test vector generator is reset to a predetermined value,
in the scanning shifting stage, the scanning enabling output enables the circuit to be detected to be in an effective state, the reset signal is in an invalid state, the scanning vector output enables the scanning input of the circuit to be detected to be set to be 1, the clock signal is the number of beats of the scanning chain length response, and all 1 signals are shifted to all scanning chain registers of the circuit to be detected; in the scanning capturing stage, the scanning enabling output enables the circuit to be detected to be in an invalid state, the reset signal is in a reset state, whether the values latched in all the complex position 0 registers are 0 or not is detected, and if the values latched in the complex position 0 registers are not 0, the reset 0 registers have defects; and
in the scanning shifting stage, the scanning enabling output enables the circuit to be detected to be in an effective state, the reset signal is in an ineffective state, the scanning vector output enables the scanning input of the circuit to be detected to be 0, the clock signal is the number of beats of the scanning chain length response, and all 0 signals are shifted to all scanning chain registers of the circuit to be detected; in the scan capture stage, the scan enable output makes the circuit to be tested in an invalid state and the reset signal in a reset state, detects whether the value latched in all the complex position 1 registers is 1, and if the value latched in the complex position 1 registers is not 1, the reset 1 registers have defects.
2. The reset circuit test system of claim 1 wherein said test vector generator further comprises, a selector, wherein,
the selector receives the control from the logic built-in self-test controller, selects the input reset test vector and pseudo-random test vector, and outputs a reset signal, a clock signal, a scanning enabling signal and a scanning vector output signal to the circuit to be tested.
3. A reset circuit testing method of logic built-in self-test, adopting the reset circuit testing system of logic built-in self-test as set forth in claim 1 or 2, comprising the steps of:
selecting a reset test vector generator, and testing whether a reset 0 register of a circuit to be tested has defects or not: in the scanning shifting stage, the scanning enabling output enables the circuit to be detected to be in an effective state, the reset signal is in an invalid state, the scanning vector output enables the scanning input of the circuit to be detected to be set to be 1, the clock signal is the number of beats of the scanning chain length response, and all 1 signals are shifted to all scanning chain registers of the circuit to be detected; in the scanning capturing stage, the scanning enabling output enables the circuit to be detected to be in an invalid state, the reset signal is in a reset state, whether the values latched in all the complex position 0 registers are 0 or not is detected, and if the values latched in the complex position 0 registers are not 0, the reset 0 registers have defects;
selecting a reset test vector generator, and testing whether a reset 1 register of a circuit to be tested has defects or not: in the scanning shifting stage, the scanning enabling output enables the circuit to be detected to be in an effective state, the reset signal is in an ineffective state, the scanning vector output enables the scanning input of the circuit to be detected to be 0, the clock signal is the number of beats of the scanning chain length response, and all 0 signals are shifted to all scanning chain registers of the circuit to be detected; in the scanning capturing stage, the scanning enabling output enables a circuit to be detected to be in an invalid state, a reset signal is in a reset state, whether the values latched in all the complex position 1 registers are 1 or not is detected, and if the values latched in the complex position 1 registers are not 1, the reset 1 registers have defects;
selecting a pseudo-random test vector generator to perform pseudo-random test on the circuit to be tested: and setting the reset test enabling to 0, outputting a pseudo-random test vector, enabling a reset signal to be in an invalid state, and generating a clock cycle by a clock signal during a scanning capturing stage to test the combinational logic in the circuit to be tested.
4. A chip comprising the reset circuit test system of the logic built-in self-test of claim 1 or 2.
5. An electronic device comprising a memory and a processor, the memory having stored thereon a computer program that is executed on the processor, the processor executing the steps of the reset circuit test method of logic built-in self-test of claim 3 when the computer program is executed.
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| CN116225771B (en) * | 2023-05-08 | 2023-07-25 | 上海励驰半导体有限公司 | System external monitoring reset circuit, chip, electronic equipment and related equipment |
| CN117521588B (en) * | 2024-01-08 | 2024-05-10 | 深圳中安辰鸿技术有限公司 | Control method and device for preventing non-uniform aging of integrated circuit and processing chip |
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| CN103943152B (en) * | 2014-03-31 | 2017-02-01 | 西安紫光国芯半导体有限公司 | Rapid built-in self-testing system and method of memory |
| US10866280B2 (en) * | 2019-04-01 | 2020-12-15 | Texas Instruments Incorporated | Scan chain self-testing of lockstep cores on reset |
| CN114076883B (en) * | 2021-11-10 | 2023-09-05 | 北京中电华大电子设计有限责任公司 | Burn-in circuit, chip burn-in test method and chip |
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