CN114359029B - Image processing method, image processing apparatus, image processing system, and storage medium - Google Patents
Image processing method, image processing apparatus, image processing system, and storage medium Download PDFInfo
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Abstract
The invention discloses an image processing method, an image processing device, an image processing system and a storage medium. The image processing method is applied to an image processing device, and comprises the following steps: acquiring image size information of an original image; acquiring a first processing block currently sent by a first image processing module, and blocking information and accumulation information corresponding to the first processing block; obtaining the position information of the first processing block in the original image according to the image size information, the block information and the accumulated information; acquiring first error information according to the position information; and carrying out intra-block error diffusion processing on the first processing block according to the first error information and the error diffusion template to obtain second error information. According to the scheme of the embodiment of the invention, when the high-resolution image is processed in hardware, the dynamic blocking error diffusion image processing can be supported; under the condition of ensuring the image quality, the consumption of the internal storage resources of the hardware is reduced, and the chip area occupied during the image processing is reduced.
Description
Technical Field
The present invention relates to the field of image processing technologies, and in particular, to an image processing method, an apparatus, a system, and a storage medium.
Background
With the development of information technology, the application range of images is also more and more extensive. The information is transmitted more visually and vividly by utilizing the image, the image is stored under the condition of ensuring the image quality, and the occupied memory is larger. In the related art, when an image is processed using an error diffusion dither image processing technique, the processing is generally performed on the basis of the entire image. The existing error diffusion algorithm is basically implemented by processing images according to the whole image, and after a template of the error diffusion algorithm is selected, the whole image is processed one by one according to pixels. Taking high resolution image processing as an example, 4096 × 4096 pixels, when processing error diffusion according to the whole picture, because the next row of pixels needs to inherit the error of the previous row of pixels, at least 4096 pixel data needs to be cached, taking ARGB32 as an example, the chip needs at least 4096 × 32 bit storage resource space. When the width of the processed image is large (such as 4K), a large chip cache resource area is needed to ensure smooth processing of the image. How to reduce the consumption of internal storage resources under the condition of ensuring the image quality when processing high-resolution images is an urgent problem to be solved.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
The embodiment of the invention provides an image processing method, an image processing device, an image processing system and a storage medium, which can support dynamic blocking error diffusion image processing, reduce the consumption of hardware internal storage resources under the condition of ensuring the image quality, and reduce the occupied chip area during image processing.
In a first aspect, an embodiment of the present invention provides an image processing method, which is applied to an image processing apparatus, and the image processing method includes:
acquiring image size information of an original image;
acquiring a first processing block currently sent by a first image processing module, and block information and accumulated information corresponding to the first processing block;
obtaining the position information of the first processing block in the original image according to the image size information, the blocking information and the accumulation information;
acquiring first error information according to the position information;
and carrying out intra-block error diffusion processing on the first processing block according to the first error information and an error diffusion template to obtain second error information, wherein the second error information is used for carrying out the intra-block error diffusion processing on a next-stage processing block of the first processing block.
In a second aspect, an embodiment of the present invention further provides an image processing system, including: the image processing system includes:
an image processing apparatus including a first image processing module and an error diffusion module;
the first image processing module is configured to perform blocking processing on a whole original image to obtain a first processing block and blocking information corresponding to the first processing block, and transmit the first processing block and the blocking information to an error diffusion module;
the error diffusion module is used for acquiring image size information of an original image, acquiring a first processing block currently sent by the first image processing module, and blocking information and accumulation information corresponding to the first processing block, acquiring position information of the first processing block in the original image according to the image size information, the blocking information and the accumulation information, acquiring first error information according to the position information, and performing intra-block error diffusion processing on the first processing block according to the first error information and an error diffusion template to acquire second error information, wherein the second error information is used for performing the intra-block error diffusion processing on a next-stage processing block of the first processing block;
an external storage unit is also included for storing the first horizontal direction error data in the first error information.
In a third aspect, an embodiment of the present invention further provides an image processing apparatus, including: a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the image processing method as described above in the first aspect when executing the computer program.
In a fourth aspect, the embodiment of the present invention further provides a computer storage medium storing computer-executable instructions for executing the image processing method described above.
The embodiment of the invention comprises the following steps: acquiring image size information of an original image; acquiring a first processing block currently sent by a first image processing module, and block information and accumulated information corresponding to the first processing block; obtaining the position information of the first processing block in the original image according to the image size information, the blocking information and the accumulation information; acquiring first error information according to the position information; and processing the first processing block according to the first error information and an error diffusion template to obtain second error information. According to the scheme of the embodiment of the invention, the image size information of the original image, the first processing block currently sent by the first image processing module, the block information corresponding to the first processing block and the accumulated information are obtained by using the image processing device, so as to obtain the position information of the first processing block in the original image; and acquiring first error information by using the position information, and processing the first processing block based on the first error information and an error diffusion template to obtain second error information, wherein the second error information is used for carrying out intra-block error diffusion processing on a next-stage processing block of the first processing block. That is to say, the scheme of the embodiment of the invention can support dynamic blocking error diffusion image processing when processing high-resolution images in hardware; under the condition of ensuring the image quality, the consumption of the internal storage resources of the hardware is reduced, and the chip area occupied during the image processing is reduced.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.
Fig. 1 is a schematic structural diagram of an image processing system according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an embodiment of an image processing system according to the present invention;
FIG. 3 is a flowchart illustrating an image processing method according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of image dynamic blocking processing according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of error diffusion based on the image motion block shown in FIG. 4 according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of an error diffusion template according to an embodiment of the present invention;
fig. 7 is an image processing apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
It should be noted that, although a logical order is illustrated in the flowcharts, in some cases, the steps illustrated or described may be performed in an order different from that in the flowcharts. The terms first, second and the like in the description and in the claims, and the drawings described above, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
The invention has provided a image processing method and its apparatus, system, storage medium, utilize the image processing apparatus to obtain the image size information of the original image, first processing block, corresponding to said first processing block of information and accumulation information of the corresponding partitioning of first processing block that the first image processing module sends at present, get the position information of the first processing block in the original image; and then, acquiring first error information by using the position information, and processing the first processing block based on the first error information and the error diffusion template to obtain second error information, wherein the second error information is used for carrying out intra-block error diffusion processing on a next-stage processing block of the first processing block. That is to say, the scheme of the embodiment of the invention can support dynamic blocking error diffusion image processing when processing high-resolution images in hardware; under the condition of ensuring the image quality, the consumption of the internal storage resources of the hardware is reduced, and the chip area occupied during the image processing is reduced.
The embodiments of the present invention will be further explained with reference to the drawings.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an image processing system according to an embodiment of the present invention. In the example of fig. 1, the image processing system includes an external storage unit and an image processing apparatus, wherein the image processing apparatus includes a first image processing module, an error diffusion module, and a second image processing module. The error diffusion module is arranged between the first image processing module and the second image processing module, and is in communication connection with the first image processing module, the second image processing module and the external storage unit respectively.
The first image processing module is used for carrying out blocking processing on the whole original image to obtain a first processing block and blocking information corresponding to the first processing block, and transmitting the first processing block and the blocking information to the error diffusion module.
It should be noted that, after the first image processing module performs the block processing on the original image, at least two processing blocks and block information corresponding to the processing blocks are obtained. And the first image processing module sequentially sends the processing blocks and the corresponding block information to the error processing module until the error processing module finishes the error diffusion processing of the whole original image. It is understood that the first image processing module can perform other processing, such as scaling, etc., on the original image besides the blocking processing. The present application does not specifically limit other functions implemented by the first image processing module, as long as the first image processing module can perform blocking processing on the whole original image.
The error diffusion module is used for acquiring image size information of an original image, receiving a first processing block sent by the first image processing module and blocking information corresponding to the first processing block, and obtaining position information of the first processing block in the original image according to the image size information and the blocking information; acquiring first error information according to the position information; and processing the first processing block according to the first error information and the error diffusion template to obtain second error information, wherein the second error information is used for carrying out intra-block error diffusion processing on a processing block at the next stage of the first processing block. And the error diffusion module receives the processing blocks and the corresponding block information sent by the first image processing module in sequence until the error diffusion processing of the whole original image is completed. In addition, the error diffusion module can acquire second error information updated after the error diffusion processing, and the second error information is processed according to the position information of the first processing block. And can transmit the block information corresponding to the first processing block, pixel data and the like to the second image processing module.
And the external storage space is connected with the error diffusion module and is used for storing the horizontal direction error information of the processing block.
And the second image processing module is used for receiving the block information corresponding to the first processing block, the pixel data output by the error diffusion module and the like. And the subsequent second image processing module writes the pixel data back to the memory according to the pixel position of the whole original image. This portion of the work performed by the second image processing module is outside the contemplation of the present invention. It will be appreciated that the second image processing module does not participate in the core process of dynamically blocking the processed image. The application does not specifically limit how the second image processing module is implemented to process the image.
In an alternative implementation manner, referring to fig. 2, fig. 2 is a schematic structural diagram of an image processing system according to an embodiment of the present invention. As shown in fig. 2, the image processing apparatus shown in fig. 1 is a chip in particular. The error diffusion module at least comprises an internal horizontal error data cache space module, an internal vertical error data cache space and an error diffusion image processing hardware logic module. And the error diffusion image processing hardware logic module is respectively in communication connection with the internal horizontal direction error data cache space and the internal vertical direction error data cache space. The error diffusion image processing hardware logic module can respectively carry out read-write operation on the internal horizontal direction error data cache space and the internal vertical direction error data cache space. The internal horizontal error data buffer space is connected to the external storage unit, and can buffer error information read from the external storage unit and also can buffer error information to be written to the external storage unit.
With reference to fig. 2, the dynamic blocking error diffusion image processing process performed by the error diffusion module is explained as follows:
step 1: the error diffusion module reads image size information of the whole original image, wherein the image size information comprises a second pixel height and a second pixel width of the original image.
Step 2: and the error diffusion module receives the first processing block sent by the first image processing module and the block information and the accumulated information corresponding to the first processing block.
And step 3: and the error diffusion module determines the position information of the first processing block in the whole original image according to the image size information of the whole original image and the block information corresponding to the current first processing block, wherein the position information comprises row information and column information.
And 4, step 4: the error diffusion module judges whether or not required horizontal error information needs to be read from the external storage unit according to column information of the position information of the first processing block, and judges whether or not vertical error information needs to be acquired from an internal vertical error data cache space internally according to row information of the position information of the first processing block.
And 5: the error diffusion module writes the horizontal direction error information read from the external storage unit into the internal horizontal direction error data buffer space.
Step 6: and the error diffusion image processing hardware logic module reads and utilizes the read horizontal error information and/or vertical error information and carries out error diffusion image processing according to the error diffusion template. In this step, the error diffusion module performs diffusion image processing on a single processing block, that is, a first processing block, processes the processing blocks in a pipeline manner, and transmits the processed pixel data to the next-stage module after the processing is completed. The pipeline mode refers to a hardware processing mode, which is equivalent to completing one pixel processing in one clock cycle.
And 7: and obtaining new horizontal direction error data and vertical direction error data after the error diffusion processing is finished, judging whether the horizontal direction error data needs to be written into an external storage unit or not, and judging whether the vertical direction error data needs to be written into an internal vertical direction error data cache space or not. New horizontal direction error data and vertical direction error data are used by the next processing block.
And 8: and the error diffusion module starts to process the next processing block and repeats the steps until a complete original image is processed.
When the conventional whole picture processing is performed, error data cannot be stored in the external storage unit, so that the data requested by the bus cannot realize chip logic real-time pipeline processing, data required to be processed in a current line must be cached in a chip, and memory consumption in the chip is caused. The technical scheme of the invention adopts the block type error diffusion image processing, and reduces the area of chip cache resources while supporting the dynamic block image processing. The image processing system shown in fig. 2 is beneficial to processing the first processing block, and reduces the consumption of memory resources in the chip. Take the first processing block as 32 x 32 pixels as an example. Since the error data in the vertical direction needs to be diffused to the processing block on the right side, 32 pixels need to be buffered, and thus 32-pixel storage space is required. Since it is necessary to spread the horizontal direction error data to the processing block on the lower side, 32 pixels are required to be buffered, and a buffer space in the horizontal direction is multiplexed when error diffusion is performed in the processing block. Therefore, by adopting the scheme, the chip only needs 64 × 32 bit of buffer space to complete the error diffusion image processing with any high resolution.
It should be noted that although the present application needs to write the vertical error data to an external storage unit, such as a memory of a computer, etc., through a bus, and this portion of storage space needs 4096 × 32 bits, this portion of resource consumption is not within a chip. Thereby reducing memory resource consumption within the chip.
The system structure and the application scenario described in the embodiment of the present invention are for more clearly illustrating the technical solution of the embodiment of the present invention, and do not constitute a limitation to the technical solution provided in the embodiment of the present invention, and it is known to those skilled in the art that the technical solution provided in the embodiment of the present invention is also applicable to similar technical problems with the evolution of the system structure and the occurrence of new application scenarios.
Those skilled in the art will appreciate that the system architecture shown in FIG. 1 is not intended to limit embodiments of the invention and may include more or fewer modules than shown, or some of the modules may be combined, or a different arrangement of modules.
Based on the above system configuration, various embodiments of the image processing method of the present invention are presented below.
Referring to fig. 3, fig. 3 is a flowchart illustrating an image processing method according to an embodiment of the present invention, where the image processing method can be applied to an image processing apparatus, such as the image processing apparatus in the image processing system structure shown in fig. 1. The image processing may include, but is not limited to, step S310, step S320, step S330, step S340, and step S350.
Step S310: image size information of an original image is acquired.
In this step, an error diffusion module in the image processing apparatus acquires image size information of the original image. Specifically, the image size information includes a second pixel height and a second pixel width of the original image.
Step S320: and acquiring a first processing block currently sent by the first image processing module, and block information and accumulated information corresponding to the first processing block.
In this step, the blocking information includes a first pixel height and a first pixel width of the first processing block, where the first pixel height is less than or equal to a preset maximum pixel height threshold, and the first pixel width is less than or equal to a preset maximum pixel width threshold.
It should be noted that, the first image processing module performs blocking processing on the whole original image. Referring to fig. 4, fig. 4 is a schematic diagram illustrating an image dynamic blocking process according to an embodiment of the present invention. The entire image width (i.e., the second pixel width) of an original image is W, and the entire image height (i.e., the second pixel width) is H. The first image processing module performs image blocking processing on the original image, namely, the whole picture is divided into m × n blocks. It should be noted that the block processing diagram of fig. 4 illustrates an arbitrary block method. In the drawings, (1, 1) to (m, n) identified on the respective process blocks indicate the process blocks of the m-th row and the n-th column only for convenience of understanding and description. It is not intended that the position information of each processing block is obtained after the block processing. Wherein the pixel width x of all processing blocks is less than or equal to a preset maximum pixel width threshold; the pixel height y is less than or equal to the maximum pixel height threshold. It can be understood that the first image processing module may obtain at least two processing blocks after performing the block processing on the original image, and the first image processing module may sequentially send the obtained processing blocks to the error processing module. It should be noted that the first processing block represents a processing block currently sent to the error diffusion module by the first image processing module. And, each processing block has corresponding block information including a pixel height y and a pixel width x representing the corresponding processing block.
It should be noted that the accumulated information includes accumulated row information and accumulated column information. The error diffusion module can sequentially acquire the processing blocks in the same whole image and the block information corresponding to the processing blocks, which are sent by the first image processing module. Specifically, the accumulated row information refers to an accumulated sum of pixel heights of all the received processing blocks, and the accumulated column information refers to an accumulated sum of pixel widths of all the received processing blocks.
In a specific embodiment, assuming that the maximum pixel width threshold and the maximum pixel height threshold are 32 pixels, the size of the maximum processing block that can be processed is set to be 32 × 32 pixels. The maximum processing block for image processing is 32 × 32 pixels, and dynamic blocking means that the scheme supports 32 × 32 and all the following processing block sizes: 1 x 1 to 32 x 32. It can be understood that, when the size of the processing block to be processed is 64 × 64 pixels, the internal cache space needs to be enlarged appropriately to meet the requirement, and the chip logic control in the present scheme is still applicable. Compared with the method of processing the whole image and processing the image in blocks, the method is beneficial to reducing the consumption of the internal storage resources of hardware and reducing the chip area occupied when the image is processed.
Step S330: and obtaining the position information of the first processing block in the original image according to the image size information, the block information and the accumulated information.
In this step, the error diffusion template obtains the position information of the first processing block in the original image according to the image size information, the block information and the accumulated information. Specifically, the error diffusion module acquires a second pixel height and a second pixel width of the original image according to the image size information; acquiring a first pixel height and a first pixel width of a first processing block according to the blocking information; obtaining row accumulated information and column accumulated information according to the accumulated information; obtaining the line information of the first processing block according to the line accumulation information, the second pixel height and the first pixel height; and obtaining the column information of the first processing block according to the column accumulated information, the second pixel width and the first pixel width.
It should be noted that the position information includes row information and column information of the first processing block in the original image. It should be noted that, in the chip hardware implementation process, only 4 registers are defined to respectively mark the head row, the tail row, the head column, and the tail column. And carrying out unified processing on the corresponding intermediate blocks. Therefore, the line information includes head line information, middle line information, and tail line information; the column information includes head column information, middle column information, and tail column information.
Specifically, obtaining the line information of the first processing block according to the line accumulation information, the second pixel height, and the first pixel height includes: when the row accumulated information is equal to the second pixel height, determining the row information of the first processing block as tail row information; or when the line accumulation information is equal to the first pixel height, determining the line information of the first processing block as the head line information; or, when the row accumulated information is greater than the first pixel height and less than the second pixel height, determining the row information of the first processing block as the middle row information.
Specifically, obtaining the column information of the first processing block according to the column accumulation information, the second pixel width and the first pixel width includes: when the column accumulated information is equal to the second pixel width, determining the column information of the first processing block as tail column information; or when the column accumulated information is equal to the first pixel width, determining the column information of the first processing block as the first column information; or, when the column accumulated information is greater than the first pixel width and less than the second pixel width, determining the column information of the first processing block as the middle column information.
In the process of realizing the chip hardware, only 4 registers are defined to respectively mark a first row of blocks, a last row of blocks, a leftmost column of blocks and a rightmost column of blocks, and middle processing blocks can be processed consistently due to no particularity. According to the method, the middle block is distinguished for processing according to the different positions of the rows and the columns of the processing blocks, so that the memory of a chip is saved, and the efficiency of processing the blocking error diffusion image is higher.
Step S340: first error information is obtained according to the position information.
In this step, the error diffusion template acquires first error information according to the position information of the processing block. The first error information includes first horizontal direction error data and first vertical direction error data. The first error information that needs to be obtained by the processing blocks at different positions is not exactly the same. Specifically, column information and row information of the first processing block in the original image are obtained according to the position information, when the column information is middle column information or tail column information, first horizontal direction error data are obtained from an external storage unit, and when the column information is first column information, the first horizontal direction error data are obtained from the first horizontal direction error data; when the line information is middle line information or end line information, first vertical direction error data is obtained from an internal vertical direction error data cache space, and when the line information is head line information, first horizontal direction error data is obtained from the line information.
Specifically, referring to fig. 5 for explanation, fig. 5 is a schematic diagram of error diffusion based on the image motion block shown in fig. 4 according to an embodiment of the present invention. In addition, some processing blocks do not necessarily need to be spread for data in either the vertical or horizontal direction. For example, the vertical direction error data of the rightmost processing block does not need to be right-diffused, and therefore the vertical direction error data does not need to be written into the internal vertical direction error data buffer space when the rightmost processing block is processed. Since the horizontal direction error data of the lowermost processing block does not spread to the lower side, it is not necessary to write the horizontal direction error data into the external storage unit. Similarly, the uppermost (i.e., top row) processing block does not need to read the horizontal direction error data of the external memory unit, and the leftmost (i.e., top column) processing block does not need to read the vertical direction error data buffered in the internal vertical direction error data buffer space.
When viewed in conjunction with the entire image, the error data is diffused from left to right due to the error diffusion template. Therefore, the error data of the first line of the whole image is not required to be diffused from the error data of the previous line, and similarly, the error data of the first column of the image is not required to be diffused from the error data of the left column. However, the first row processing block also needs to diffuse the error data of itself downward, and the first column processing block also needs to diffuse the error data of itself rightward.
Specifically, from a single block perspective: the processing block at the (m, 1) position is the leftmost (i.e. the first line) block, and since the error diffusion module diffuses from left to right, the processing block at the (m, 1) position does not receive error data diffusion from the left side, so that the cached error data in the vertical direction needs to be continuously diffused to the right side. Further, since the processing block at the (m, 1) position is the block of the last line, there is no processing block on the lower side (i.e., the next line), and therefore there is no need to spread the horizontal direction error data to the processing block of the next line, and there is no need to write the horizontal direction error data to the external memory unit.
As for the intermediate block, for example, the processing block of the (2, 2) position, it is necessary to receive the horizontal direction error data diffused from the processing block of the (1, 2) position on the upper side and the vertical direction error data diffused from the processing block of the (2, 1) position on the left side, while also diffusing new vertical direction error data obtained after completion of the intra-block error processing to the processing block on the right side and diffusing new horizontal direction error data to the processing block on the lower side. For the processing block of the (1, 1) position, the horizontal direction error data diffused from the upper side and the vertical direction error data diffused from the left side are not received, but the error data itself needs to be diffused. That is, the processing block at the (1, 1) position also needs to spread the horizontal direction error data to the processing block at the (2, 1) position, and spread the vertical direction error data to the processing block at the (1, 2) position. From the perspective of error data transfer, for the processing block at the (1, 1) position, the processing block at the (2, 1) position and the processing block at the (1, 2) position are both the processing blocks at the next stage of the processing block at the (1, 1) position. Similarly, the processing blocks in other positions also have the next-stage processing block.
In the process of realizing the chip hardware, only 4 registers are defined to respectively mark a first row of blocks, a last row of blocks, a leftmost column of blocks and a rightmost column of blocks, and middle processing blocks can be processed consistently due to no special property. By the method, the memory of the chip is saved, and the efficiency of processing the blocking error diffusion image is higher.
It should be noted that, when the position of the processing block is located in the first line and error data from the previous line cannot be acquired, error data in the horizontal direction owned by the processing block is diffused to the next line; when the position of the processing block is in the top row and error data from the left row cannot be acquired, the error data in the vertical direction owned by the processing block is diffused to the right row.
Step S350: and carrying out intra-block error diffusion processing on the first processing block according to the first error information and the error diffusion template to obtain second error information, wherein the second error information is used for carrying out intra-block error diffusion processing on a next-stage processing block of the first processing block.
In this step, the error diffusion module performs intra-block error diffusion processing on the first processing block according to the first error information and the error diffusion template to obtain second error information, where the second error information is used for processing a next-stage processing block of the first processing block. The second error information includes second horizontal direction error data and second vertical direction error data, and a processing block that needs to read the second horizontal direction error data or the second vertical direction error data of the first processing block is a next-stage processing block of the first processing block. And the next-stage processing block repeats the steps, acquires and utilizes the second error information of the response to complete the intra-block error diffusion processing aiming at the next-stage processing block, and the specific processing process of the next-stage processing block is not repeated herein.
It is understood that after a chip processes an image, it is stored in memory (e.g., a memory bank of a computer). The first processing block can be regarded as processing a complete image, and only the horizontal direction error data and/or the vertical direction error data need to be considered when processing the blocks (i.e., processing blocks). And storing the first processing block after the intra-block error diffusion processing is finished in the memory. It should be noted that, the number of processing blocks processed by the error diffusion module is not specifically limited in the present application, and the processing blocks may be sequentially processed according to an actual image blocking condition, and error diffusion processing may be performed on each processing block until a complete image is processed.
The diffusion error algorithm is to diffuse the error of pixel pixels. For example, in an ARGB color mode, the input R component is 8 bits, but the output R component is required to be 6 bits, so that the low-order 2 bits are errors, and the 2 bits need to be diffused, so that a stripe dark line and the like cannot occur during image display. Referring to fig. 6, fig. 6 is a schematic diagram of an error diffusion template according to an embodiment of the present invention. X in the error diffusion template refers to a pixel point to be converted, and the number represents the proportion of the melon score error of the surrounding pixel points. In fig. 6, error data of a pixel (pixel) at an X point needs to be transmitted 2/4 to a pixel at the right side, needs to be diffused 1/4 to a pixel at the lower side, needs to be diffused 1/4 to a pixel at the lower right side, and then each pixel is diffused in this way. The error template is thus error diffused in a manner from the upper left to the lower right of the image. It can be understood that the ratio of the pixel point melon division errors around can be changed, for example, the error data of the pixel (pixel) of the X point can be transmitted 1/4 to the pixel point on the right side, needs to be diffused 2/4 to the pixel point on the lower side, needs to be diffused 1/4 to the pixel point on the lower right side, and then each pixel point is diffused in this way; or error data of a pixel (pixel) of the X point can be transmitted 2/4 to a pixel on the right side, needs to be diffused 2/4 to a pixel on the lower side, needs to be diffused 0/4 to a pixel on the lower right side, and then each pixel is diffused in this way; or the error data of the pixel (pixel) of the X point may be transmitted 1/4 to the pixel on the right side, needs to be diffused 1/4 to the pixel on the lower side, needs to be diffused 2/4 to the pixel on the lower right side, and then each pixel is diffused in this way. By using the diffusion error template, the efficiency of processing the image can be improved, and the quality of the image can be ensured.
Specifically, the operations to be performed are: to reduce a processing block from 8bit storage to 5bit storage, suppose that the X point original pixel is binary 10000100 (i.e., decimal 132). Then the pixel at that point would have to discard the lower three bits to 10000000 (i.e., decimal 128) (actual memory stores 5 bits), so there is 4 error data, and the 4 errors would need to be diffused to the surroundings. When the error diffusion template shown in fig. 6 is used, it is necessary to diffuse the error data downward at a rate of 1/4. I.e. to the lower pixel point by 1. If the lower pixel is 10000110 (decimal 134), then adding 1 is 10000111 (decimal 135). The target is stored as 5 bits and thus it is actually 10000000 (decimal 128) into memory, so the lower pixel needs to be diffused 111 (decimal 7) to the surrounding pixels. Error diffusion is therefore a progressive and additive process. And carrying out intra-block error diffusion processing on the processing block according to the error processing module, the horizontal error data and/or the vertical error data until the pixel points in the processing block are processed.
It should be noted that, in addition to the error diffusion template shown in fig. 6 mentioned in the present application, other error diffusion templates, such as a Jarris-judic-Ninke diffusion template, a Sierra diffusion template, etc., may be used. The error diffusion template used in the present application is not particularly limited, as long as the error diffusion image processing can be completed.
After the first processing block is subjected to the intra-block error diffusion processing based on the first error information and the error diffusion template to obtain the second error information, the second error information is further processed based on the position information of the first processing block. First, updated second error information is acquired after the first processing block is processed, the second error information including second horizontal direction error data and a second vertical direction error count. Then, position information of the first processing block is acquired, the position information including row information and column information. The second error information is processed based on the position information of the first processing block. That is, when the column information is the first column information or the middle column information, the second vertical direction error data is written into the internal vertical direction error data buffer space, and when the column information is the last column information, the second vertical direction error data does not need to be written into the internal vertical direction error data buffer space. When the line information is head line information or middle line information, the second horizontal direction error data is written in the external storage unit, and when the line information is tail line information, the second horizontal direction error data is not required to be written in the external storage unit. This process advantageously stores the second error information for use by the error handling module when processing the next block.
Specifically, the second horizontal direction error data is written to the external storage unit through the bus. The second vertical direction error data can use an internal vertical direction error data buffer space with the size of 32 pixels to store error information due to pipeline processing in hardware, and a storage unit in a chip is used. The internal vertical direction error data buffer space does not limit SRAM (static random access memory), for example, using FIFO: error diffusion read and write can be done in first-out. So that the subsequent processing blocks can acquire the error data in the horizontal direction from the external storage unit or acquire the error data in the vertical direction from the internal buffer space. And partial data is stored in the external storage unit, so that internal storage resources are saved.
It should be noted that, since the image processing apparatus of this embodiment can implement the image processing method according to any of the foregoing embodiments, the image processing apparatus of this embodiment and the image processing method according to any of the foregoing embodiments have the same technical principle and the same technical effect, and are not described herein again to avoid redundant content.
In addition, referring to fig. 7, fig. 7 is an image processing apparatus 700 according to an embodiment of the present invention, where the image processing apparatus 700 includes: memory 720, processor 710, and computer programs stored on the memory and executable on the processor.
The processor 710 and the memory 720 may be connected by a bus or other means.
The memory 720, which is a non-transitory computer readable storage medium, may be used to store non-transitory software programs as well as non-transitory computer executable programs. Further, memory 720 may include high speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, the memory optionally includes memory located remotely from the processor, and these remote memories may be connected to the processor through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
It should be noted that the image processing apparatus in this embodiment can be applied to, for example, the image processing apparatus in the embodiment shown in fig. 1, the image processing apparatus in this embodiment can form a part of, for example, the system architecture in the embodiment shown in fig. 1, and these embodiments all belong to the same inventive concept, so these embodiments have the same implementation principle and technical effect, and are not described in detail here.
The non-transitory software programs and instructions required to implement the image processing method of the above-described embodiment are stored in the memory 720, and when executed by the processor, perform the image processing method of the above-described embodiment, for example, perform the method steps S310 to S350 in fig. 3 described above.
In addition, an embodiment of the present invention also provides an image processing system including an image processing apparatus, an external storage unit, wherein the data processing apparatus can be applied as, for example, the image processing apparatus in the embodiment shown in fig. 1. The image processing system in the present embodiment can constitute a system architecture in the embodiment shown in fig. 1, for example, and these embodiments all belong to the same inventive concept, so these embodiments have the same implementation principle and technical effect, and are not described in detail here.
The above-described apparatus embodiments or system embodiments are merely illustrative, wherein elements described as separate components may or may not be physically separate, may be located in one place, or may be distributed over multiple network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
Furthermore, an embodiment of the present invention also provides a computer-readable storage medium, which stores computer-executable instructions, which are executed by a processor or a controller, for example, by a processor in the above-mentioned apparatus embodiment, and can make the above-mentioned processor execute the image processing method in the above-mentioned embodiment, for example, execute the above-mentioned method steps S310 to S350 in fig. 3.
One of ordinary skill in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
While the preferred embodiments of the present invention have been described in detail, it will be understood by those skilled in the art that the foregoing and various other changes, omissions and deviations in the form and detail thereof may be made without departing from the scope of this invention.
Claims (9)
1. An image processing method applied to an image processing apparatus, the image processing method comprising:
acquiring image size information of an original image;
acquiring a first processing block currently sent by a first image processing module, and block information and accumulated information corresponding to the first processing block;
obtaining the position information of the first processing block in the original image according to the image size information, the blocking information and the accumulation information;
acquiring first error information according to the position information;
performing intra-block error diffusion processing on the first processing block according to the first error information and an error diffusion template to obtain second error information, wherein the second error information is used for performing the intra-block error diffusion processing on a next-stage processing block of the first processing block;
wherein the position information includes row information and column information of the first processing block in the original image, the first error information includes first horizontal direction error data and first vertical direction error data, and the acquiring the first error information based on the position information includes:
obtaining the column information and the row information of the first processing block in the original image according to the position information;
when the column information is middle column information or tail column information, acquiring first horizontal direction error data from an external storage unit;
when the column information is the first column information, acquiring first horizontal direction error data from the column information;
when the line information is middle line information or tail line information, acquiring first vertical direction error data from an internal vertical direction error data cache space;
and when the line information is the first line information, acquiring first horizontal direction error data from the line information.
2. The method according to claim 1, wherein the block information comprises a first pixel height and a first pixel width of the first processing block, the first pixel height being less than or equal to a preset maximum pixel height threshold, the first pixel width being less than or equal to a preset maximum pixel width threshold.
3. The method according to claim 2, wherein the position information includes row information and column information of the first processing block in the original image, and the obtaining of the position information of the first processing block in the original image based on the image size information, the block information, and the accumulated information includes:
acquiring a second pixel height and a second pixel width of the original image according to the image size information;
acquiring the first pixel height and the first pixel width of the first processing block according to the blocking information;
obtaining row accumulation information and column accumulation information according to the accumulation information;
obtaining the line information of the first processing block according to the line accumulation information, the second pixel height and the first pixel height;
and obtaining the column information of the first processing block according to the column accumulated information, the second pixel width and the first pixel width.
4. The method of claim 3, wherein obtaining the line information of the first processing block according to the line accumulation information, the second pixel height, and the first pixel height comprises:
determining the line information to be the tail line information when the line accumulation information is equal to the second pixel height;
or when the line accumulation information is equal to the first pixel height, determining the line information as the head line information;
or, when the row accumulated information is greater than the first pixel height and less than the second pixel height, determining the row information as the middle row information.
5. The method according to claim 4, wherein said deriving the column information of the first processing block according to the column accumulated information, the second pixel width and the first pixel width comprises:
determining the column information to be the tail column information when the column accumulated information is equal to the second pixel width;
or, when the column accumulated information is equal to the first pixel width, determining the column information as the head column information;
or, when the column accumulated information is greater than the first pixel width and less than a second pixel width, determining the column information as the middle column information.
6. The image processing method according to claim 5, wherein performing intra-block error diffusion processing on the first processing block according to the first error information and an error diffusion template to obtain second error information, the second error information being used after processing a next-stage processing block of the first processing block, further comprising:
acquiring updated second error information after processing the first processing block, wherein the second error information comprises second horizontal direction error data and second vertical direction error data;
acquiring the position information of the first processing block, wherein the position information comprises row information and column information;
when the column information is the head column information or the middle column information, writing the second vertical direction error data into the internal vertical direction error data cache space;
and writing the second horizontal direction error data into the external storage unit when the line information is the first line information or the middle line information.
7. An image processing system, characterized in that the image processing system comprises:
an image processing apparatus including a first image processing module and an error diffusion module;
the first image processing module is configured to perform blocking processing on a whole original image to obtain a first processing block and blocking information corresponding to the first processing block, and transmit the first processing block and the blocking information to an error diffusion module;
the error diffusion module is used for acquiring image size information of an original image, acquiring a first processing block currently sent by the first image processing module, and blocking information and accumulation information corresponding to the first processing block, acquiring position information of the first processing block in the original image according to the image size information, the blocking information and the accumulation information, acquiring first error information according to the position information, and performing intra-block error diffusion processing on the first processing block according to the first error information and an error diffusion template to acquire second error information, wherein the second error information is used for performing the intra-block error diffusion processing on a next-stage processing block of the first processing block;
an external storage unit for storing first horizontal direction error data in the first error information;
wherein the position information includes row information and column information of the first processing block in the original image, the first error information includes first horizontal direction error data and first vertical direction error data, and the acquiring the first error information based on the position information includes:
obtaining the column information and the row information of the first processing block in the original image according to the position information;
when the column information is middle column information or tail column information, acquiring first horizontal direction error data from an external storage unit;
when the column information is the first column information, acquiring first horizontal direction error data from the column information;
when the line information is middle line information or tail line information, acquiring first vertical direction error data from an internal vertical direction error data cache space;
and when the line information is the first line information, acquiring first horizontal direction error data from the line information.
8. An image processing apparatus comprising: memory, processor and computer program stored on the memory and executable on the processor, characterized in that the processor implements the image processing method according to any one of claims 1 to 6 when executing the computer program.
9. A computer storage medium having stored thereon computer-executable instructions for performing the image processing method of any one of claims 1 to 6.
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