CN114357941A - Method and system for optimizing region with overproof current density of integrated circuit layout - Google Patents
Method and system for optimizing region with overproof current density of integrated circuit layout Download PDFInfo
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Abstract
The application discloses an integrated circuit layout current density superstandard area optimization method and a system, which belong to the field of integrated circuit optimization design and mainly comprise the following steps: based on the accurate calibration of the integrated circuit layout area with the current density exceeding standard, two types of areas with the current density exceeding standard are provided according to the distribution rule of the calibration area; aiming at the first class of overproof areas, based on the subdivision grid cells, the area of the overproof areas is increased on the same layer by adopting a neighbor expansion method, a layer with redundant space is found under the condition that the expandable area of the same layer is insufficient, and a method optimizing circuit for increasing the area of a layout polygon is adopted at the corresponding position of the layer by adopting cell search and the neighbor expansion method; aiming at the second class of overproof areas, a circuit is optimized by adopting a method of uniformly arranging new through holes around the through holes V; the method and the device realize division of two types of current density overproof areas in the integrated circuit layout and targeted optimization of the overproof areas.
Description
Technical Field
The application belongs to the field of integrated circuit optimization design, and particularly relates to a method and a system for optimizing an area with overproof integrated circuit layout current density.
Background
At present, the calibration of the region with overproof current density on the integrated circuit layout is usually the calibration of a rectangular region, the calibration method is effective for the layout shape with simple structure in the early stage, can quickly identify the position with overproof current density from the calibrated area, thereby optimizing and modifying the designed layout, but along with the increasing complexity of the shape of the integrated circuit layout, the original calibration method is no longer effective, which is particularly shown in the fact that a large number of bent strip-shaped layout polygons exist, if the current density on the layout polygon exceeds the standard, according to the traditional calibration method, the exceeding rectangular area including the whole strip layout polygon is included, a large number of layout polygons which do not exceed the standard are also included in the rectangular area, this calibration is therefore essentially ineffective and does not allow accurate retrieval of useful information from the calibrated area. Because the calibration is carried out by the traditional method, a user obtains rectangles at the lower left corner and the upper right corner of the frame-fixed layout polygon with the exceeding-standard current, when the difference between the lower left corner and the upper right corner is far, the rectangular frame contains a large number of layout polygons which do not exceed the standard, and the user cannot accurately determine which layout polygons in the rectangular frame are really exceeding the standard, so that the optimal design can not be carried out only on the layout polygons which exceed the standard.
The direct current voltage drop analysis is carried out on a new layout design model according to the latest method for calibrating the area with the overproof current density of the integrated circuit layout, so that the area with the overproof current density can be found out, and the accurate calibration of the area with the overproof current density of the integrated circuit layout is realized.
Judging the type of the current density exceeding based on the type of the boundary of the exceeding area: if all the boundaries of the region with the current density exceeding the standard are also the boundaries of the layout polygon at the same time, the current density exceeding the standard in the whole layout polygon region is shown; if only a part of the boundary of the region with the excessive current density is not the boundary of the layout polygon, the current density is determined to be the local excessive formed by the starting of the via hole. For the integrated circuit layout with the two types of current density exceeding areas, no scheme for optimizing only the current density exceeding areas exists at present.
Disclosure of Invention
In order to overcome the defects in the prior art, the application provides a method and a system for optimizing an area with overproof integrated circuit layout current density.
In a first aspect, the present application provides a method for optimizing an area with overproof current density in an integrated circuit layout, comprising the following steps:
step S1: calculating the current density of the grid split unit in each layer of integrated circuit layout, and judging whether a current density overproof area exists or not by calibrating the current density overproof area;
if the current density exceeds the standard area, the step S2 is executed;
if the current density does not exceed the standard, the step S10 is executed;
step S2: defining two types of current density exceeding areas according to the distribution rule of the current density exceeding areas, and judging which type of exceeding areas the current density exceeding areas belong to;
if the current density exceeding area is judged to be the first type exceeding area, the step S3 is executed;
if the current density exceeding area is judged to be the second type exceeding area, the step S8 is carried out;
step S3: determining a potential highest point A and a potential lowest point B of a first-class overproof area, and calculating a current density average value of the first-class overproof area;
step S4: increasing the area of the first class of exceeding area on the current layer according to the ratio of the current density average value of the first class of exceeding area to the current density allowable maximum value;
step S5: updating the current density average value of the first type of exceeding area, judging whether the area of the first type of exceeding area is successfully increased, if so, turning to the step S9, otherwise, turning to the step S6;
step S6: setting Stotal=SnewJudging whether a layer with redundant space exists between the projections corresponding to the A and the B, if so, turning to the step S7, otherwise, turning to the step S10; said StotalFor the increased total area, S, of the superscalar region of the first kindnewThe area of the first-class superscalar region after the increase is realized in step S4;
step S7: increasing a via hole V for communicating the overproof region to the current layerA, VBAdding a via V capable of communicating with the layer having the redundant spaceA, VBCoated with copperEdge shape, obtaining updated StotalStep S5 is performed;
step S8: defining a via hole nearest to the maximum current density as a via hole V, and uniformly arranging new via holes around the via hole V;
step S9: obtaining a new circuit layout design model, and turning to the step S1;
step S10: and finishing the optimization.
The two types of current density exceeding areas defined according to the distribution rule of the current density exceeding areas comprise the following categories:
the first class of overproof areas are areas which comprise a complete polygon in an integrated circuit layout, and the current density of all mesh subdivision units in the areas exceeds the standard;
the second type of overproof area is a local area in a polygon contained in the integrated circuit layout, and the current density of the mesh subdivision unit in the local area only exceeds the standard in the polygon.
The formula for calculating the average value of the current density of the first type of standard exceeding area is as follows:
in the formula, SeFor the area of the mesh division unit e, JeIs the current density of the mesh division unit e,
is the average value of the current density,
indicating a summation.
The specific steps of increasing the area of the first-class superstandard area on the current layer are as follows:
s4.1 calculating the average value J of the current density of the first-class overproof areaaveAnd the maximum value J of the allowable current densitymaxThe ratio of (A) to (B):
(ii) a Calculating the initial area S of the layout polygon P in which the first class of overproof region is located according to the area calculation formula of the layout polygon0；
Step S4.2: for all grid subdivision cells e as boundary cells with copper-clad propertybndIf no such neighbor unit e existsnbrSaid neighbor unit enbrIs insulating, and the neighbor cell enbrIf all the vertexes of the graph are only positioned on the edge of the layout polygon P or in the insulating area, the area of the first class of superstandard area is increased unsuccessfully, an insufficient space mark is added, and the step S4.5 is carried out; neighbor cell e if there is an attribute of insulationnbrThen step S4.3 is performed;
step S4.3: the neighbor unit enbrIs set to be covered with copper, the neighbor unit enbrAdding the graph polygon P and the mesh generation unit e for updating the graph polygon PbndEdge-to-neighbor cell e correlated as a border cellnbrAssociated edge, the neighbor unit enbrBecoming a new border cell; the neighbor unit enbrAdding the area of the first class of standard exceeding area into the area of the layout polygon P in which the first class of standard exceeding area is positioned, and using SnewRepresenting the updated area of the layout polygon P;
step S4.4: comparing r with
If it is satisfied
If so, the area of the first class of overproof area is successfully increased, and the step S4.5 is carried out, otherwise, the step S4.2 is carried out;
step S4.5: and the step of increasing the area of the first type exceeding area is finished.
The layer with the redundant space is added with a through hole V capable of being communicatedA, VBThe concrete steps of the copper-clad polygon comprise:
step S7.1: searching the neighbors of the mesh generation unit by adopting a neighbor search algorithmFrom via hole VATo the via hole VBSearching a mesh division unit with the insulating property, putting the searched mesh division unit with the insulating property into a set T, and converting the mesh division unit in the set T into a mesh division unit with the copper-clad property;
step S7.2: calculating the area of the grid subdivision unit with the property of covering copper in the set T to obtain the total area S of the area which equally divides the first class of overproof area currenttotal；
Step S7.3: increasing the mesh subdivision units in the set T according to the steps S7.1-S7.2 to increase the total area of the area bisecting the first type of overproof area current until the requirement is met
Or a neighboring unit with insulation property does not exist, and a through hole V capable of being communicated is added on a layer with redundant spaceA，VBThe step of covering the copper polygon is ended, S0The initial area of the layout polygon P where the first class of standard exceeding area is located is r is the ratio of the average value of the current density of the first class of standard exceeding area to the maximum value of the allowed current density.
The method for searching the neighbors of the mesh generation unit by adopting the neighbor search algorithm comprises the following specific steps:
step S7.1.1: set the vertex to contain the via hole VAThe mesh division unit is tAThe vertex comprises a via VBThe mesh division unit is tB(ii) a Setting a first variable t of a mesh generation unitALet t = tASetting a set T = { T }, setting a second variable previous of a mesh generation unit, and enabling the previous = T;
step S7.1.2: take i = rand (1, n)e) Taking m as the ith edge of the mesh division unit t; wherein rand (1, n)e) Represent 1 to neRandom integer of between, neThe number of edges of the mesh dividing unit t is shown; let t be the neighbor of t sharing the ith edge m with ti；
Step S7.1.3: if t isBIs not a neighbor that shares edge m with previous, and tBOn both sides of edge m with previousGo to step S7.1.4, otherwise go to step S7.1.5;
step S7.1.4: setting previous = t, t = tiIf t isiIs not in the set T, and TiAny vertex of (a) does not belong to any vertex of a copper-clad polygon, and t isiAdding the mixture into the set T; go to step S7.1.2;
step S7.1.5: if t isBInstead of a neighbor sharing an edge m with previous, set i = i +1 if i>neSetting i = 1; taking the ith edge with m as t, and setting the neighbor of t sharing the ith edge m with t as tiGo to S7.1.3; otherwise, if tBIf the neighbor shares the edge m with previous, go to step S7.1.6;
step S7.1.6: will tBAnd adding the mixture into the set T, and finishing.
The layer with the redundant space is an insulation area without copper cladding at the corresponding projection positions of the layers A and B, and a line segment formed between the projections corresponding to the layers A and B is not intersected with the edge of any layout polygon.
The via hole VA, VBAdding a via hole V for communicating the layer of the first class overproof area and the layer with the redundant space at the projection position corresponding to A and BA, VB。
The new via holes are uniformly distributed on the circumference of which the radius is r from the radius of the via hole V, the radius of the new via holes is the same as that of the via hole V, the layers spanned by the newly-added via holes are the same as that of the via hole V, the number of the via holes is 3-6, and the radius of the r is 5-50 times that of the via hole V.
In a second aspect, the present application provides a system for optimizing an area with overproof current density in an integrated circuit layout, including: the system comprises a first module, a second module, a third module, a scheme 1 module, a scheme 2 module, a scheme 3 module, a fourth module, a fifth module, a sixth module and a seventh module, wherein the first module is respectively connected with the second module and the seventh module, the second module is respectively connected with the third module and the scheme 3 module, the fourth module is respectively connected with the fifth module and the sixth module, the fifth module is respectively connected with the scheme 2 module and the seventh module, the third module is connected with the scheme 1 module, the scheme 1 module and the scheme 2 module are respectively connected with the fourth module, and the sixth module is connected with the first module;
the first module is used for calculating the current density of the grid split unit in each layer of integrated circuit layout and judging whether a current density overproof area exists or not by calibrating the current density overproof area; if the current density exceeds the standard area, the second module is switched to; if no current density exceeds the standard area, the seventh module is switched to;
the second module is used for defining two types of current density exceeding areas according to the distribution rule of the current density exceeding areas and judging which type of exceeding areas the current density exceeding areas belong to; if the current density exceeding area is judged to be a first class exceeding area, the current density exceeding area is transferred to a third module; if the current density exceeding area is judged to be a second class exceeding area, executing a module of a scheme 3;
the third module is used for determining a potential highest point A and a potential lowest point B of the first-class overproof area and calculating a current density average value of the first-class overproof area;
the module in the scheme 1 is used for increasing the area of the first type exceeding area on the current layer according to the ratio of the average current density value of the first type exceeding area to the maximum allowable current density value;
the fourth module is used for updating the current density average value of the first class of standard exceeding area, judging whether the area of the first class of standard exceeding area is successfully increased, if so, turning to the sixth module, otherwise, turning to the fifth module;
the fifth module is used for setting Stotal=SnewJudging whether a layer with redundant space exists between the projections corresponding to the A and the B, if so, executing the module of the scheme 2, otherwise, turning to a seventh module; said StotalFor the increased total area, S, of the superscalar region of the first kindnewIncreased area of superscalar region of the first class implemented for execution of module of scheme 1
The module of the scheme 2 is used for increasing a via hole V for communicating the superstandard area to the current layerA, VBAdding a via V capable of communicating with the layer having the redundant spaceA, VBThe copper-clad polygon; obtaining updatesS oftotalGo to the fourth module;
the module in the scheme 3 is used for defining the via hole closest to the maximum current density as a via hole V, and uniformly arranging new via holes around the via hole V;
the sixth module is used for obtaining a new circuit layout design model and turning to the first module;
the seventh module is configured to end the optimization.
The beneficial effect that this application reached:
the method and the device are based on accurate calibration of the region with the excessive current density of the integrated circuit layout, provide two types of regions with the excessive current density according to the distribution rule of the region with the excessive current density, and realize the optimization of the integrated circuit layout aiming at the two types of regions with the excessive current density.
Drawings
FIG. 1 is a flowchart of a method for optimizing an IC layout region with excessive current density according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a system for optimizing an integrated circuit layout area with an excessive current density according to an embodiment of the present application;
fig. 3 is an exemplary diagram of two types of superstandard areas subdivided on a layout polygon mesh according to the embodiment of the present application.
Detailed Description
The present application is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present application more clearly, and the protection scope of the present application is not limited thereby.
In a first aspect, the present application provides a method for optimizing an area with overproof current density in an integrated circuit layout, as shown in fig. 1, including the following steps:
step S1: calculating the current density of the grid split unit in each layer of integrated circuit layout, and judging whether a current density overproof area exists or not by calibrating the current density overproof area;
if the current density exceeds the standard area, the step S2 is executed;
if the current density does not exceed the standard, the step S9 is executed;
step S2: defining two types of current density exceeding areas according to the distribution rule of the current density exceeding areas, and judging which type of exceeding areas the current density exceeding areas belong to;
if the current density exceeding area is judged to be the first type exceeding area, the step S3 is executed;
if the current density exceeding area is judged to be the second type exceeding area, the step S8 is carried out;
step S3: determining a potential highest point A and a potential lowest point B of a first-class overproof area, and calculating a current density average value of the first-class overproof area;
step S4: increasing the area of the first class of exceeding area on the current layer according to the ratio of the current density average value of the first class of exceeding area to the current density allowable maximum value;
step S5: updating the current density average value of the first type of exceeding area, judging whether the area of the first type of exceeding area is successfully increased, if so, turning to the step S9, otherwise, turning to the step S6;
step S6: setting Stotal=SnewJudging whether a layer with redundant space exists between the projections corresponding to the A and the B, if so, turning to the step S7, otherwise, turning to the step S10; said StotalFor the increased total area, S, of the superscalar region of the first kindnewThe area of the first-class superscalar region after the increase is realized in step S4;
step S7: increasing a via hole V for communicating the overproof region to the current layerA, VBAdding a via V capable of communicating with the layer having the redundant spaceA, VBTo obtain updated StotalStep S5 is performed;
step S8: defining a via hole nearest to the maximum current density as a via hole V, and uniformly arranging new via holes around the via hole V;
step S9: obtaining a new circuit layout design model, and turning to the step S1;
step S10: and finishing the optimization.
To more clearly illustrate the optimization for the two types of current exceeding regions, the following is detailed by taking fig. 3 as an example:
step S1: calculating the current density of a grid splitting unit in each layer of integrated circuit layout (summarized by layers in subsequent steps), and judging whether a current density exceeding area exceeds the standard or not by calibrating the current density exceeding area, wherein the current density exceeding area is the maximum value allowed by the current density, and the current density at any position of the area is larger than the current density;
if the current density exceeds the standard area, the step S2 is executed;
if the current density does not exceed the standard, the step S10 is executed;
the specific method for calibrating the area with the excessive current density comprises the following steps:
mesh subdivision is carried out on the integrated circuit layout, and the current density of mesh subdivision units in each layer of layout is calculated by adopting an electromagnetic field numerical calculation method; identifying the mesh subdivision units with the current density exceeding the standard based on the current density of the mesh subdivision units in each layer of layout; and identifying the communicated mesh division units by adopting a neighbor search method based on the identified mesh division units with the current density exceeding the standard to form communicated mesh division unit areas, and setting edges corresponding to the mesh division units without neighbors as boundaries of the communicated mesh division unit areas aiming at each communicated mesh division unit area. The details are as follows:
the method for mesh subdivision of the integrated circuit layout and calculation of the current density of the mesh subdivision units in each layer of the layout by adopting an electromagnetic field numerical calculation method comprises the following steps:
simplifying the three-dimensional electric field model of the integrated circuit into a multilayer two-dimensional electric field model, and performing mesh subdivision on each layer of integrated circuit layout of the two-dimensional electric field model;
dispersing a functional corresponding to a differential equation formed by the direct current electric field two-dimensional model on a grid dividing unit, taking an extreme value and enabling the extreme value to be zero to obtain a finite element stiffness matrix equation set, and solving the finite element stiffness matrix equation set to obtain potential distribution on each layer of flat plate of the integrated circuit;
and calculating the current density distribution of the field, namely the current density of the grid subdivision unit in each layer of layout according to the potential distribution on each layer of flat plate of the integrated circuit.
The three-dimensional electric field model of the integrated circuit is simplified into a multilayer two-dimensional electric field model, and the specific calculation is as follows:
the three-dimensional model of the DC electric field of the multilayer integrated circuit refers to the conductivity in the DC electric field model
Potential of the electrodeuThe distribution of (a) is a function of the three-dimensional spatial coordinates (x, y, z), i.e.:
，
which satisfies the following equation (1) and boundary condition (2):
in the formula (2), the reaction mixture is,
is a boundary of the first type and is,nis normal to the boundary of the second type,
is an electric potentialuAt the first kind boundary
Value of above, using
It is shown that,
is the body electricity of an external circuitA flow density;
aiming at the three-dimensional model of the multilayer integrated circuit direct current electric field, establishing a functional of the two-dimensional model of each layer of integrated circuit direct current electric field:
in the formula (I), thehIs the thickness of the metal layer or layers,
for subdividing cells into cellseThe electrical conductivity of (a);
for subdividing cells into cellseThe potential of (a);
for subdividing cells into cellseThe surface of (a) is provided with,
surface current density generated for external excitation, saidI(u)In order to be a functional function,l e representing mesh generation uniteThe edge of (2).
The method for identifying the mesh subdivision units with the current density exceeding the standard based on the current density of the mesh subdivision units in each layer of layout comprises the following steps:
based on the mesh generation units, calculating the current density of each mesh generation unit of all layers by using a field current density distribution formula;
and judging whether the current density of each mesh division unit of all the layers is greater than a preset current density threshold, if so, setting the HOT spot state of the mesh division unit to be HOT, and if not, setting the HOT spot state to be COLD.
Recording a set stored by all the grid subdivision units with HOT states as a HOT area set H, and recording a set formed by at least one grid subdivision unit with 0 neighbor or COLD neighbor grid subdivision unit in the current HOT area set H as a peripheral grid subdivision unit set F;
step S1.1: setting the current processing hot spot area as q to 1, and setting a current hot spot area set HqIf the current peripheral grid subdivision unit set F is empty, setting the sequence number of the current processing layer as layer 1;
step S1.2: calculating neighbors of all mesh generation units of the current first layer; setting the mesh generation unit v of the current processing to be 1, and setting the maximum value J of the current densitymaxIs 0; setting a current calibration boundary set BqIs empty; setting the processing states of all mesh generation units of the current first layer as FRESH;
step S1.3: checking the state of the v mesh division unit;
step S1.3. A: if the processing state of the v-th mesh generation unit is DONE or the hot spot state is COLD, setting v to v +1, and going to step S1.4;
step S1.3. B: comparing the current density J of the v-th mesh division unitvWith the maximum value J of the current densitymax，Jv>JmaxThen update JmaxSo that Jmax＝Jv；Jv<＝JmaxThen J ismaxThe change is not changed;
step S1.3. B.1: adding the v-th mesh generation unit into a current peripheral mesh generation unit set F;
step S1.3. B.2: judging whether the set F is empty, if the set F is empty, judging the current JmaxAs the current hot spot region HqMaximum current density of, current calibration boundary set BqAs the current hot spot region HqDemarcated boundary of, increasing HqTo set H, reset the current density maximum JmaxTo 0, set q ═ q +1, set the current calibration boundary set BqIf the current hotspot region set is empty, setting a current hotspot region set HqIf the value is null, setting v to v +1, and going to step S1.4;
step S1.3. B.3: if the set F is not empty, taking out any mesh generation unit p in the set F, and deleting the mesh generation unit p from the set F;
step S1.3. B.4: judging the processing state of the mesh generation unit p, and if the processing state of the mesh generation unit p is DONE, turning to the step S1.3. B.2;
step S1.3. B.5: finding Nbr neighbors p of p1,p2,pk,...pNbrK is more than or equal to 1 and less than or equal to Nbr, k represents the kth edge of the mesh subdivision unit p, Nbr is the total number of p edges, and pkThe neighbor mesh generation unit represents the k-th edge of the common mesh generation unit p, the processing state of the mesh generation unit p is set to be DONE, and k is 1;
step S1.3. B.6: judgment of pkWhether or not it is equal to zero, when pkEqual to zero, indicating that there is no mesh subdivision unit with shared edge with the kth edge of the mesh subdivision unit p, adding the kth edge of the mesh subdivision unit p to the current calibration boundary set BqAnd (4) going to step S1.3. B.10;
step S1.3. B.7: judgment of pkProcessing state if pkThe processing state of (1) is DONE, and the step S1.3.B.10 is carried out;
step S1.3. B.8: judgment of pkIf p is a hot spot statekThe hot spot state of the grid subdivision unit is COLD, and the kth edge of the grid subdivision unit is added into the current calibration boundary set BqIn, setting pkThe treatment state of (1) is DONE, and the step S1.3.B.10 is carried out;
step S1.3. B.9: p is to bekAdding the current peripheral grid subdivision unit set F, and comparing pkCurrent density of (d) and current density maximum value JmaxSize, if pkIs not more than the current density maximum value Jmax，JmaxNot updated if pkIs greater than the current density maximum value JmaxUpdate JmaxIs pkCurrent density of (d);
step S1.3. B.10: setting k to be k +1, judging whether k is larger than Nbr, if k is larger than Nbr, then going to step S1.3.B.2, and if k is not larger than Nbr, then going to step S1.3. B.6;
step S1.4: comparing v with the number of the mesh generation units of the current first layer, and if v is less than the number of the mesh generation units of the current first layer, turning to the step S1.3;
step S1.5: setting layer + 1;
step S1.6: comparing the layer with the total layer number of the integrated circuit, and if the layer is less than the total layer number of the integrated circuit, turning to step S1.2;
step S1.7: and exiting the flow and finishing the algorithm.
Step S2: and defining two types of current density exceeding areas according to the distribution rule of the current density exceeding areas, and judging which type of exceeding area the current density exceeding areas belong to. If the current density exceeding area is judged to be the first type exceeding area, the step S3 is executed; if the current density exceeding area is judged to be the second type exceeding area, the step S8 is carried out;
the two types of current density exceeding areas are defined as follows: the first class of overproof areas are areas which comprise a complete polygon in an integrated circuit layout, and the current density of all mesh subdivision units in the areas exceeds the standard; this embodiment is a hatched portion as shown by 1 in fig. 3;
the second type of overproof area is a local area in a polygon contained in the integrated circuit layout, and the current density of the mesh subdivision unit of the local area only exceeds the standard in the polygon; this embodiment is shown as a shaded portion at 2 in fig. 3.
In the specific implementation of this embodiment, the method for calibrating the current density exceeding area is adopted, and the neighbor search method is adopted to identify the connected mesh division units to form the connected mesh division unit area, so that it is easy to determine which kind of exceeding area the optimized integrated circuit board diagram belongs to.
Based on the two types of exceeding areas, respectively adopting corresponding optimization schemes to obtain a new layout design model, returning to the step S1, further performing direct-current voltage drop analysis on the new layout design model, finding out the current density exceeding areas again, and continuing the same cyclic iterative optimization until all the current density exceeding areas are eliminated or no layer with redundant space is found for optimization.
Step S3: if the current density exceeding area is judged to be a first class exceeding area, the current density exceeding of the whole layout polygon of the first class exceeding area is described, aiming at the first class exceeding area shown in the figure 3, a potential highest point A and a potential lowest point B of the first class exceeding area are firstly determined, and current density average values of the first class exceeding area are calculated according to the point A and the point B shown in the figure 3;
the formula for calculating the average value of the current density of the first type of standard exceeding area is as follows:
in the formula, SeFor the area of the mesh division unit e, JeIs the current density of the mesh division unit e,
is the average value of the current density,
indicating a summation.
Step S4: increasing the area of the first class of exceeding area on the current layer according to the ratio of the current density average value of the first class of exceeding area to the current density allowable maximum value;
in the implementation process of the method, the area of the layout polygon of the first class of overproof area is increased by operating on the basis of changing the attribute of the mesh subdivision unit, and the operation needs to ensure that at least one layer of mesh subdivision unit with the insulating attribute exists between the increased copper-clad polygon and other copper-clad polygons.
The specific steps of increasing the area of the first-class superstandard area on the current layer are as follows:
step S4.1: calculating the average value J of the current density of the first class of standard exceeding areaaveAnd the maximum value J of the allowable current densitymaxThe ratio of (A) to (B):
(ii) a Calculating the initial area S of the layout polygon P in which the first class of overproof region is located according to the area calculation formula of the layout polygon0；
Step S4.2: for all grid subdivision cells e as boundary cells with copper-clad propertybndIf no such neighbor unit e existsnbrSaid neighbor unit enbrIs insulating, and the neighbor cell enbrIf all the vertexes of the graph are only positioned on the edge of the layout polygon P or in the insulating area, the area of the first class of superstandard area is increased unsuccessfully, an insufficient space mark is added, and the step S4.5 is carried out; neighbor cell e if there is an attribute of insulationnbrThen step S4.3 is performed; if the mesh division unit ebndThere are no neighbor cells with insulating property, the mesh division cell ebndIs no longer a boundary cell, cannot be subdivided based on the meshbndExpanding the first class of overproof areas; the filling material with the property that copper is covered as the grid subdivision unit is copper; the filling material with the property of insulating the grid subdivision unit is an insulating material; the neighbor unit of the mesh generation unit is a mesh generation unit which has a common edge with the mesh generation unit in all the mesh generation units; the boundary unit is a mesh generation unit with at least one edge being a polygon edge of the layout, or at least one neighbor unit is a mesh generation unit with different attributes from the boundary unit; the mesh division unit ebndAll the mesh-divided cells as boundary cells with the property of copper cladding are shown; the mesh division unit ebndDynamic updating;
step S4.3: the neighbor unit enbrIs set to be covered with copper, the neighbor unit enbrAdding the graph polygon P and the mesh generation unit e for updating the graph polygon PbndEdge-to-neighbor cell e correlated as a border cellnbrAssociated edge, the neighbor unit enbrBecoming a new border cell; the neighbor unit enbrIs added toIn the area of the layout polygon P in which the first class of superstandard area is positioned, S is usednewRepresenting the updated area of the layout polygon P;
step S4.4: comparing r with
If it is satisfied
If so, the area of the first class of overproof area is successfully increased, and the step S4.5 is carried out, otherwise, the step S4.2 is carried out;
S0is the initial area, S, of the layout polygon P in which the first class of superstandard region is locatednewRepresenting the updated area of the layout polygon P;
step S4.5: and the step of increasing the area of the first type exceeding area is finished.
Step S5: updating the current density average value of the first type of exceeding area, judging whether the area of the first type of exceeding area is successfully increased, if so, turning to the step S9, otherwise, turning to the step S6;
and judging whether the area of the first type of superstandard region is successfully increased or not according to an insufficient space identifier in the step S4.2, if the identifier indicates that the area is unsuccessfully increased, if the identifier does not indicate that the area is unsuccessfully increased, continuing to execute the step S4 until the area of the first type of superstandard region is successfully increased.
Step S6: setting Stotal=SnewJudging whether a layer with redundant space exists between the projections corresponding to the projection A and the projection B, if the layer with redundant space exists, turning to the step S7, otherwise, turning to the step S10, which means that the optimization of the area with overproof integrated circuit layout current density fails, and the optimization is finished, wherein the failure information can be marked in the embodiment, and then the optimization is finished; said StotalFor the increased total area, S, of the superscalar region of the first kindnewThe area of the first-class superscalar region after the increase is realized in step S4; the copper-clad polygon is a layout polygon with copper cladding property; the projection corresponding to the A and the B is the highest potential of the first-class overproof areaProjection of the point A and the potential lowest point B on all layers;
the layer with the redundant space is an insulation area which is not covered with copper at the corresponding projection positions of the layers A and B, and a line segment formed between the projections corresponding to the layers A and B is not intersected with the edge of any layout polygon, wherein the layout polygons are all polygons given by a user and used for describing an integrated circuit layout;
the via hole V for connecting the overproof area to the current layer is addedA, VBAdding a via hole V for communicating the layer of the first class overproof area and the layer with the redundant space at the projection position corresponding to A and BA, VB。
The layer with the redundant space is added with a through hole V capable of being communicatedA, VBThe concrete steps of the copper-clad polygon comprise:
step S7.1: the neighbors of the mesh generation unit are searched by adopting a neighbor search algorithm and are provided with through holes VATo the via hole VBSearching a mesh division unit with the insulating property, putting the searched mesh division unit with the insulating property into a set T, and converting the mesh division unit in the set T into a mesh division unit with the copper-clad property;
step S7.2: calculating the area of the grid subdivision unit with the property of covering copper in the set T to obtain the total area S of the area which equally divides the first class of overproof area currenttotal；
Step S7.3: increasing the mesh subdivision units in the set T according to the steps S7.1-S7.2 to increase the total area of the area bisecting the first type of overproof area current until the requirement is met
Or a neighboring unit with insulation property does not exist, and a through hole V capable of being communicated is added on a layer with redundant spaceA, VBThe step of covering the copper polygon is ended, S0The initial area of the layout polygon P where the first class of standard exceeding area is located is r is the ratio of the average value of the current density of the first class of standard exceeding area to the maximum value of the allowed current density.
The method for searching the neighbors of the mesh generation unit by adopting the neighbor search algorithm comprises the following specific steps:
step S7.1.1: set the vertex to contain the via hole VAThe mesh division unit is tAThe vertex comprises a via VBThe mesh division unit is tB(ii) a Setting a first variable t of a mesh generation unitALet t = tASetting a set T = { T }, setting a second variable previous of a mesh generation unit, and enabling the previous = T;
step S7.1.2: take i = rand (1, n)e) Taking m as the ith edge of the mesh division unit t; wherein rand (1, n)e) Represent 1 to neRandom integer of between, neThe number of edges of the mesh dividing unit t is shown; let t be the neighbor of t sharing the ith edge m with ti；
Step S7.1.3: if t isBIs not a neighbor that shares edge m with previous, and tBIf the position of the edge m is on both sides of previous, the step S7.1.4 is executed, otherwise, the step S7.1.5 is executed;
step S7.1.4: setting previous = t, t = tiIf t isiIs not in the set T, and TiAny vertex of (a) does not belong to any vertex of a copper-clad polygon, and t isiAdding the mixture into the set T; go to step S7.1.2;
step S7.1.5: if t isBInstead of a neighbor sharing an edge m with previous, set i = i +1 if i>neSetting i = 1; taking the ith edge with m as t, and setting the neighbor of t sharing the ith edge m with t as tiGo to S7.1.3; otherwise, if tBIf the neighbor shares the edge m with previous, go to step S7.1.6;
step S7.1.6: will tBAnd adding the mixture into the set T, and finishing.
Step S8: preferably, for the second-class overproof region, the local current density of the layout polygon of the second-class overproof region is indicated to be overproof, and the via hole closest to the maximum current density is defined as a via hole V, as shown by a point V in FIG. 3, which is the overproof current density at the via hole position caused by the current introduced by the via holes V of the layer and other layers; aiming at a second type of overproof area, taking a via hole V as a circle center, uniformly arranging 3-6 new via holes on a circumference with the radius r around the via hole V, wherein r is 5-50 times of the radius of the via hole V, the layers spanned by the newly-added via holes are the same as the via hole V, the distance between the new via holes is distributed as much as possible, the new via holes are outwards expanded under the possible condition, whether the expansion is reasonable is checked by judging whether the area current exceeds the standard, and the radius of the new via holes is set to be the same as V;
the number of the arranged through holes is less and better under the condition that the current density is not over standard, so that the processing cost can be reduced as much as possible, and the through holes V are shunted through new through holes.
Step S9: and obtaining a new circuit layout design model, and turning to the step S1.
And step S1 is carried out to recalculate the current density of the grid split unit in the new circuit layout design model and mark the area with the excessive current density again.
Step S10: and finishing the optimization. And finishing the optimization of the region with the overproof current density of the integrated circuit layout.
In a second aspect, the present application provides a system for optimizing an area with overproof integrated circuit layout current density, as shown in fig. 2, including: the system comprises a first module, a second module, a third module, a scheme 1 module, a scheme 2 module, a scheme 3 module, a fourth module, a fifth module, a sixth module and a seventh module, wherein the first module is respectively connected with the second module and the seventh module, the second module is respectively connected with the third module and the scheme 3 module, the fourth module is respectively connected with the fifth module and the sixth module, the fifth module is respectively connected with the scheme 2 module and the seventh module, the third module is connected with the scheme 1 module, the scheme 1 module and the scheme 2 module are respectively connected with the fourth module, and the sixth module is connected with the first module;
the first module is used for calculating the current density of the grid split unit in each layer of integrated circuit layout and judging whether a current density overproof area exists or not by calibrating the current density overproof area; if the current density exceeds the standard area, the second module is switched to; if no current density exceeds the standard area, the seventh module is switched to;
the second module is used for defining two types of current density exceeding areas according to the distribution rule of the current density exceeding areas and judging which type of exceeding areas the current density exceeding areas belong to; if the current density exceeding area is judged to be a first class exceeding area, the current density exceeding area is transferred to a third module; if the current density exceeding area is judged to be a second class exceeding area, executing a module of a scheme 3;
the third module is used for determining a potential highest point A and a potential lowest point B of the first-class overproof area and calculating a current density average value of the first-class overproof area;
the module in the scheme 1 is used for increasing the area of the first type exceeding area on the current layer according to the ratio of the average current density value of the first type exceeding area to the maximum allowable current density value;
the fourth module is used for updating the current density average value of the first class of standard exceeding area, judging whether the area of the first class of standard exceeding area is successfully increased, if so, turning to the sixth module, otherwise, turning to the fifth module;
the fifth module is used for setting Stotal=SnewJudging whether a layer with redundant space exists between the projections corresponding to the A and the B, if so, executing the module of the scheme 2, otherwise, turning to a seventh module; said StotalFor the increased total area, S, of the superscalar region of the first kindnewFor the increased area of the first-class overproof area realized by the module in the implementation scheme 1, the projections corresponding to the A and the B are projections of the highest potential point A and the lowest potential point B of the first-class overproof area on all layers;
the module of the scheme 2 is used for increasing a via hole V for communicating the superstandard area to the current layerA, VBAdding a via V capable of communicating with the layer having the redundant spaceA, VBThe copper-clad polygon; obtaining updated StotalGo to the fourth module; the copper-clad polygon is a layout polygon with copper cladding property;
the module in the scheme 3 is used for defining the via hole closest to the maximum current density as a via hole V, and uniformly arranging new via holes around the via hole V;
the sixth module is used for obtaining a new circuit layout design model and turning to the first module;
the seventh module is configured to end the optimization.
The present applicant has described and illustrated embodiments of the present invention in detail with reference to the accompanying drawings, but it should be understood by those skilled in the art that the above embodiments are merely preferred embodiments of the present invention, and the detailed description is only for the purpose of helping the reader to better understand the spirit of the present invention, and not for limiting the scope of the present invention, and on the contrary, any improvement or modification made based on the spirit of the present invention should fall within the scope of the present invention.
Claims (10)
1. An integrated circuit layout current density superstandard area optimization method is characterized by comprising the following steps:
step S1: calculating the current density of the grid split unit in each layer of integrated circuit layout, and judging whether a current density overproof area exists or not by calibrating the current density overproof area;
if the current density exceeds the standard area, the step S2 is executed;
if the current density does not exceed the standard, the step S10 is executed;
step S2: defining two types of current density exceeding areas according to the distribution rule of the current density exceeding areas, and judging which type of exceeding areas the current density exceeding areas belong to;
if the current density exceeding area is judged to be the first type exceeding area, the step S3 is executed;
if the current density exceeding area is judged to be the second type exceeding area, the step S8 is carried out;
step S3: determining a potential highest point A and a potential lowest point B of a first-class overproof area, and calculating a current density average value of the first-class overproof area;
step S4: increasing the area of the first class of exceeding area on the current layer according to the ratio of the current density average value of the first class of exceeding area to the current density allowable maximum value;
step S5: updating the current density average value of the first type of exceeding area, judging whether the area of the first type of exceeding area is successfully increased, if so, turning to the step S9, otherwise, turning to the step S6;
step S6: setting Stotal=SnewJudging whether a layer with redundant space exists between the projections corresponding to the A and the B, if so, turning to the step S7, otherwise, turning to the step S10; said StotalFor the increased total area, S, of the superscalar region of the first kindnewThe area of the first-class superscalar region after the increase is realized in step S4;
step S7: increasing a via hole V for communicating the overproof region to the current layerA, VBAdding a via V capable of communicating with the layer having the redundant spaceA, VBTo obtain updated StotalStep S5 is performed;
step S8: defining a via hole nearest to the maximum current density as a via hole V, and uniformly arranging new via holes around the via hole V;
step S9: obtaining a new circuit layout design model, and turning to the step S1;
step S10: and finishing the optimization.
2. The method for optimizing the region of the integrated circuit layout with the excessive current density according to claim 1, wherein the two types of regions with the excessive current density defined according to the distribution rule of the regions with the excessive current density comprise the following categories:
the first class of overproof areas are areas which comprise a complete polygon in an integrated circuit layout, and the current density of all mesh subdivision units in the areas exceeds the standard;
the second type of overproof area is a local area in a polygon contained in the integrated circuit layout, and the current density of the mesh subdivision unit in the local area only exceeds the standard in the polygon.
3. The method for optimizing the excessive current density area of the integrated circuit layout according to claim 1, wherein the formula for calculating the average value of the current density of the first excessive area is as follows:
in the formula, SeFor the area of the mesh division unit e, JeIs the current density of the mesh division unit e,
is the average value of the current density,
indicating a summation.
4. The method for optimizing the excessive current density area of the integrated circuit layout according to claim 1, wherein the specific step of increasing the area of the first excessive area on the current layer is as follows:
step S4.1: calculating the average value J of the current density of the first class of standard exceeding areaaveAnd the maximum value J of the allowable current densitymaxThe ratio of (A) to (B):
(ii) a Calculating the initial area S of the layout polygon P in which the first class of overproof region is located according to the area calculation formula of the layout polygon0；
Step S4.2: for all grid subdivision cells e as boundary cells with copper-clad propertybndIf no such neighbor unit e existsnbrSaid neighbor unit enbrIs insulating, and the neighbor cell enbrIf all the vertexes of the graph are only positioned on the edge of the layout polygon P or in the insulating area, the area of the first class of superstandard area is increased unsuccessfully, an insufficient space mark is added, and the step S4.5 is carried out; neighbor cell e if there is an attribute of insulationnbrThen step S4.3 is performed;
step S4.3: the neighbor unit enbrIs set to be covered with copper, the neighbor unit enbrAdding the polygon P into the layout, and updatingLayout polygon P and mesh subdivision unit ebndEdge-to-neighbor cell e correlated as a border cellnbrAssociated edge, the neighbor unit enbrBecoming a new border cell; the neighbor unit enbrAdding the area of the first class of standard exceeding area into the area of the layout polygon P in which the first class of standard exceeding area is positioned, and using SnewRepresenting the updated area of the layout polygon P;
step S4.4: comparing r with
If it is satisfied
If so, the area of the first class of overproof area is successfully increased, and the step S4.5 is carried out, otherwise, the step S4.2 is carried out;
step S4.5: and the step of increasing the area of the first type exceeding area is finished.
5. The method for optimizing an IC layout region with excessive current density according to claim 1, wherein the layer with the excessive space is added with a through hole V capable of being communicated withA, VBThe concrete steps of the copper-clad polygon comprise:
step S7.1: the neighbors of the mesh generation unit are searched by adopting a neighbor search algorithm and are provided with through holes VATo the via hole VBSearching a mesh division unit with the insulating property, putting the searched mesh division unit with the insulating property into a set T, and converting the mesh division unit in the set T into a mesh division unit with the copper-clad property;
step S7.2: calculating the area of the grid subdivision unit with the property of covering copper in the set T to obtain the total area S of the area which equally divides the first class of overproof area currenttotal；
Step S7.3: increasing the mesh subdivision units in the set T according to the steps S7.1-S7.2 to increase the total area of the area bisecting the first type of overproof area current until the requirement is met
Or a neighboring unit with insulation property does not exist, and a through hole V capable of being communicated is added on a layer with redundant spaceA，VBThe step of covering the copper polygon is ended, S0The initial area of the layout polygon P where the first class of standard exceeding area is located is r is the ratio of the average value of the current density of the first class of standard exceeding area to the maximum value of the allowed current density.
6. The method for optimizing the integrated circuit layout area with the excessive current density according to claim 5, wherein the neighbor search algorithm is adopted to search the neighbors of the mesh generation unit, and the method comprises the following specific steps:
step S7.1.1: set the vertex to contain the via hole VAThe mesh division unit is tAThe vertex comprises a via VBThe mesh division unit is tB(ii) a Setting a first variable t of a mesh generation unitALet t = tASetting a set T = { T }, setting a second variable previous of a mesh generation unit, and enabling the previous = T;
step S7.1.2: take i = rand (1, n)e) Taking m as the ith edge of the mesh division unit t; wherein rand (1, n)e) Represent 1 to neRandom integer of between, neThe number of edges of the mesh dividing unit t is shown; let t be the neighbor of t sharing the ith edge m with ti；
Step S7.1.3: if t isBIs not a neighbor that shares edge m with previous, and tBIf the position of the edge m is on both sides of previous, the step S7.1.4 is executed, otherwise, the step S7.1.5 is executed;
step S7.1.4: setting previous = t, t = tiIf t isiIs not in the set T, and TiAny vertex of (a) does not belong to any vertex of a copper-clad polygon, and t isiAdding the mixture into the set T; go to step S7.1.2;
step S7.1.5: if t isBInstead of a neighbor sharing an edge m with previous, set i = i +1 if i>neSetting i = 1; take the ith edge with m being tLet t be the neighbor of t sharing the ith edge m with tiGo to S7.1.3; otherwise, if tBIf the neighbor shares the edge m with previous, go to step S7.1.6;
step S7.1.6: will tBAnd adding the mixture into the set T, and finishing.
7. The method for optimizing the integrated circuit layout region with the excessive current density according to claim 1, wherein the layer with the excessive space is an insulating region without copper cladding at the projection positions corresponding to the layers A and B, and a line segment formed between the projections corresponding to the layers A and B is not intersected with the edge of any layout polygon.
8. The method for optimizing an IC layout region with excessive current density according to claim 1, wherein the via hole VA, VBAdding a via hole V for communicating the layer of the first class overproof area and the layer with the redundant space at the projection position corresponding to A and BA，VB。
9. The method for optimizing the area with the overproof current density of the integrated circuit layout according to claim 1, wherein the new via holes are uniformly distributed on a circumference with a radius r from a via hole V, the radius of the new via holes is the same as that of the via hole V, the number of the via holes is 3-6, and r is 5-50 times the radius of the via hole V.
10. An integrated circuit layout current density superstandard area optimization system is characterized by comprising: the system comprises a first module, a second module, a third module, a scheme 1 module, a scheme 2 module, a scheme 3 module, a fourth module, a fifth module, a sixth module and a seventh module, wherein the first module is respectively connected with the second module and the seventh module, the second module is respectively connected with the third module and the scheme 3 module, the fourth module is respectively connected with the fifth module and the sixth module, the fifth module is respectively connected with the scheme 2 module and the seventh module, the third module is connected with the scheme 1 module, the scheme 1 module and the scheme 2 module are respectively connected with the fourth module, and the sixth module is connected with the first module;
the first module is used for calculating the current density of the grid split unit in each layer of integrated circuit layout and judging whether a current density overproof area exists or not by calibrating the current density overproof area; if the current density exceeds the standard area, the second module is switched to; if no current density exceeds the standard area, the seventh module is switched to;
the second module is used for defining two types of current density exceeding areas according to the distribution rule of the current density exceeding areas and judging which type of exceeding areas the current density exceeding areas belong to; if the current density exceeding area is judged to be a first class exceeding area, the current density exceeding area is transferred to a third module; if the current density exceeding area is judged to be a second class exceeding area, executing a module of a scheme 3;
the third module is used for determining a potential highest point A and a potential lowest point B of the first-class overproof area and calculating a current density average value of the first-class overproof area;
the module in the scheme 1 is used for increasing the area of the first type exceeding area on the current layer according to the ratio of the average current density value of the first type exceeding area to the maximum allowable current density value;
the fourth module is used for updating the current density average value of the first class of standard exceeding area, judging whether the area of the first class of standard exceeding area is successfully increased, if so, turning to the sixth module, otherwise, turning to the fifth module;
the fifth module is used for setting Stotal=SnewJudging whether a layer with redundant space exists between the projections corresponding to the A and the B, if so, executing the module of the scheme 2, otherwise, turning to a seventh module; said StotalFor the increased total area, S, of the superscalar region of the first kindnewIncreased area of superscalar region of the first class implemented for execution of module of scheme 1
The module of the scheme 2 is used for increasing a via hole V for communicating the superstandard area to the current layerA, VBAdding a via V capable of communicating with the layer having the redundant spaceA, VBCoated with copperA polygon; obtaining updated StotalGo to the fourth module;
the module in the scheme 3 is used for defining the via hole closest to the maximum current density as a via hole V, and uniformly arranging new via holes around the via hole V;
the sixth module is used for obtaining a new circuit layout design model and turning to the first module;
the seventh module is configured to end the optimization.
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