CN114339994A - UWB chip and method for executing machine learning algorithm on chip - Google Patents

Abstract

The embodiment of the invention discloses a UWB chip and a method for executing a machine learning algorithm on chip; the UWB chip includes: a neural network computing part and an ARM processing core; wherein the neural network computing section is configured to read CIR data in an existing CIR memory on the UWB chip; calculating by using a trained neural network algorithm according to the CIR data to obtain a non-line-of-sight (NLOS) judgment value and correction data of a target corresponding to a UWB receiving signal; the ARM processing core is configured to correct the timestamp data transmitted from the existing timestamp calculation unit on the UWB chip according to the NLOS determination value and the correction data transmitted by the neural network calculation part, and obtain a corrected timestamp.

Description

UWB chip and method for executing machine learning algorithm on chip

Technical Field

The embodiment of the invention relates to the technical field of Ultra Wide Band (UWB) chip design, in particular to a UWB chip and a method for executing a machine learning algorithm on chip.

Background

Currently, a UWB radio-frequency chip includes two parts, namely a receiving path part and an emitting path part, and for the receiving path part, after receiving a UWB wireless signal, a receiving-end radio-frequency front-end circuit completes operations such as amplification and down-conversion of the UWB wireless signal; then, the UWB wireless signal subjected to amplification, down-conversion, and the like is converted from an Analog signal to a Digital signal by an Analog-to-Digital Converter (ADC), and sent to a reception demodulator. In a receiving demodulator, Data passes through a correlator, a preamble detector, a Start Frame Delimiter (SFD) detector, a Physical Layer Header (PHR) and a Physical Layer Service Data Unit (PSDU) decoder, and is decoded; then, the signals are sent to an ARM processor outside the chip through a Serial Peripheral Interface (SPI); meanwhile, Channel Impulse Response (CIR) and timestamp calculation are carried out in parallel with the processing process, and a timestamp result is also sent to an ARM processor outside the chip; when the CIR is calculated, the intermediate result of the calculation is stored in a CIR memory, the ARM processor reads CIR data from the CIR memory and sends the CIR data to a Personal Computer (PC) end, the neural network calculation is completed at the PC end, and the timestamp is corrected.

In the implementation process, the data amount in the CIR memory is 6KB, and the SPI speed is set to 20Mbps, then it takes at least 2.4ms for the ARM processor to read data from the CIR memory through the SPI interface, and the transmission time of the UWB data frame length is generally within 200 us. Therefore, in the current implementation process, the time for reading the CIR memory by the ARM processor is far longer than the time for transmitting the UWB data frame, so that the whole UWB communication system is limited to process data offline and cannot perform machine learning calculation in real time, and the positioning delay is increased.

Disclosure of Invention

In view of the above, the embodiments of the present invention are directed to providing an UWB chip and method for executing a machine learning algorithm on chip; the neural network calculation related to machine learning can be completed on line in the UWB chip, and data in the CIR memory does not need to be transmitted to a PC (personal computer) through an ARM (advanced RISC machine) processor, so that the time stamp correction can be completed on the chip in real time, and the positioning delay is reduced.

The technical scheme of the embodiment of the invention is realized as follows:

in a first aspect, an embodiment of the present invention provides an UWB chip for executing a machine learning algorithm on chip, where the UWB chip includes: a neural network computing part and an ARM processing core;

the neural network computing part is configured to read CIR data in an existing CIR memory on the UWB chip; calculating by using a trained neural network algorithm according to the CIR data to obtain a non-line-of-sight (NLOS) judgment value and correction data of a target corresponding to a UWB receiving signal;

the ARM processing core is configured to correct the timestamp data transmitted from the existing timestamp calculation unit on the UWB chip according to the NLOS determination value and the correction data transmitted by the neural network calculation part, and obtain a corrected timestamp.

In a second aspect, an embodiment of the present invention provides a method for executing a machine learning algorithm on chip, where the method is applied to the UWB chip in the first aspect, and the method includes:

reading CIR data in an existing CIR memory on the UWB chip through a neural network computing part in the UWB chip;

calculating by the neural network calculating part according to the CIR data by using a trained neural network algorithm to obtain a non-line-of-sight (NLOS) judgment value and correction data of a target corresponding to a UWB receiving signal;

and correcting the timestamp data transmitted from the existing timestamp calculation unit on the UWB chip by an ARM processing core in the UWB chip according to the NLOS judgment value and the correction data transmitted by the neural network calculation part to obtain the corrected timestamp.

The embodiment of the invention provides a UWB chip and a method for executing a machine learning algorithm on chip; by integrating the neural network computing part and the ARM processing core in the UWB chip, machine learning computation can be completed on a chip, data on the chip does not need to be transmitted to the outside of the chip, data transmission rate is improved, processing delay and positioning delay are reduced, and real-time high-precision positioning can be achieved compared with the conventional scheme.

Drawings

FIG. 1 is a schematic diagram of an exemplary UWB chip and peripheral circuit architecture in a conventional scheme;

FIG. 2 is a schematic diagram illustrating an on-chip UWB chip for executing a machine learning algorithm according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a neural network model according to an embodiment of the present invention;

FIG. 4 is a schematic diagram illustrating a UWB chip configured to execute a machine learning algorithm in a chip according to another embodiment of the invention;

FIG. 5 is a schematic diagram of an exemplary structure of a neural network computing unit provided in an embodiment of the present invention;

fig. 6 is a schematic diagram illustrating an exemplary network system according to an embodiment of the present invention;

fig. 7 is a flowchart illustrating a method for executing a machine learning algorithm on a chip according to an embodiment of the present invention.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

Referring to fig. 1, an exemplary UWB chip and peripheral circuit architecture schematic in a currently conventional scenario is shown. Fig. 1 includes a UWB chip 100, an ARM processor 200, and a PC 300 that performs offline neural network computations. For a UWB chip, as shown by the dashed box, a receive path portion 11, a transmit path portion 12, and an SPI interface 13 for data transmission with the outside of the chip are included.

For the receive path portion 11 shown in fig. 1, based on the signal flow trend of the received signal, it may in turn include: a receiving-end antenna 110, a receiving-end radio frequency front-end circuit 111, an ADC 112, a correlator 113, a preamble detector 114, an SFD detector 115, a PHR & PSDU decoder 116, a CIR calculation unit 117, a timestamp calculation unit 118, and a CIR memory 119; in detail, as shown in fig. 1, the correlator 113, the preamble detector 114, the SFD detector 115, the PHR & PSDU decoder 116, the CIR calculation unit 117, the time stamp calculation unit 118, and the CIR memory 119 constitute a reception demodulator in the reception path section 11.

For the transmit path segment 12 shown in fig. 1, based on the signal flow trend of the transmit signal, it may in turn include: a transmit demodulator 120, a Digital-to-Analog Converter (DAC) 121, a transmit front-end circuit 122, and a transmit antenna 123. Based on the above exemplary composition of the transmit path portion 12 as shown in fig. 1, in some examples, after receiving the transmit data to be transmitted by the ARM processor 200 through the SPI interface 13, the transmit data is modulated by the transmit modulator 120; then, after the modulated transmission data is converted into an analog transmission signal by the DAC 121, the analog transmission signal is filtered and amplified by the transmission rf front-end circuit 122, and finally radiated to a free space through the transmission antenna 123.

Based on the above-mentioned exemplary composition structure of the receiving path portion 11 shown in fig. 1, in some examples, after receiving the UWB wireless signal, the receiving-end antenna 111 completes operations of amplification, down-conversion, and the like on the UWB wireless signal through the receiving-end rf front-end circuit 111; then, the UWB wireless signal after the above operations of amplification, down-conversion, and the like is converted from an analog signal to a digital signal by the ADC 112, so that reception data is obtained and sent to the reception demodulator. In the receiving demodulator, the received data sequentially passes through the correlator 113, the preamble detector 114, the SFD detector 115 and the PHR & PSDU decoder 116 for decoding, and the decoded received data is sent to the ARM processor 200 outside the chip through the SPI interface 13; meanwhile, in parallel with the above processing, after the received data is processed by the correlator 113, the received data sequentially passes through the CIR calculation unit 117 and the timestamp calculation unit 118 to perform CIR calculation and timestamp calculation, respectively, and finally obtained timestamp data is sent to the ARM processor 200 outside the chip through the SPI interface 13; in addition, while CIR calculation is performed, an intermediate result of the calculation, that is, CIR data, needs to be stored in the CIR memory, so that the ARM processor 200 also reads the CIR data from the CIR memory 119 through the SPI interface 13 and transmits the CIR data to the PC 300, and the PC 300 can complete neural network calculation based on the CIR data and correct the time stamp data calculated by the time stamp calculating unit 118.

Based on the UWB chip and the peripheral circuit architecture shown in fig. 1, in the conventional scheme, during the time stamp data correction process, data obtained in the UWB chip needs to be transmitted to the external ARM processor 200 and the PC 300 through the SPI interface 13 to perform offline neural network calculation. This section states that the data transmission involved in the content typically takes up to milliseconds, but the UWB data frame is typically transmitted within the chip for 200 us. Therefore, the time consumption for transmitting the data in the UWB chip to the outside is much longer than the transmission time of the UWB data frame in the chip, which increases the delay for performing high-precision positioning, and thus real-time high-precision positioning cannot be realized. Based on this, the embodiment of the invention is expected to realize the neural network calculation related to machine learning in the UWB chip, and reduce the data transmission between the chip and the outside, thereby reducing the positioning delay and realizing real-time high-precision positioning.

Based on the above explanation, referring to fig. 2, which shows the composition of an on-chip UWB chip 20 for executing a machine learning algorithm according to an embodiment of the present invention, as can be seen from fig. 2, the UWB chip 20 includes a neural network computing section 21 and an ARM processing core 22, in addition to a receiving path section 11, which is comprised of a receiving-end antenna 110, a receiving-end rf front-end circuit 111, an ADC 112, a correlator 113, a preamble detector 114, an SFD detector 115, a PHR & PSDU decoder 116, a CIR computing unit 117, a timestamp computing unit 118 and a CIR memory 119, and a transmitting path section 12, which is comprised of a transmitting demodulator 120, a DAC 121, a transmitting-end front-end circuit 122 and a transmitting-end antenna 123, which are included in the UWB chip 100 in fig. 1; for the neural network calculating section 21, configured to read CIR data in the CIR memory 119; calculating by using a trained neural network algorithm according to the CIR data to obtain a Non-Line-Of-Sight (NLOS) judgment value and correction data Of a target corresponding to the UWB receiving signal;

the ARM processing core 22 is configured to correct the time stamp data transmitted from the time stamp calculating unit 118 according to the NLOS determination value and the correction data transmitted by the neural network calculating part 21, obtaining a corrected time stamp.

Through the structure shown in fig. 2, the neural network computing part 21 and the ARM processing core 22 are integrated inside the UWB chip 20, so that machine learning computation can be completed on chip without transmitting data on chip to the outside of the chip, the data transmission rate is increased, the processing delay and the positioning delay are reduced, and real-time high-precision positioning can be realized compared with the conventional scheme.

With respect to the structure shown in fig. 2, in some examples, since the ARM processing core 22 is included in the structure shown in fig. 2, compared with the structure shown in fig. 1, the decoded received data obtained by decoding by the PHR & PSDU decoder 116 and the timestamp data obtained by calculating by the timestamp calculating unit 118 do not need to be transmitted through an external interface. In the embodiment of the present invention, the remaining components (such as the PHR & PSDU decoder 116, the transmission modulator 120, the CIR memory 119, and other components in the UWB chip 20 that need to interact with the ARM processing core 22) may interact with the ARM processing core 22 through a system-on-chip Bus, such as an Advanced High performance Bus (AHB), so as to increase the data transmission rate and reduce the positioning delay.

With the configuration shown in fig. 2, in some examples, the neural network computing section 21 preferably reads the CIR data directly from the CIR Memory 119 by way of Direct Memory Access (DMA). It can be understood that, in an implementation environment with a data width of 192 bits and a frequency of 125MHz clock, the read bandwidth of the DMA can reach 24Gbps, which is about 1000 times that of the current conventional scheme, and therefore, after the neural network computing part 21 is integrated in the UWB chip, the transmission time of the CIR data is no longer a bottleneck of a long time consumed by positioning of the UWB system.

With the configuration shown in fig. 2, in some examples, since the CIR data needs to be transmitted to the neural network computing section 21 and the ARM processing core 22, unlike the configuration shown in fig. 1, the CIR memory 119 may be disposed outside the receiving demodulator, thereby facilitating data reading by the neural network computing section 21 by way of DMA.

In conjunction with the structure shown in fig. 2, the neural network computing section 21 is integrated on the UWB chip, and therefore, a neural network model for performing machine learning needs to be configured, and functionally, the structure of the neural network model used in the embodiment of the present invention is shown by a dashed box in fig. 3, and may sequentially include: input layer, convolutional layer, pooling layer, convolutional layer, full-link layer and output layer. In detail, CIR data is input to the neural network model through the input layer, and finally an NLOS determination value and correction data are output through calculation operations such as convolution, pooling, full connection, and the like. In the specific implementation process, model descriptions such as the topology of each layer, the size of the convolution kernel, and the size of the weight can be determined by the model training result. Further, for the functional implementation of the neural network model, the core is to multiply CIR data and weight and then perform an accumulation operation, and therefore, referring to fig. 4, the neural network calculating part 21 includes: a weight memory 211 and a neural network calculation unit 212; in detail, the weight memory 211 may receive and store the weight data transmitted by the ARM processor 22, and may also transmit the stored weight data to the neural network computing unit 212, and it can be understood that the weight data may be obtained by training the neural network model in advance; the neural network computing unit 212 is configured to compute through the trained neural network model by using the CIR data and the weight data to obtain an NLOS decision value and correction data.

It is understood that the core of the neural network model is a computational array consisting of a plurality of multipliers and adders. Thus, for the above example, in a specific implementation, referring to fig. 4, the neural network computing unit 212 may include: CIR data buffer 2121, multiply-accumulate calculation array 2122, weight buffer 2123, calculation controller 2124, and calculation result buffer 2125; wherein, the CIR data buffer 2121 is configured to buffer CIR data received from the CIR memory 119 based on the scheduling of the operation controller 2124, and transmit the buffered CIR data to the multiply-accumulate calculation array 2122; the weight buffer 2123 is configured to buffer the weight data received from the weight memory 211 based on the scheduling of the operation controller 2124, and transmit the buffered weight data to the multiply-accumulate calculation array 2122; a multiply-accumulate calculation array 2122 configured to perform a multiply-accumulate operation on the received CIR data and weight data based on the scheduling of the operation controller 2124 to obtain an operation result including an NLOS decision value and correction data, and transmit the operation result to the calculation result buffer 2125 for buffering; the calculation result buffer 2125 is configured to transmit the buffered calculation result (i.e., the NLOS decision value and the correction data shown in fig. 2 or 4) to the ARM processing core 22 based on the scheduling of the calculation controller 2124.

Specifically, taking the exemplary structure of the neural network computing unit 212 shown in fig. 5 as an example, the multiply-accumulate computing array 2122 is composed of a 3 × 3 multiply-add device, and after receiving one frame of data, the receiving demodulator transfers CIR data and weight data of the data amount required for current computation from the CIR memory 119 and the weight memory 211 to the CIR data buffer 2121 and the weight buffer 2123, respectively, under the scheduling of the operation controller 2124; then, the multiply-accumulate calculation array 2122 reads the three CIR data paths and the three weight data paths in the CIR data buffer 2121 and the weight buffer 2123 respectively under the scheduling of the calculation controller 2124, and performs multiply-accumulate calculation respectively, and the three calculation results after the calculation are stored in the calculation result buffer 2125. After completing one operation, the operation controller 2124 may obtain CIR data and weight data required for the next calculation according to the foregoing procedure, and then perform multiply-accumulate operation. Such operations are repeated until the calculation of the frame data is completed, that is, the calculation of each function of the whole neural network model is completed, and the final calculation result is output to be read by the ARM processing core 22.

In conjunction with the structures shown in fig. 2 and 4, in some examples, the neural network model in the neural network computing section 21 or the neural network computing unit 212 needs to be trained and parameter configured in advance. In the embodiment of the present invention, training and parameter configuration for a neural network model generally need to be completed by means of an external training server, and with reference to fig. 4, the receiving demodulator further includes a feature value memory 23 configured to store feature value data corresponding to the edge UWB device obtained according to a set feature value type in a signal receiving process; wherein the feature value types include: receiving the distance, the amplitude of the first reaching path, the amplitude of the first harmonic of the first reaching path, the amplitude of the second harmonic of the first reaching path, the amplitude of the third harmonic of the first reaching path, the accumulation times of Preamble, the energy estimation of the first reaching path, the energy estimation of a receiving signal RX, the noise estimation and the maximum value of noise calculated in a demodulator;

the characteristic value data is transmitted to the ARM processing core 22, so that the ARM processing core 22 sends the characteristic value data and the CIR data read from the CIR memory 119 to the server side through the UWB wireless link, so that the server side trains the neural network model according to the characteristic value data and the CIR data.

For the above example, in particular, since the training process of the neural network model is usually performed outside the chip or even at the server side outside the UWB device, the network system architecture required for the specific training is shown in fig. 6. In detail, referring to fig. 4 and 6, the UWB chip 20 is configured to be disposed in the edge UWB device, and since the training of the neural network model requires the feature value data described in the above example, in the implementation, the edge UWB device calculates the feature value during the process of receiving one frame of data, and stores the feature value data in the feature value storage 23 after the data frame is received. The ARM processing core 22 will read the characteristic value data in the characteristic value storage 23 and the CIR data in the CIR storage 119, and it can be understood that, in the implementation process, the data can be transmitted through a system-on-chip bus such as an AHB bus; then, the edge UWB device sends the characteristic value data and the CIR data to a server side through a UWB wireless link, which may be specifically a server-side UWB device; finally, the UWB equipment at the server end sends the characteristic value data and the CIR data to a training server with strong computing capacity through a communication network or other transmission modes to train the neural network.

After the training of the training server is completed, the training server issues the weight data of the neural network model obtained by training to the UWB device at the server end, and then the UWB device at the server end is sent to each edge UWB device through a UWB wireless link, and the UWB chip 20 in the edge UWB device stores the weight in the weight memory 211 through the ARM processing core 22 for the neural network computing part 212 to use in the process of executing the neural network computing, thereby completing the configuration operation of the neural network model in the chip 20, and completing the training and configuration work of the neural network model.

With the above-described arrangement, in detail, the UWB chip 20 shown in fig. 2 or fig. 4 is set to the edge UWB device, and in the process that the edge UWB device receives one frame of data, CIR data can be calculated and obtained by the CIR calculation unit 117 in the chip 20 and stored in the CIR memory 119. After receiving one frame of data, the chip 20 may turn on the neural network computing unit 212. The CIR data is DMA-transmitted to a CIR data buffer 2121 in the neural network computing unit 212, and the weights stored in the weight memory 211 are also transmitted to a weight buffer 2123; then, the neural network calculation such as convolution, pooling, full connection and the like is completed through the configured neural network model, so that the judgment result and the correction data of whether the NLOS is the non-line-of-sight are obtained, and the judgment result and the correction data are sent to the ARM processing core 22. The ARM processing core 22 corrects the timestamp data calculated by the timestamp calculation unit 118 in the receiving demodulator by combining the NLOS determination result and the correction data, thereby obtaining a more accurate ranging result. For example, regarding the timestamp correction method and the neural network, generally, it is preferable to subtract the correction data from the timestamp data to obtain the corrected timestamp data, although more complicated correction may be performed in combination with other statistical methods. Since the measured distance error is equal to the time error times the speed of light: Δ S = Δ t × c, the time error is reduced by correcting the time stamp data, and the accuracy of distance measurement and the accuracy of positioning are improved.

Based on the same inventive concept of the foregoing technical solution, referring to fig. 7, a method for executing a machine learning algorithm on chip according to an embodiment of the present invention is shown, where the method may be applied to the UWB chip 20 structure shown in fig. 2 or fig. 4, and the method may include:

s701: reading CIR data in an existing CIR memory on the UWB chip through a neural network computing part in the UWB chip;

s702: calculating by the neural network calculating part according to the CIR data by using a trained neural network algorithm to obtain a non-line-of-sight (NLOS) judgment value and correction data of a target corresponding to a UWB receiving signal;

s703: and correcting the timestamp data transmitted from the existing timestamp calculation unit on the UWB chip by an ARM processing core in the UWB chip according to the NLOS judgment value and the correction data transmitted by the neural network calculation part to obtain the corrected timestamp.

With respect to the above scheme, in some examples, as shown in fig. 4, the neural network computing section includes: a weight memory and a neural network computing unit; correspondingly, the calculating according to the CIR data by using the trained neural network algorithm to obtain the non-line-of-sight NLOS decision value and the correction data of the target corresponding to the UWB received signal includes:

receiving and storing the weight data transmitted by the ARM processing core through the weight memory; transmitting the stored weight data to the neural network computing unit;

and calculating by the neural network calculating unit through the trained neural network model by using the CIR data and the weight data to obtain the NLOS judgment value and the correction data.

With respect to the above scheme, in some examples, as shown in fig. 4, the neural network computing unit includes: CIR data buffer, multiply accumulate calculate array, weight buffer, operation controller and calculate result buffer; correspondingly, the obtaining the NLOS determination value and the correction data by calculating, by the neural network calculating unit, the CIR data and the weight data through a trained neural network model includes:

buffering CIR data received from the CIR memory through the CIR data buffer based on the scheduling of the operation controller, and transmitting the CIR data to the multiply-accumulate calculation array;

buffering the weight data received from the weight memory through the weight buffer based on the scheduling of the operation controller, and transmitting the weight data to the multiply-accumulate calculation array;

performing multiply-accumulate operation on the received CIR data and the weight data through the multiply-accumulate calculation array based on the scheduling of the operation controller to obtain an operation result comprising an NLOS (non-linear operating system) judgment value and correction data, and transmitting the operation result to the calculation result buffer for caching;

transmitting the cached operation result to the ARM processing core through the calculation result cache based on scheduling of the operation controller.

With respect to the above, in some examples, as shown in fig. 4, the UWB chip further includes a feature value memory; accordingly, the method further comprises:

storing corresponding characteristic value data obtained by the edge UWB equipment according to a set characteristic value type in a signal receiving process through the characteristic value memory; wherein the feature value types include: receiving the distance, the amplitude of the first reaching path, the amplitude of the first harmonic of the first reaching path, the amplitude of the second harmonic of the first reaching path, the amplitude of the third harmonic of the first reaching path, the accumulation times of Preamble, the energy estimation of the first reaching path, the energy estimation of a receiving signal RX, the noise estimation and the maximum value of noise calculated in a demodulator;

and transmitting the characteristic value data to the ARM processing core through the characteristic value memory so that the ARM processing core can transmit the characteristic value data and the CIR data read from the CIR memory to a server end through a UWB wireless link, so that the server end trains the neural network model according to the characteristic value data and the CIR data.

It should be understood that the above exemplary technical solution of the method for executing a machine learning algorithm on a chip belongs to the same concept as the above technical solution of the UWB chip 20 for executing a machine learning algorithm on a chip shown in fig. 2 or fig. 4, and therefore, the details of the above technical solution of the method for executing a machine learning algorithm on a chip, which are not described in detail, can be referred to the above description of the technical solution of the method for executing a machine learning algorithm on a chip 20 shown in fig. 2 or fig. 4. The embodiments of the present invention will not be described in detail herein.

It should be noted that: the technical schemes described in the embodiments of the present invention can be combined arbitrarily without conflict.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (10)

1. An UWB chip for executing a machine learning algorithm on chip, the UWB chip comprising: a neural network computing part and an ARM processing core; wherein the content of the first and second substances,

the neural network computing part is configured to read CIR data in an existing CIR memory on the UWB chip; calculating by using a trained neural network algorithm according to the CIR data to obtain a non-line-of-sight (NLOS) judgment value and correction data of a target corresponding to a UWB receiving signal;

the ARM processing core is configured to correct the timestamp data transmitted from the existing timestamp calculation unit on the UWB chip according to the NLOS determination value and the correction data transmitted by the neural network calculation part, and obtain a corrected timestamp.

2. The UWB chip of claim 1 wherein components on the UWB chip that need to interact with the ARM processing core through a system-on-chip bus.

3. The UWB chip according to claim 1, wherein the neural network computing section is configured to read the CIR data directly from the CIR memory by means of direct memory access DMA.

4. The UWB chip according to claim 1, wherein the CIR memory is disposed outside a reception demodulator in the UWB chip.

5. The UWB chip according to claim 1, wherein the neural network calculating section includes: a weight memory and a neural network computing unit;

the weight memory is used for receiving and storing weight data transmitted by the ARM processing core; and transmitting the stored weight data to the neural network computing unit;

the neural network computing unit is configured to utilize the CIR data and the weight data to perform computation through a trained neural network model to obtain the NLOS judgment value and the correction data.

6. The UWB chip of claim 5 wherein the neural network computation unit comprises: CIR data buffer, multiply accumulate calculate array, weight buffer, operation controller and calculate result buffer; wherein the content of the first and second substances,

the CIR data buffer is configured to buffer CIR data received from the CIR memory based on the scheduling of the operation controller and transmit the CIR data to the multiply-accumulate calculation array;

the weight buffer is configured to buffer the weight data received from the weight memory based on the scheduling of the operation controller, and transmit the weight data to the multiply-accumulate calculation array;

the multiply-accumulate calculation array is configured to perform multiply-accumulate calculation on the received CIR data and the weight data based on the scheduling of the calculation controller to obtain a calculation result comprising an NLOS (non-line-of-sight) judgment value and correction data, and transmit the calculation result to the calculation result buffer for buffering;

the compute result buffer configured to transmit the buffered compute results to the ARM processing core based on scheduling by the compute controller.

7. The UWB chip according to claim 1, wherein the UWB chip further comprises an eigenvalue memory configured to:

the storage edge UWB equipment acquires corresponding characteristic value data according to the set characteristic value type in the signal receiving process; wherein the feature value types include: receiving the distance, the amplitude of the first reaching path, the amplitude of the first harmonic of the first reaching path, the amplitude of the second harmonic of the first reaching path, the amplitude of the third harmonic of the first reaching path, the accumulation times of Preamble, the energy estimation of the first reaching path, the energy estimation of a receiving signal RX, the noise estimation and the maximum value of noise calculated in a demodulator;

and transmitting the characteristic value data to the ARM processing core so that the ARM processing core can transmit the characteristic value data and the CIR data read from the CIR memory to a server side through a UWB wireless link, and the server side can train the neural network model according to the characteristic value data and the CIR data.

8. The UWB chip according to claim 7, wherein the eigenvalue memory is provided in a reception demodulator in the UWB chip.

9. A method of executing a machine learning algorithm on chip, the method being applied to the UWB chip of any one of claims 1 to 8, the method comprising:

reading CIR data in an existing CIR memory on the UWB chip through a neural network computing part in the UWB chip;

calculating by the neural network calculating part according to the CIR data by using a trained neural network algorithm to obtain a non-line-of-sight (NLOS) judgment value and correction data of a target corresponding to a UWB receiving signal;

and correcting the timestamp data transmitted from the existing timestamp calculation unit on the UWB chip by an ARM processing core in the UWB chip according to the NLOS judgment value and the correction data transmitted by the neural network calculation part to obtain the corrected timestamp.

10. The method of claim 9, wherein the neural network computing portion comprises: a weight memory and a neural network computing unit; correspondingly, the calculating according to the CIR data by using the trained neural network algorithm to obtain the non-line-of-sight NLOS decision value and the correction data of the target corresponding to the UWB received signal includes:

receiving and storing the weight data transmitted by the ARM processing core through the weight memory; transmitting the stored weight data to the neural network computing unit;

and calculating by the neural network calculating unit through the trained neural network model by using the CIR data and the weight data to obtain the NLOS judgment value and the correction data.

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